N-type lateral device and preparation method thereof

Abstract

The present invention discloses an N-type lateral device and a preparation method thereof. Based on the traditional lateral double-diffused metal oxide semiconductor, the device adds another set of gates and current paths. Through the collaborative control of the lower polysilicon gate and the upper polysilicon gate, two parallel source-drain current paths are formed. At the same time, a floating P-type silicon layer is embedded in the N⁻ silicon layer, and at the same breakdown voltage, the doping concentration of the N⁻ silicon layer can be increased, thereby further reducing the on-resistance of the device. In the preparation method, processes such as Si-SiO₂ bonding, ion implantation, plasma etching, atomic layer deposition, and thermal oxide layer growth are used to prepare the device, and its preparation process is compatible with the standard CMOS process. Under the same chip area, the current density of the device of the present invention is increased to more than twice that of the traditional LDMOS. At the same time, the design of the lower layer of silicon dioxide is easy to achieve complete isolation between devices, improving the high-temperature stability and radiation resistance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to an N-type lateral device and a preparation method thereof. Background Art

[0002] High-voltage power devices are core components of power electronic systems and are widely used in industrial motor drives, new energy generation, electric vehicles, aerospace, smart grids and other fields. As power electronic technology develops towards high efficiency, integration and high frequency, higher requirements are placed on the performance of power devices: on the one hand, they need to withstand hundreds of volts of high-voltage blocking capability, and on the other hand, they need to achieve low-loss high-current transmission when turned on. However, traditional high-voltage lateral devices (such as lateral double-diffused metal oxide semiconductor devices LDMOS, lateral insulated gate bipolar transistors LIGBT, etc.) face severe challenges in the coordinated optimization of high voltage and high current density, which has become a key bottleneck restricting the improvement of system efficiency. Traditional LDMOS devices share high voltage through the resistance of the lateral drift region, but their on-resistance increases exponentially with the square of the breakdown voltage. Therefore, how to reduce the on-resistance of the device while meeting the breakdown voltage required by the system has always been an eternal pursuit. In addition, although LIGBT devices reduce the on-voltage drop through conductivity modulation, their slow turn-off speed and large tail current limit the increase in switching frequency, and the device structure is complex and reliability issues are prominent. In recent years, lateral devices based on SiC and GaN wide bandgap semiconductors have attracted much attention due to their excellent breakdown field strength and electron mobility, but their high-voltage capabilities are limited by material defects and surface trap effects, and the thermal effect is significant under high current density, resulting in dynamic resistance degradation. In addition, although SiC lateral devices have high-temperature stability, they are limited by heteroepitaxial growth technology and high-cost processes, making it difficult to achieve large-area uniform manufacturing, making it difficult to prepare large-scale power integrated circuits. Summary of the invention

[0003] Purpose of the invention: The purpose of the present invention is to provide an N-type lateral device and a preparation method, so as to reduce the on-resistance of the device under the condition of the same chip area and reduce the area of ​​the power integrated circuit designed based on the device.

[0004] Technical solution: An N-type lateral device, a lower silicon dioxide layer is provided on the substrate, a window is etched on the lower silicon dioxide layer and filled with polysilicon to form a lower polysilicon gate; a lower gate oxide layer is provided on the lower silicon dioxide layer and the lower polysilicon gate, and a source metal layer, a second N + Silicon layer, P — Silicon layer, N — Silicon layer, first N + silicon layer and drain metal layer, the P — The silicon layer is disposed at a position corresponding to the lower polysilicon gate;

[0005] In N — A field oxide layer is provided on the silicon layer; — Silicon layer, first N + The silicon layer and the second N + The upper surface of the silicon layer, the upper surface of the field oxide layer and both sides are provided with an upper gate oxide layer; on the upper gate oxide layer, corresponding to P — An upper polysilicon gate is provided above the silicon layer;

[0006] The upper polysilicon gate and the lower polysilicon gate serve as the upper polysilicon gate and the lower polysilicon gate of the device respectively; when the upper and lower polysilicon gates are turned on at the same time, — An upper conductive channel is formed between the upper silicon layer and the upper gate oxide layer, corresponding to the position of the upper polysilicon gate. — A lower conductive channel is formed between the lower part of the silicon layer and the lower gate oxide layer, corresponding to the position of the lower polysilicon gate, and correspondingly forms two upper and lower current paths between the source and the drain.

[0007] Further, in N — A floating P-type silicon layer is provided in the silicon layer, and the doping concentration of the floating P-type silicon layer is N — 0.5~2 times the doping concentration of the silicon layer.

[0008] Furthermore, the floating P-type silicon layer is — Located in the center of the silicon layer.

[0009] Furthermore, the lower gate oxide layer, the field oxide layer and the upper gate oxide layer are silicon dioxide layers respectively.

[0010] Furthermore, the thickness of the lower silicon dioxide layer and the field oxide layer are both 2000nm-3000nm, the thickness of the lower polysilicon gate and the upper polysilicon gate are both 1500nm, and the thickness of the lower gate oxide layer and the upper gate oxide layer are both 15nm-30nm.

[0011] Furthermore, the second N + Silicon layer, P — Silicon layer, N — Silicon layer, first N + The thickness of the silicon layer is the same as that of the N — The length of the silicon layer is 5 μm to 50 μm, the thickness is 1500 nm to 8000 nm, and the doping concentration is 1.0×10 16 ~1.0×10 18 / cm 3 .

[0012] Further, P — The doping concentration of the silicon layer is 1.0×10 17 ~1.0×10 19 / cm 3, the first N + The silicon layer and the second N + The doping concentration of the silicon layer is 1.0×10 20 ~1.0×10 21 / cm 3 , the doping concentration of the substrate is 1.0×10 15 ~1.0×10 16 / cm 3 .

[0013] Furthermore, the source metal layer and the drain metal layer are made of the same material, tungsten, aluminum, or copper.

[0014] The first method for preparing an N-type lateral device is used to prepare a lateral device provided with a floating P-type silicon layer, comprising the following steps:

[0015] SA1, prepare the doped substrate;

[0016] SA2, growing a silicon dioxide layer on the substrate to form a lower silicon dioxide layer;

[0017] SA3, etching a window in the lower silicon dioxide layer;

[0018] SA4, filling the etched window with polysilicon to form a lower polysilicon gate;

[0019] SA5, using atomic layer deposition, a thin layer of silicon dioxide is prepared on the lower silicon dioxide layer and the lower polysilicon gate to form a lower gate oxide layer;

[0020] SA6, through Si-SiO 2 Bonding process, bonding a layer of N on the lower gate oxide layer — Silicon, forming the lower N — Silicon layer;

[0021] SA7, I am N — Into the silicon layer, boron is ion-implanted to form a boron ion-implanted layer;

[0022] SA8, under N — A layer of N is grown on top of the silicon layer. — Silicon layer, upper N — Silicon layer and lower N — The concentration and thickness of the silicon layer are the same, and thermal diffusion is performed to form a floating P-type silicon layer centered above and below;

[0023] SA9, I am N — Silicon layer and upper N — Boron ions are implanted into the silicon layer at the position above the lower polysilicon gate through an ion implantation process, and after diffusion, P — Silicon layer;

[0024] SA10, on N — A silicon dioxide layer is grown on the silicon layer as a field oxide layer;

[0025] SA11, on N — Silicon layer, P — A thin layer of silicon dioxide is grown on the silicon layer and the field oxide layer to form an upper gate oxide layer;

[0026] SA12, on the upper gate oxide layer, corresponding to P — Depositing polysilicon on the silicon layer to form an upper polysilicon gate;

[0027] SA13, under N — Silicon layer and upper N — On one side of the silicon layer, the lower N — Silicon layer and upper N — The other side of the silicon layer, P — The silicon layer is away from the floating P-type silicon layer, and the lower N — Silicon layer and upper N — Arsenic ions are implanted into the silicon layer through an ion implantation process, and the first N + The silicon layer and the second N + Silicon layer;

[0028] SA14, plasma etching both sides N + Silicon layer;

[0029] SA15, through the metal filling process, in the first N + The silicon layer and the second N + A drain metal layer and a source metal layer are respectively formed on one side of the silicon layer, and finally a complete drain and source are formed.

[0030] The second method for preparing an N-type lateral device is used to prepare a lateral device provided with a floating P-type silicon layer, comprising the following steps:

[0031] SB1, prepare the doped substrate;

[0032] SB2, growing a silicon dioxide layer on the substrate to form a lower silicon dioxide layer;

[0033] SB3, etching a window in the lower silicon dioxide layer;

[0034] SB4, filling the etched window with polysilicon to form a lower polysilicon gate;

[0035] SB5, using atomic layer deposition, a thin layer of silicon dioxide is prepared on the lower silicon dioxide layer and the lower polysilicon gate to form a lower gate oxide layer;

[0036] SB6, through Si-SiO 2 Bonding process, bonding a layer of N on the lower gate oxide layer— Silicon, forming N — Silicon layer;

[0037] SB7, in N — In the silicon layer, high-energy ions are implanted with boron and thermally diffused to form a floating P-type silicon layer centered above and below.

[0038] SB8, in N — Boron ions are implanted into the silicon layer and the position above the lower polysilicon gate is corresponding to the position above the lower polysilicon gate. After diffusion, the P — Silicon layer;

[0039] SB9, in N — A silicon dioxide layer is grown on the silicon layer as a field oxide layer;

[0040] SB10, in N — Silicon layer, P — A thin layer of silicon dioxide is grown on the silicon layer and the field oxide layer to form an upper gate oxide layer;

[0041] SB11, on the upper gate oxide layer, corresponding to P — Depositing polysilicon on the silicon layer to form an upper polysilicon gate;

[0042] SB12, in N — On one side of the silicon layer, N — The other side of the silicon layer, P — The silicon layer is away from the floating P-type silicon layer. — Arsenic ions are implanted into the silicon layer through an ion implantation process, and the first N + The silicon layer and the second N + Silicon layer;

[0043] SB13, plasma etching of the left and right sides N + Silicon layer;

[0044] SB14, through the metal filling process, in the first N + The silicon layer and the second N + A drain metal layer and a source metal layer are respectively formed on one side of the silicon layer, and finally a complete drain and source are formed.

[0045] Compared with the prior art, the present invention has the following significant effects:

[0046] 1. The present invention is provided with two sets of gates, source and drain. When the upper and lower polysilicon gates are turned on at the same time, two current paths are formed between the source and drain. Under the same chip area, the current density is increased to more than 2.3 times that of the traditional LDMOS, thereby significantly reducing the on-resistance of the device, and can greatly reduce the area of ​​the power integrated circuit designed based on the device. The greater the chip output current, the more significant the reduction in chip area.

[0047] 2. The present invention is in N — After the floating P-type silicon layer is introduced into the silicon layer, when the device is turned on, at the same breakdown voltage, the upper and lower current paths are not affected and the N — The doping concentration of the silicon layer can be increased by more than 30%, so the on-resistance of the device can be further reduced by more than 20%;

[0048] 3. The present invention adopts atomic layer deposition to prepare the lower gate oxide layer. Compared with the traditional CVD deposition (Chemical Vapor Deposition, chemical vapor deposition), it can prepare a higher density gate oxide layer and improve the reliability of the gate oxide layer; Si-SiO 2 The bonding process can prepare a high-quality silicon layer on the oxide layer for preparing upper devices;

[0049] 4. The present invention is provided with a lower silicon dioxide layer. By preparing an isolation oxide layer between two devices and on the lower silicon dioxide layer, complete isolation between the devices can be achieved, thereby suppressing leakage crosstalk between the devices, and thus having the characteristics of high temperature resistance; the power integrated circuit designed based on the device can avoid the risk of latch failure caused by increased leakage at high temperature, and can enable the power integrated circuit to work at a high temperature of 200°C;

[0050] 5. The present invention is provided with a lower silicon dioxide layer, so that the device has better radiation resistance and can withstand a total dose of more than 100 krad (Si), so it can be used in the aerospace field;

[0051] 6. The preparation method of the present invention is compatible with the standard CMOS (Complementary Metal Oxide Semiconductor) process and can be used for the design and preparation of large-scale power integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a schematic diagram of a first lateral device structure of the present invention;

[0053] Figure 2 It is a schematic diagram of a P-type substrate of the present invention;

[0054] Figure 3 It is a schematic diagram of a P-type substrate and a silicon dioxide layer of the present invention;

[0055] Figure 4 It is a schematic diagram of the structure after etching a window on the silicon dioxide layer of the present invention;

[0056] Figure 5 It is a schematic diagram of the structure of the present invention after the etched window is filled with polysilicon;

[0057] Figure 6 It is a schematic diagram of the structure of the present invention after the lower gate oxide layer is deposited;

[0058] Figure 7 In the present invention, a layer of N is bonded on the silicon dioxide layer. — Schematic diagram of the structure after silicon;

[0059] Figure 8 For the present invention in N — Schematic diagram of the structure after ion implantation of boron into the silicon layer;

[0060] Fig. 9 For the present invention in N — A N layer with the same concentration and thickness is grown on the silicon layer. — Silicon layer, and thermal diffusion is performed to form a structural schematic diagram of a floating P-type silicon layer;

[0061] Fig.10 The present invention forms P after ion implantation of boron — Schematic diagram of the structure of the silicon layer;

[0062] Fig.11 It is a schematic diagram of the structure of the present invention after the field oxide layer is grown;

[0063] Fig.12 It is a schematic diagram of the structure of the present invention after the gate oxide layer is grown;

[0064] Fig.13 It is a schematic diagram of the structure of the present invention after polysilicon is deposited;

[0065] Fig.14 The present invention forms a first N + The silicon layer and the second N + Schematic diagram of the structure of the silicon layer;

[0066] Fig.15 The present invention is in the etching part N + Schematic diagram of the structure after silicon;

[0067] Fig.16 is a schematic structural diagram of a second lateral device of the present invention;

[0068] Fig.17 Based on the high energy ion implantation process, the present invention bonds a layer of N on the silicon dioxide layer. — Schematic diagram of the structure after silicon;

[0069] Fig.18 This is a schematic diagram of the structure after high-energy ion implantation of boron and thermal diffusion of the present invention;

[0070] Fig.19Based on high energy ion implantation process, the present invention forms P after ion implantation of boron - Schematic diagram of the structure of the silicon layer;

[0071] Fig. 20 It is a schematic diagram of the structure of the present invention after growing a field oxide layer based on a high-energy ion implantation process;

[0072] Fig.21 This is a schematic diagram of the structure of the present invention after the gate oxide layer is grown based on the high-energy ion implantation process;

[0073] Fig. 22 The schematic diagram of the structure of the present invention after polysilicon deposition based on high-energy ion implantation process;

[0074] Fig.23 Based on the high energy ion implantation process, the present invention forms a first N + The silicon layer and the second N + Schematic diagram of the structure of the silicon layer;

[0075] Fig.24 Based on high energy ion implantation process, part of N is etched + Schematic diagram of the structure after silicon;

[0076] Fig.25 is a schematic diagram of a third lateral device structure of the present invention;

[0077] Fig.26 A schematic diagram of current flow directions of two current paths of the present invention;

[0078] Fig. 27 A comparison diagram of output characteristic curves when the gate voltage is 5V for a conventional single-channel LDMOS, a dual-gate structure of the present invention without a floating P-type silicon layer, and a dual-gate structure of the present invention with a floating P-type silicon layer;

[0079] Fig.28 A schematic diagram of using an oxide layer to isolate two devices of the present invention;

[0080] Fig.29 It is a circuit diagram of an application scenario of the present invention;

[0081] In the figure: 1-P-type substrate, 2-lower silicon dioxide layer, 3-lower polysilicon gate, 4-lower gate oxide layer, 5-N — Silicon layer, 501-N — Silicon layer, 502-upper N — Silicon layer, 6-P — Silicon layer, 7-field oxide layer, 8-upper gate oxide layer, 9-upper polysilicon gate, 1001-first N + Silicon layer, 1002-second N +Silicon layer, 1101-drain metal layer, 1102-source metal layer, 12-floating P-type silicon layer, 13-boron ion implantation layer. DETAILED DESCRIPTION

[0082] The present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0083] like Figure 1 As shown, an N-type lateral device comprises: a P-type substrate 1, on which a lower silicon dioxide layer 2 is provided; a window is etched on the lower silicon dioxide layer 2, and the window is filled with polysilicon to form a lower polysilicon gate 3; a thin silicon dioxide layer is provided on the lower silicon dioxide layer 2 and the lower polysilicon gate 3 as a lower gate oxide layer 4; and a lower N — Silicon layer 501 and upper N — Silicon layer 502, N — Silicon layer 501 and upper N — A floating P-type silicon layer 12 is provided between the silicon layers 502; a P — Silicon layer 6, N — Silicon layer 501 and upper N — One side of the silicon layer 502 is provided with a first N + Silicon layer 1001; in P — A second N + Silicon layer 1002, on top N — An upper silicon dioxide layer is provided on the silicon layer 502 as a field oxide layer 7; — Silicon layer 6, first N + Silicon layer 1001 and second N + On the silicon layer 1002, a thin silicon dioxide layer is provided on the upper surface and both sides of the field oxide layer 7, respectively, as an upper gate oxide layer 8; on the upper gate oxide layer 8, corresponding to P — A polysilicon layer is provided above the silicon layer 6 as an upper polysilicon gate 9; + The silicon layer 1002 and the first N + A source metal layer 1102 and a drain metal layer 1101 are provided on one side of the silicon layer 1001. The upper polysilicon gate 9 and the lower polysilicon gate 3 serve as the upper polysilicon gate and the lower polysilicon gate of the device respectively. + Silicon layer 1001, second N + The silicon layer 1002 serves as the drain and source of the device respectively; when the upper and lower polysilicon gates are simultaneously high-voltage, the device is fully turned on. — An upper conductive channel is formed between the upper portion of the silicon layer 6 and the upper gate oxide layer 8, corresponding to the position of the upper polysilicon gate; —A lower conductive channel is formed between the lower part of the silicon layer 6 and the lower gate oxide layer 4, corresponding to the position of the lower polysilicon gate; when a high voltage is applied to the upper and lower polysilicon gates, two upper and lower current paths are formed between the source and the drain respectively (such as Fig.26 As shown in FIG. 1 ), the first current path passes through the drain metal layer 1101 through the drain, and then through the upper N — The second current path flows from the drain metal layer 1101 through the drain, and then through the lower N — The current flows through the silicon layer 501, the lower conductive channel, the source, and finally to the source metal layer 1102. On the same device area, the current density is increased to twice that of the traditional LDMOS, thereby significantly reducing the on-resistance.

[0084] Preferably, the thickness of the source metal layer 1102 and the drain metal layer 1101 are the same. Assuming the thickness of the source metal layer 1102 is d, then d=d 1 +d 2 , where d 1 P — The thickness of the silicon layer 6, d 2 is the thickness of the upper gate oxide layer 8.

[0085] The doping concentration of the P-type substrate 1 is 1.0×10 15 ~1.0×10 16 / cm 3 The thickness of the lower silicon dioxide layer 2 and the field oxide layer 7 are both 2000nm~3000nm, the thickness of the lower polysilicon gate 3 and the upper polysilicon gate 9 are both 1500nm, the thickness of the lower gate oxide layer 4 and the upper gate oxide layer 8 are both 15nm~30nm; the lower N — The length of the silicon layer 501 is 5 μm to 50 μm, the thickness is 750 nm to 4000 nm, and the doping concentration is 1.0×10 16 ~1.0×10 18 / cm 3 , on N — The length, thickness, and doping concentration of the silicon layer 502 are related to the lower N — The floating P-type silicon layer 12 has a doping concentration of N — 0.5~2 times the doping concentration of silicon layer 501; P — The doping concentration of silicon layer 6 is 1.0×10 17 ~1.0×10 19 / cm 3 , the first N + Silicon layer 1001 and second N + The doping concentration of the silicon layer 1002 is 1.0×10 20 ~1.0×10 21 / cm 3 .

[0086] like Figure 1 In the device structure shown, N — Silicon layer (i.e. including the lower N — Silicon layer 501 and upper N — After the floating P-type silicon layer is introduced into the silicon layer 502, when the device is turned on, the floating P-type silicon layer — The silicon layer is centered up and down, so it does not affect the upper and lower current paths; in the off-state withstand voltage, — A new PN junction will be formed between the silicon layer and the floating P-type silicon layer. Under the same breakdown voltage, N — The doping concentration of the silicon layer can be increased by more than 30%. Therefore, when the device is turned on, the upper and lower current paths are not affected and the N — The doping concentration of the silicon layer can be increased by more than 30%, so the on-resistance of the device can be further reduced by more than 20%.

[0087] Preferably, for N — The silicon layer can adopt an integral structure, through Si-SiO 2 Bonding process, bonding a layer of N on the lower gate oxide layer 4 — Silicon, namely N — Silicon layer 5, the specific structure is as follows Fig.25 shown.

[0088] Further, in Fig.25 Based on the structure shown in N — In the silicon layer, boron is implanted by high energy ions and thermally diffused to form a floating P-type silicon layer 12 centered above and below. The specific structure is as follows: Fig.16 shown.

[0089] The preparation method of the present invention is further described below in conjunction with the accompanying drawings.

[0090] like Figure 1 The first method for preparing a lateral device includes the following steps:

[0091] Step A1, prepare a doping concentration of about 1.0×10 15 ~1.0×10 16 / cm 3 The P-type substrate 1, such as Figure 2 As shown;

[0092] Step A2, growing a 2000nm thick silicon dioxide layer on the P-type substrate 1, as the lower silicon dioxide layer 2, such as Figure 3 As shown;

[0093] Step A3, such as Figure 4As shown, a window with a depth of 1500nm and a width of 0.5μm~2μm is etched on the lower silicon dioxide layer 2;

[0094] Step A4, filling the etched window with polysilicon to form a lower polysilicon gate 3, such as Figure 5 As shown;

[0095] Step A5, using atomic layer deposition, a thin layer of silicon dioxide is prepared on the lower silicon dioxide layer 2 and the lower polysilicon gate 3 to form a lower gate oxide layer 4, such as Figure 6 As shown;

[0096] Step A6, by Si-SiO 2 Bonding process, bonding a layer of N on the lower gate oxide layer 4 — Silicon, forming the lower N — Silicon layer 501, such as Figure 7 As shown;

[0097] Step A7, in the next N — Boron is ion-implanted into the silicon layer 501 to form a boron ion-implanted layer 13. Figure 8 shown.

[0098] Step A8, in the next N — An upper N layer is epitaxially grown on the silicon layer 501. — Silicon layer 502, upper N — The silicon layer 502 and the lower N — The doping concentration and thickness of the silicon layer 501 are the same, and thermal diffusion is performed to form a floating P-type silicon layer 12 centered above and below. Fig. 9 As shown;

[0099] Step A9, in the next N — Silicon layer 501 and upper N — Boron ions are implanted into the silicon layer 502 at a position corresponding to the lower polysilicon gate 3 by an ion implantation process, and after diffusion, P — Silicon layer 6, such as Fig.10 As shown;

[0100] Step A10, on N — A silicon dioxide layer is grown on the silicon layer 502 as a field oxide layer 7. The thickness of the field oxide layer 7 is 2000nm to 3000nm. Fig.11 As shown;

[0101] Step A11, on N — Silicon layer 502 and P — A thin layer of silicon dioxide is grown on the silicon layer 6 and the upper surface and both sides of the field oxide layer 7 to form an upper gate oxide layer 8. Fig.12 As shown;

[0102] Step A12, on the upper gate oxide layer 8, corresponding to P — Polysilicon is deposited on the silicon layer 6 to form an upper polysilicon gate 9. Fig.13 As shown;

[0103] Step A13, in the next N — Silicon layer 501 and upper N — On one side of the silicon layer 502, the lower N — Silicon layer 501 and upper N — The other side of the silicon layer 502 (ie, near P — Silicon layer 6 side), under N — Silicon layer 501 and upper N — Arsenic ions are implanted into the silicon layer 502 by an ion implantation process, and after diffusion, the first N + Silicon layer 1001 and second N + Silicon layer 1002, such as Fig.14 As shown;

[0104] Step A14, plasma etching the two side portions N + Silicon layer, such as Fig.15 As shown;

[0105] Step A15, through a metal filling process, in the first N + A drain metal layer 1101 is formed on one side of the silicon layer 1001. + A source metal layer 1102 is formed on one side of the silicon layer 1002, and finally a complete drain and source are formed. Figure 1 As shown, the filling metal can be selected from tungsten, aluminum, copper, etc.

[0106] like Fig.16 The second method for preparing a lateral device shown is different from the first method for preparing a lateral device in that the floating P-type silicon layer is prepared by a high-energy ion implantation boron process, and includes the following steps:

[0107] Step B1, prepare a doping concentration of about 1.0×10 15 ~1.0×10 16 / cm 3 The P-type substrate 1, such as Figure 2 As shown;

[0108] Step B2, growing a 2000nm thick silicon dioxide layer on the P-type substrate 1, as the lower silicon dioxide layer 2, such as Figure 3 As shown;

[0109] Step B3, such as Figure 4 As shown, a window with a depth of 1500nm and a width of 0.5μm~2μm is etched on the lower silicon dioxide layer 2;

[0110] Step B4, filling the etched window with polysilicon to form a lower polysilicon gate 3, such as Figure 5 As shown;

[0111] Step B5, using atomic layer deposition, a thin layer of silicon dioxide is prepared on the lower silicon dioxide layer 2 and the lower polysilicon gate 3 to form a lower gate oxide layer 4, such as Figure 6 As shown;

[0112] Step B6, by Si-SiO 2 Bonding process, bonding a layer of N on the lower gate oxide layer 4 — Silicon, forming N — Silicon layer 5, such as Fig.17 As shown;

[0113] Step B7, in N — In the silicon layer 5, high energy ions are implanted with boron and thermally diffused to form a floating P-type silicon layer 12 centered above and below. Fig.18 As shown;

[0114] Step B8, in N — Boron ions are implanted into the silicon layer 5 at a position corresponding to the lower polysilicon gate 3 by an ion implantation process, and after diffusion, P — Silicon layer 6, such as Fig.19 As shown;

[0115] Step B9, in N — A silicon dioxide layer is grown on the silicon layer 5 as a field oxide layer 7. Fig. 20 As shown;

[0116] Step B10, in N — Silicon layer 5 and P — A thin layer of silicon dioxide is grown on the silicon layer 6 and the upper surface and both sides of the field oxide layer 7 to form an upper gate oxide layer 8. Fig.21 As shown;

[0117] Step B11, on the upper gate oxide layer 8, corresponding to P — Polysilicon is deposited on the silicon layer 6 to form an upper polysilicon gate 9. Fig. 22 As shown;

[0118] Step B12, in N — One side of the silicon layer 5, N — The other side of the silicon layer 5 (ie, near P — Silicon layer 6 side), on N — Arsenic ions are implanted into the silicon layer 5 by an ion implantation process, and after diffusion, the first N + Silicon layer 1001 and second N + Silicon layer 1002, such as Fig.23 As shown;

[0119] Step B13, plasma etching the left and right side portions N + Silicon layer, such as Fig.24 As shown;

[0120] Step B14, through a metal filling process, in the first N + A drain metal layer 1101 is formed on one side of the silicon layer 1001, and a second N + A source metal layer 1102 is formed on one side of the silicon layer 1002, and finally a complete drain and source are formed. Fig.16 shown.

[0121] Fig. 27 The figure shows the output characteristic curve comparison of the conventional single-channel LDMOS, the dual-gate structure of the present invention without the floating P-type silicon layer, and the dual-gate structure of the present invention with the floating P-type silicon layer when the gate voltage is 5V. It can be concluded that the dual-gate structure of the present invention can increase the current density (such as Fig.26 As shown), thereby reducing the on-resistance of the device. — After the floating P-type silicon layer is introduced into the silicon layer, the N — The doping concentration of the silicon layer can further reduce the on-resistance of the device.

[0122] Fig.28 Two devices of the present invention are shown (with Figure 1 Because a lower silicon dioxide layer 2 is provided, in practical applications, a layer of isolation oxide layer is prepared between the two devices and on the lower silicon dioxide layer 2, so that complete isolation between the devices can be achieved, thereby suppressing leakage crosstalk between the devices.

[0123] The present invention can be used as a power driver in integrated intelligent driver chips used in the fields of industrial control, aerospace, etc. Fig.29 The power drive tubes M1 to M6 shown in the figure. Since the device of the present invention has a lower on-resistance, the chip area can be reduced by more than 30% under the same drive current.

Claims

1. An N-type lateral device, characterized in that: A lower silicon dioxide layer (2) is provided on a P-type substrate (1); a window is etched on the lower silicon dioxide layer (2) and filled with polysilicon to form a lower polysilicon gate (3); a lower gate oxide layer (4) is provided on the lower silicon dioxide layer (2) and the lower polysilicon gate (3); a source metal layer (1102), a second N + Silicon layer (1002), P — Silicon layer (6), N — Silicon layer (5), first N + The silicon layer (1001) and the drain metal layer (1101), the P — The silicon layer (6) is disposed at a position corresponding to the lower polysilicon gate (3), in the N — A field oxide layer (7) is provided on the silicon layer (5); In P — Silicon layer (6), first N + Silicon layer (1001) and the second N + An upper gate oxide layer (8) is provided on the upper surface of the silicon layer (1002), the upper surface of the field oxide layer (7) and both sides thereof; on the upper gate oxide layer (8), corresponding to P — An upper polysilicon gate (9) is provided above the silicon layer (6); The upper polysilicon gate (9) and the lower polysilicon gate (3) serve as the upper polysilicon gate and the lower polysilicon gate of the device respectively; when the upper and lower polysilicon gates are turned on at the same time, — An upper conductive channel is formed between the upper portion of the silicon layer (6) and the upper gate oxide layer (8) at a position corresponding to the upper polysilicon gate. — A lower conductive channel is formed between the lower part of the silicon layer (6) and the lower gate oxide layer (4), corresponding to the position of the lower polysilicon gate, and correspondingly forms two upper and lower current paths between the source and the drain.

2. The N-type lateral device according to claim 1, characterized in that: In N — A floating P-type silicon layer (12) is provided in the silicon layer (5), and the doping concentration of the floating P-type silicon layer (12) is N — 0.5 to 2 times the doping concentration of the silicon layer (5).

3. The N-type lateral device according to claim 2, characterized in that: The floating P-type silicon layer (12) is — The silicon layer (5) is located in the middle of the upper and lower parts.

4. The N-type lateral device according to claim 2, characterized in that: The lower gate oxide layer (4), the field oxide layer (7) and the upper gate oxide layer (8) are respectively silicon dioxide layers.

5. The N-type lateral device according to claim 2, characterized in that: The thickness of the lower silicon dioxide layer (2) and the field oxide layer (7) are both 2000nm to 3000nm, the thickness of the lower polysilicon gate (3) and the upper polysilicon gate (9) are both 1500nm, and the thickness of the lower gate oxide layer (4) and the upper gate oxide layer (8) are both 15nm to 30nm.

6. The N-type lateral device according to claim 2, characterized in that: The second N + Silicon layer (1002), P — Silicon layer (6), N — Silicon layer (5), first N + The thickness of the silicon layer (1001) is the same as that of the N — The length of the silicon layer (5) is 5 μm to 50 μm, the thickness is 1500 nm to 8000 nm, and the doping concentration is 1.0×10 16 ~1.0×10 18 / cm 3 .

7. The N-type lateral device according to any one of claims 1, 2, 4 to 6, characterized in that: P — The doping concentration of the silicon layer (6) is 1.0×10 17 ~1.0×10 19 / cm 3 , the first N + Silicon layer (1001) and the second N + The doping concentration of the silicon layer (1002) is 1.0×10 20 ~1.0×10 21 / cm 3 , the doping concentration of the P-type substrate (1) is 1.0×10 15 ~1.0×10 16 / cm 3 .

8. The N-type lateral device according to any one of claims 1, 2, 4 to 6, characterized in that: The source metal layer (1102) and the drain metal layer (1101) are made of the same material, namely tungsten, aluminum, or copper.

9. A method for preparing an N-type lateral device, characterized in that: The method for preparing the lateral device according to any one of claims 2 to 8 comprises the following steps: SA1, prepare the doped P-type substrate (1); SA2, growing a silicon dioxide layer on the P-type substrate (1) to form a lower silicon dioxide layer (2); SA3, etching a window in the lower silicon dioxide layer (2); SA4, filling the etched window with polysilicon to form a lower polysilicon gate (3); SA5, using atomic layer deposition to prepare a thin layer of silicon dioxide on the lower silicon dioxide layer (2) and the lower polysilicon gate (3) to form a lower gate oxide layer (4); SA6, through Si-SiO2 bonding process, a layer of N is bonded on the lower gate oxide layer (4) — Silicon, forming the lower N — Silicon layer (501); SA7, I am N — Ion implantation of boron into the silicon layer (501) forms a boron ion implantation layer (13); SA8, under N — A layer of N is epitaxially grown on the silicon layer (501) — Silicon layer (502), upper N — The silicon layer (502) and the lower N — The concentration and thickness of the silicon layer (501) are the same, and thermal diffusion is performed to form a floating P-type silicon layer (12) centered above and below; SA9, I am N — Silicon layer (501) and upper N — Boron ions are implanted into the silicon layer (502) at a position corresponding to the lower polysilicon gate (3) by an ion implantation process, and after diffusion, P — Silicon layer (6); SA10, on N — A silicon dioxide layer is grown on the silicon layer (502) to serve as a field oxide layer (7); SA11, on N — Silicon layer (502), P — A thin layer of silicon dioxide is grown on the silicon layer (6) and the field oxide layer (7) to form an upper gate oxide layer (8); SA12, on the upper gate oxide layer (8), corresponding to P — Depositing polysilicon at a position above the silicon layer (6) to form an upper polysilicon gate (9); SA13, under N — Silicon layer (501) and upper N — On one side of the silicon layer (502), the lower N — Silicon layer (501) and upper N — The other side of the silicon layer (502), P — The silicon layer (6) is away from the floating P-type silicon layer (12), and the lower N — Silicon layer (501) and upper N — Arsenic ions are implanted into the silicon layer (502) by an ion implantation process to form a first N + Silicon layer (1001) and the second N + Silicon layer (1002); SA14, plasma etching both sides N + Silicon layer; SA15, through the metal filling process, in the first N + Silicon layer (1001) and the second N + A drain metal layer (1101) and a source metal layer (1102) are respectively formed on one side of the silicon layer (1002), and finally a complete drain and source are formed.

10. A method for preparing an N-type lateral device, characterized in that: The method for preparing the lateral device according to any one of claims 2 to 8 comprises the following steps: SB1, prepare the doped P-type substrate (1); SB2, growing a silicon dioxide layer on the P-type substrate (1) to form a lower silicon dioxide layer (2); SB3, etching a window in the lower silicon dioxide layer (2); SB4, filling the etched window with polysilicon to form a lower polysilicon gate (3); SB5, using atomic layer deposition to prepare a thin layer of silicon dioxide on the lower silicon dioxide layer (2) and the lower polysilicon gate (3) to form a lower gate oxide layer (4); SB6, through Si-SiO2 bonding process, a layer of N is bonded on the lower gate oxide layer (4) — Silicon, forming N — Silicon layer (5); SB7, in N — In the silicon layer (5), high energy ions are implanted with boron, and thermal diffusion is performed to form a floating P-type silicon layer (12) centered above and below; SB8, in N — Boron ions are implanted into the silicon layer (5) at a position corresponding to the lower polysilicon gate (3) by an ion implantation process, and after diffusion, a P — Silicon layer (6); SB9, in N — A silicon dioxide layer is grown on the silicon layer (5) to serve as a field oxide layer (7); SB10, in N — Silicon layer (5), P — A thin layer of silicon dioxide is grown on the silicon layer (6) and the field oxide layer (7) to form an upper gate oxide layer (8); SB11, on the upper gate oxide layer (8), corresponding to P — Depositing polysilicon at a position above the silicon layer (6) to form an upper polysilicon gate (9); SB12, in N — One side of the silicon layer (5), N — The other side of the silicon layer (5), P — The silicon layer (6) is away from the floating P-type silicon layer (12) and is located on the N — Arsenic ions are implanted into the silicon layer (5) by an ion implantation process, and after diffusion, a first N + Silicon layer (1001) and the second N + Silicon layer (1002); SB13, plasma etching of the left and right sides N + Silicon layer; SB14, through the metal filling process, in the first N + Silicon layer (1001) and the second N + A drain metal layer (1101) and a source metal layer (1102) are respectively formed on one side of the silicon layer (1002), and finally a complete drain and source are formed.

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