Manufacturing method of semiconductor structure
By forming a multi-layer spacer layer on the bit line structure of the semiconductor structure and oxidation treatment, the problem of increasing parasitic capacitance in the semiconductor device is solved, and the effect of reducing power consumption and RC time delay is achieved.
Patent Information
- Application Number
- CN202410094582.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-07
- Filing Date
- 2024-01-23
- Publication Date
- 2025-04-08
AI Technical Summary
As the feature size of semiconductor components decreases, the parasitic capacitance between metal features increases, resulting in high power consumption and large RC time delays, and existing low dielectric constant materials encounter difficulties in further improvement.
By forming a multi-layer spacer layer on the side walls of the bit line structure and performing an oxidation process on the second spacer layer, the oxidation portion and the remaining portion are formed, the structure and thickness of the spacer layer are optimized to reduce parasitic capacitance.
It effectively reduces parasitic capacitance between metal features, reduces power consumption and RC time delay, while maintaining the uniformity and overall thickness of the spacer layer structure.
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Figure CN119789517A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for manufacturing a semiconductor structure. Background Art
[0002] The integration density of various electronic components such as transistors, diodes, resistors, capacitors, etc. continues to improve in the semiconductor industry by continuously reducing the minimum feature size. As the feature size decreases, the distance between metal features also continues to decrease. As the distance between metal features decreases, the parasitic capacitance generated between metal features increases, resulting in higher power consumption and larger resistance-capacitance (RC) time delay for the integrated chip. To improve performance and reduce parasitic capacitance between metal features, materials with low dielectric constant (k) values are used. However, this dielectric material encounters many processing problems that prevent further improvement of the dielectric constant.
[0003] In the process of manufacturing semiconductor devices, it is necessary to deposit low-K spacers (LKS) with good uniformity on different substrate surfaces. These different surfaces can be composed of different materials, such as metals and dielectrics. It is a problem to uniformly deposit a material on two or more different substrate surfaces while maintaining the distance between metal features. Summary of the invention
[0004] One aspect of the present invention is to provide a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes the following steps. A bit line structure is formed above a substrate. A first spacer is formed on a first sidewall of the bit line structure. A second spacer is formed on a second sidewall of the first spacer. A third spacer is formed on a third sidewall of the second spacer. An oxidation process is performed on the second spacer to form an oxidized portion and a remaining portion in the second spacer, wherein the oxidized portion is located between the remaining portion and the third spacer. A fourth spacer is formed on a fourth sidewall of the third spacer.
[0005] According to one or more embodiments of the present invention, the first spacer layer includes insulating nitride.
[0006] According to one or more embodiments of the present invention, the second spacer layer comprises SiCO.
[0007] According to one or more embodiments of the present invention, the third spacer layer includes an insulating oxide.
[0008] According to one or more embodiments of the present invention, the fourth spacer layer includes insulating nitride.
[0009] According to one or more embodiments of the present invention, performing an oxidation process on the second spacer is performed before forming a fourth spacer on the fourth sidewall of the third spacer.
[0010] According to one or more embodiments of the present invention, the oxidized portion of the second spacer layer comprises SiO 2 and the third spacer layer comprises SiO 2 .
[0011] According to one or more embodiments of the present invention, the oxidation process is a plasma oxidation process.
[0012] According to one or more embodiments of the present invention, the plasma oxidation process includes O 2 and H 2 N 2 plasma oxidation processes.
[0013] According to one or more embodiments of the present invention, the first spacer layer, the second spacer layer and the third spacer layer have a first thickness, a second thickness and a third thickness respectively, the second thickness is greater than the third thickness, and the third thickness is greater than the first thickness.
[0014] Another aspect of the present invention is to provide a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes the following steps. A bit line structure is formed above a substrate. A first spacer is formed on a first sidewall of the bit line structure, wherein the first spacer includes an insulating nitride. A second spacer is formed on a second sidewall of the first spacer, wherein the second spacer includes SiO2 and has a first portion and a second portion, and the first portion is located between the first spacer and the second portion. A third spacer is formed to cover the second portion of the second spacer. An oxidation process is performed on the second portion of the second spacer. A fourth spacer is formed on a third sidewall of the third spacer. A buried contact is formed adjacent to the fourth spacer.
[0015] According to one or more embodiments of the present invention, the oxidation process is a plasma oxidation process.
[0016] According to one or more embodiments of the present invention, the plasma oxidation process includes O 2 and H 2 N 2 plasma oxidation processes.
[0017] According to one or more embodiments of the present invention, before the oxidation process is performed, the third spacer layer has a first thickness, and after the oxidation process is performed, the third spacer layer has a second thickness, and the second thickness is less than the first thickness.
[0018] According to one or more embodiments of the present invention, the third spacer layer includes an insulating oxide.
[0019] According to one or more embodiments of the present invention, the fourth spacer layer includes insulating nitride.
[0020] According to one or more embodiments of the present invention, performing an oxidation process to oxidize the second portion of the second spacer is performed before forming a fourth spacer on the third sidewall of the third spacer. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] When reading the accompanying drawings, the various aspects of the present invention can be fully understood from the following detailed description. It is worth noting that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various features can be arbitrarily increased or reduced.
[0022] Figure 1 is a configuration diagram of a semiconductor structure according to some embodiments of the present invention.
[0023] Figure 2 are cross-sectional views of semiconductor structures at various manufacturing stages according to various embodiments of the present invention.
[0024] Figure 3 is an enlarged view of a semiconductor structure at a certain manufacturing stage according to a comparative example.
[0025] Figure 4 are enlarged views of semiconductor structures at various stages of fabrication according to various embodiments of the present invention.
[0026] Figure 5 are enlarged views of semiconductor structures at various stages of fabrication according to various embodiments of the present invention.
[0027] Figure 6 are enlarged views of semiconductor structures at various stages of fabrication according to various embodiments of the present invention.
[0028] Figure 7 are enlarged views of semiconductor structures at various stages of fabrication according to various embodiments of the present invention.
[0029] Figure 8 are enlarged views of semiconductor structures at various stages of fabrication according to various embodiments of the present invention.
[0030] Fig. 9 are enlarged views of semiconductor structures at various stages of fabrication according to various embodiments of the present invention.
[0031] Fig.10 are cross-sectional views of semiconductor structures at various manufacturing stages according to various embodiments of the present invention.
[0032] Fig.11 are cross-sectional views of semiconductor structures at various manufacturing stages according to various embodiments of the present invention.
[0033] Fig.12are cross-sectional views of semiconductor structures at various manufacturing stages according to various embodiments of the present invention.
[0034] Fig.13 are cross-sectional views of semiconductor structures at various manufacturing stages according to various embodiments of the present invention. DETAILED DESCRIPTION
[0035] The following will disclose multiple embodiments of the present invention with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are not necessary. And for the sake of clarity, the size or thickness of the components may be exaggerated and not drawn according to the original size. In addition, in order to simplify the drawings, some conventional structures and components will be depicted in a simple schematic manner in the drawings.
[0036] The following disclosure provides many different embodiments or examples to realize the different features of each embodiment. The following describes specific examples of parts and arrangements to simplify the present invention. Of course, these examples are only examples and are not intended to be restrictive. For example, the formation of the first feature above or on the second feature in the subsequent description may include an embodiment in which the first and second features are formed as direct contacts, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present invention may repeat component symbols and / or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.
[0037] Spatially relative terms such as "below", "under", "above", "on", etc. are used in this article to facilitate the description of the relative relationship between one element or feature and another element or feature, as shown in the figure. The true meaning of these spatially relative terms includes other orientations. For example, when the figure is flipped 180 degrees up and down, the relationship between one element and another element may change from "below" or "under" to "above" or "on". In addition, the spatially relative descriptions used in this article should also be interpreted in the same way.
[0038] See also Figure 1 , Figure 1 A configuration diagram of a semiconductor structure 100 is shown according to some embodiments of the present invention. The semiconductor structure 100 may include a plurality of active regions ACT. The active region ACT has a short axis and a long axis. In some embodiments, the long axis of the active region ACT extends along an oblique axis, wherein the oblique axis is at an angle to the X axis.
[0039] A plurality of word lines WL may be disposed across the active area ACT and extend along the X-axis direction. The word lines WL are parallel to one another. In addition, the word lines WL are spaced apart from one another by substantially equal intervals.
[0040] A plurality of bit lines BL may be disposed on the word line WL and extend along the Y-axis direction. Similarly, the bit line BL is parallel to another bit line BL. In addition, the bit line BL is connected to the active region ACT through a direct contact DC. One active region ACT may be electrically connected to one direct contact DC.
[0041] A plurality of buried contacts BC may be formed between two adjacent bit lines BL. In some embodiments, each buried contact BC is spaced apart from each other along the Y axis. The buried contacts BC may electrically connect the bottom electrode (not shown) of the storage node / capacitor to the corresponding active region ACT. A single active region ACT may electrically connect two buried contacts BC.
[0042] A plurality of landing pads LP may be disposed on the buried contact BC and cover at least a portion of the corresponding bit line BL. The landing pad LP may be electrically connected to the buried contact BC. The landing pad LP may also electrically connect the lower electrode (not shown) of the storage node / capacitor to the corresponding active region ACT. In other words, the lower electrode (not shown) of the storage node / capacitor is electrically connected to the corresponding active region ACT through the corresponding buried contact BC and the corresponding landing pad LP.
[0043] In some embodiments, one buried contact BC and one landing pad LP may be collectively referred to as a contact plug, and respectively referred to as a first contact plug (ie, buried contact BC) and a second contact plug (ie, landing pad LP).
[0044] Figure 2 and Figures 5 to 12 Shown are cross-sectional views of various steps of a method of fabricating a semiconductor (eg, semiconductor structure 100 ) according to some embodiments of the present invention. Figures 5 to 9 The enlarged view is based on Figure 2 Take the reference cross-sectional view shown in box B.
[0045] It should be noted that, unless otherwise specified, when the following embodiments are depicted or described as a series of operations or events, the order in which these operations or events are described should not be limited. For example, some operations or events may be performed in a different order than the present invention, some operations or events may occur simultaneously, some operations or events may not be required, and / or some operations or events may be repeated. Furthermore, the actual process may require additional operations before, during, or after each step to fully form a semiconductor device. Therefore, the present invention may briefly describe some of these additional operations.
[0046] See also Figure 2 , a plurality of bit line structures 110 are formed above the substrate 102 .
[0047] The substrate 102 has a plurality of isolation regions 104 and a plurality of active regions 106, wherein the isolation regions 104 separate the active regions 106. The substrate 102 may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 102 may include other elemental semiconductors, such as germanium. In some embodiments, the substrate 102 may include alloy semiconductors, such as silicon germanium, gallium indium phosphide, silicon germanium carbide, or other suitable materials. In some embodiments, the substrate 102 may include compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials. In addition, the substrate 102 may selectively include a semiconductor-on-insulator (SOI) structure.
[0048] The isolation region 104 may be formed by a shallow trench isolation (STI) process. The material of the isolation region 104 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation region 104 may be a single-layer structure including one insulating material, a double-layer structure including two insulating materials, or a multi-layer structure including at least three insulating materials. For example, the isolation region 104 may include silicon nitride and silicon oxide. For another example, the isolation region 104 may be a three-layer structure including silicon oxide, silicon nitride, and silicon oxynitride.
[0049] In some embodiments, an insulating layer 108 is formed on the substrate 102 and covers the top surfaces of the isolation regions 104 and the active regions 106 of the substrate 102. In some embodiments, during the process of forming the insulating layer 108, an opening (not shown) may expose at least one of the active regions 106 of the substrate 102. The opening is then filled with a conductive material to form a direct contact 109. The at least one active region contacting the direct contact 109 may be referred to as a source region 106s. The direct contact 109 may be electrically connected to the source region 106s.
[0050] A plurality of bit line structures 110 protrude from the substrate 102. In some embodiments, the bit line structures 110 may be regularly arranged above the substrate 102 at substantially equal intervals from each other. The bit line structures 110 may also include three portions along a vertical direction substantially perpendicular to the substrate 102 (e.g., along the Z-axis direction). For example, each bit line structure 110 may include a metal nitride layer 112, a metal layer 114, and a hard mask layer 116 sequentially stacked on the substrate. The metal nitride layer 112 may be, for example, a titanium nitride layer. The metal layer 114 may be, for example, a tungsten layer. The hard mask layer 116 may be, for example, a silicon nitride layer.
[0051] In some embodiments, before forming the metal nitride layer 112, a pre-metal cleaning operation may be performed on the substrate 102. In addition, in some embodiments, after forming the metal nitride layer 112, a post-metal cleaning operation may be performed on the substrate 102. Other cleaning operations or sub-operations may be optionally applied and are not limited herein. The plurality of bit line structures 110 may be the same or different. The arrangement details of the stacked materials of the bit line structure 110 are not limited herein and may be adjusted according to different applications.
[0052] Figure 3 The comparison example is Figure 2 An enlarged view of box B is shown. Figure 3 As shown, a spacer structure 310 is formed on the bit line structure 110. Specifically, the spacer structure 310 extends along the sidewall of the bit line structure 110. The spacer structure 310 may include a first spacer layer 212, a second spacer layer 214, and a third spacer layer 216 sequentially formed above the bit line structure 110. That is, the second spacer layer 214 is sandwiched between the first spacer layer 212 and the third spacer layer 216. In some embodiments, the second spacer layer 214 includes an oxide. For example, the second spacer layer 214 may include silicon oxide. In some embodiments, the third spacer layer 216 includes silicon nitride. In some embodiments, the first spacer layer 212 includes SiCO having a dielectric constant (k) of approximately 4.3, which is used to reduce parasitic capacitance between the bit line structures 110.
[0053] from Figure 3It can be clearly seen that the first spacer 212 adjacent to the metal layer 114 of the bit line structure 110 is formed with a non-uniform thickness that decreases from the first spacer 212 to the metal layer 114. This is observed when the material of the first spacer 212 does not adhere well to the material of the metal layer 114. For example, when the first spacer 212 is made of SiCO that does not adhere well to the tungsten of the metal layer 114, the first spacer 212 is formed to have a concave profile shape. As a result, the semiconductor device is prone to leakage problems.
[0054] Figure 4 According to various embodiments of the present invention, Figure 2 FIG. 1 is an enlarged view of the intercepted box B shown in FIG. 1 . In order to solve the above leakage current problem, the present invention forms an additional nitride spacer between the SiCO layer and the bit line structure. More specifically, as shown in FIG. Figure 4 As shown, a spacer structure 310 is formed on the bit line structure 110. The spacer structure 310 extends along the sidewall of the bit line structure 110. The spacer structure 310 may include a first spacer layer 311, a second spacer layer 212, a third spacer layer 214, and a fourth spacer layer 216 sequentially formed above the bit line structure 110. That is, the second spacer layer 214 and the third spacer layer 214 are sandwiched between the first spacer layer 212 and the fourth spacer layer 216. In some embodiments, the first spacer layer 311 may include an insulating nitride. For example, the first spacer layer 311 includes silicon nitride. In some embodiments, the second spacer layer 212 includes SiCO. In some embodiments, the third spacer layer 214 may include an insulating oxide. For example, the third spacer layer 214 includes silicon oxide (SiO2). In some embodiments, the fourth spacer layer 216 may include an insulating nitride. For example, the fourth spacer layer 216 may include silicon nitride. The detailed manufacturing process of the spacer structure 310 will be described below.
[0055] Figures 5 to 9 is an enlarged view of a spacer structure 310 at various stages of manufacture according to various embodiments of the present invention. Figure 5 , a first spacer layer 311 is formed on the sidewalls of the bit line structure 110. In some embodiments, the first spacer layer 311 can be formed by any suitable deposition method, such as chemical vapor deposition (CVD) technology, atomic layer deposition (ALD) or physical vapor deposition (PVD) technology. In some embodiments, the first spacer layer 311 has a thickness ranging from about 2 nm to about 20 nm, such as 4 nm, 6 nm, 8 nm, 10 nm, 12 nm, 14 nm, 16 nm or 18 nm.
[0056] Please refer to Figure 6, the second spacer layer 212 is formed on the sidewalls of the first spacer layer 311. In some embodiments, the second spacer layer 212 can be formed by any appropriate deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).
[0057] Please refer to Figure 7 , the third spacer layer 214 is formed on the sidewalls of the second spacer layer 212. In some embodiments, the third spacer layer 214 can be formed by any appropriate deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).
[0058] In some embodiments, the first spacer layer 311 has a first thickness T1, the second spacer layer 212 has a second thickness T2, and the third spacer layer 214 has a third thickness T3. The second thickness T2 is greater than the third thickness T3, and the third thickness T3 is greater than the first thickness T1.
[0059] Please refer to Figure 8 , an oxidation process is performed on the second spacer layer 212, so that an oxidized portion 212b and a remaining portion 212a are formed in the second spacer layer 212, and the oxidized portion 212b is located between the remaining portion 212a and the third spacer layer 214. Specifically, the oxidation process is performed on the third spacer layer 214 and the second spacer layer 212 at the same time. More specifically, the second spacer layer 212 has a first portion 212a and a second portion 212b, and the first portion 212a is located between the first spacer layer 311 and the second portion 212b. In other words, the second spacer layer 212 has a first portion 212a adjacent to the first spacer layer 311 and a second portion 212b away from the first spacer layer 311. That is, the first portion 212a of the second spacer layer 212 is adjacent to the first spacer layer 311, and the second portion 212b of the second spacer layer 212 is adjacent to the third spacer layer 214.
[0060] In some embodiments, the oxidation process is a plasma oxidation process. More specifically, the plasma oxidation process includes O2 and H2N2 plasma oxidation processes. It is noteworthy that after the second spacer layer 212 is subjected to the plasma oxidation process, the second portion 212b of the second spacer layer 212 will be oxidized into a material different from the original material, and part of the third spacer layer 214 will be removed. Therefore, the first portion 212a of the second spacer layer 212 may also be referred to as the remaining portion 212a. In addition, the thickness of the third spacer layer 214 after the plasma oxidation process is performed is less than the thickness of the third spacer layer 214 before the plasma oxidation process is performed. After the electric oxidation process is performed, the material of the second portion 212b includes the same material as the third spacer layer 214. For example, after the plasma oxidation process is performed, the material of the first portion 212a includes SiCO, and the materials of the second portion 212b and the third spacer layer both include SiO2. Therefore, the second portion 212b can be regarded as a portion of the third spacer layer 214 after the oxidation process is performed. It should be understood that the first portion 212a including SiCO has a thickness T2' less than the thickness T2, and the second portion 212b including SiO2 and the third spacer layer 214 have a thickness T3' greater than the thickness T3. It should be noted that the thickness T2' of the first portion 212a is related to the plasma oxidation treatment time. In other words, the longer the treatment time of the plasma oxidation process, the smaller the thickness T2' of the first portion 212a.
[0061] Please refer to Fig. 9 , the fourth spacer 216 is formed on the sidewall of the third spacer 214. In some embodiments, before forming the fourth spacer 216 on the sidewall of the third spacer 214, the second spacer 212 is subjected to an oxidation process. In some embodiments, the fourth spacer 216 can be formed by any suitable deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).
[0062] Please refer to Fig.10In some embodiments, any suitable etching method, such as reactive ion etching (RIE) technology, may be implemented on the first spacer 311, the second spacer 212, the third spacer 214, and / or the fourth spacer 216 to form a specific configuration according to the design of the semiconductor structure. In some embodiments, the first spacer 311, the second spacer 212, the third spacer 214, and the fourth spacer 216 may be etched to expose a portion 110P of the bit line structure 110. Alternatively, in other embodiments, the first spacer 311, the second spacer 212, the third spacer 214, and the fourth spacer 216 may be etched to expose the top surface of the bit line structure 110. In other words, the top surfaces of the first spacer 311, the second spacer 212, the third spacer 214, and the fourth spacer 216 may be flush with the top surface of the bit line structure 110. In some embodiments, Fig.10 The configuration of the flat surface shown is for illustration purposes only. According to some other embodiments of the present invention, other configurations may be formed using different parameters in the etching process.
[0063] Please refer to Fig.11 , a buried contact 410 is formed adjacent to the fourth spacer layer 216. Specifically, the buried contact 410 is disposed between adjacent bit line structures 110 and directly contacts the fourth spacer layer 216. The buried contact 410 includes a silicon-containing material. In some embodiments, the buried contact 410 may include doped polysilicon.
[0064] Please refer to Fig.12 , a landing pad material 420 is formed on the bit line structure 110 and between two adjacent bit line structures 110. In some embodiments, a top surface of the landing pad material 420 is higher than a top surface of the bit line structure 110. Specifically, the landing pad material 420 covers a portion 110P of the bit line structure 110 and side surfaces and top surfaces of the first spacer 311, the second spacer 212, the third spacer 214, and the fourth spacer 216.
[0065] In some embodiments, the landing pad material 420 includes a conductive material. For example, the conductive material is a void-free structure. To achieve a void-free structure, forming the conductive material may include multiple deposition processes and etching processes. In some embodiments, a deposition / etch-back / deposition (dep / etch / dep) process technique is used to deposit the conductive material into a gap (not shown) between two adjacent bit line structures 110. A possible flow of the deposition / etch / deposition process is to first deposit the conductive material, then etch back some of the conductive material to increase the width around the gap opening (not shown), and finally deposit the conductive material again.
[0066] The landing pad material 420 may be deposited by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other suitable deposition process. In some embodiments, the deposition process uses a deposition temperature in the range of about 280° C. to about 320° C. For example, the deposition process uses a deposition temperature of 280° C., 290° C., 300° C., 310° C., or 320° C. The etching process performed after the deposition process includes using any applicable dry etching process and / or wet etching process. The landing pad material 420 may be a stacked material including a metal nitride or a metal, such as tungsten, tungsten nitride, and / or titanium nitride.
[0067] Please refer to Fig.13 , at least a portion of the landing pad material 420 is removed to form the landing pad 430. A mask pattern (not shown) may be formed on the landing pad material 420. Subsequently, the landing pad material 420 is etched using the mask pattern as an etching mask. In some embodiments, a portion of the bit line structure 110, the first spacer 311, the second spacer 212, the third spacer 214, and the fourth spacer 216 disposed on the sidewall thereof, or a portion of the landing pad material 420 may also be removed. After etching, the landing pad 430 is formed, and the landing pads 430 may be separated from each other by the hole 440. In addition, the landing pad 430 is formed based on the landing pad material 420. Therefore, the landing pad 430 may include a void-free structure.
[0068] The above embodiments provide various advantages. Through the above methods and configurations, even if the semiconductor structure of the present invention includes at least four spacer layers, the uniformity of the thickness of each spacer layer can be maintained without increasing the overall thickness of the spacer layer structure, so that the volume of the buried contact subsequently formed in the present invention can be maintained.
[0069] Although the present invention has been disclosed as above in the form of implementation modes, it is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the attached claims.
[0070]
Explanation of symbols
[0071] 100:Semiconductor structure
[0072] 102:Substrate
[0073] 104: Isolation Area
[0074] 106: Active area
[0075] 106s: Source region
[0076] 108: Insulation layer
[0077] 109: Direct contact parts
[0078] 110: Bit line structure
[0079] 110P:Part
[0080] 112: Metal nitride layer
[0081] 114:Metal layer
[0082] 116: Hard Mask Layer
[0083] 212: Spacer layer
[0084] 212a: Part 1
[0085] 212b: Part 2
[0086] 214: Spacer layer
[0087] 216: Spacer layer
[0088] 310: Spacer structure
[0089] 311: Spacer layer
[0090] 410: Embedded contact
[0091] 420: Landing pad material
[0092] 430: Landing Pad
[0093] 440: Hole
[0094] ACT: Active Area
[0095] B: Box
[0096] BC:Buried contact
[0097] BL: Bit Line
[0098] DC: Direct contact
[0099] LP: Landing Pad
[0100] T1: Thickness
[0101] T2: Thickness
[0102] T2':Thickness
[0103] T3:Thickness
[0104] T3':Thickness
[0105] WL: Character Line
[0106] X: Axis
[0107] Y: Axis
[0108] Z: axis.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: Include: forming a bit line structure above the substrate; forming a first spacer layer on a first sidewall of the bit line structure; forming a second spacer layer on the second sidewall of the first spacer layer; forming a third spacer layer on the third sidewall of the second spacer layer; performing an oxidation process on the second spacer layer to form an oxidized portion and a remaining portion in the second spacer layer, wherein the oxidized portion is located between the remaining portion and the third spacer layer; as well as A fourth spacer layer is formed on the fourth sidewall of the third spacer layer. 2 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the first spacer layer comprises insulating nitride. The method for manufacturing a semiconductor structure according to claim 1 , wherein the second spacer layer comprises SiCO. The method for manufacturing a semiconductor structure according to claim 1 , wherein the third spacer layer comprises an insulating oxide. The method for manufacturing a semiconductor structure according to claim 1 , wherein the fourth spacer layer comprises insulating nitride. 6 . The method for manufacturing a semiconductor structure according to claim 1 , wherein performing the oxidation process on the second spacer is performed before forming the fourth spacer on the fourth sidewall of the third spacer. 7 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the oxidized portion of the second spacer layer comprises SiO 2 and the third spacer layer comprises SiO 2 . 8 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the oxidation process is a plasma oxidation process. 9 . The method for manufacturing a semiconductor structure according to claim 8 , wherein the plasma oxidation process comprises an O 2 and H 2 N 2 plasma oxidation process.
10. The method for manufacturing a semiconductor structure according to claim 1, wherein the first spacer layer, the second spacer layer and the third spacer layer have a first thickness, a second thickness and a third thickness respectively, the second thickness is greater than the third thickness, and the third thickness is greater than the first thickness.
11. A method for manufacturing a semiconductor structure, characterized in that: Include: forming a bit line structure above the substrate; forming a first spacer layer on a first sidewall of the bit line structure, wherein the first spacer layer comprises an insulating nitride; Forming a second spacer layer on the second sidewall of the first spacer layer, wherein the second spacer layer comprises SiO2 and has a first portion and a second portion, and the first portion is located between the first spacer layer and the second portion; forming a third spacer layer covering the second portion of the second spacer layer; performing an oxidation process on the second portion of the second spacer layer; forming a fourth spacer layer on the third sidewall of the third spacer layer; as well as A buried contact is formed adjacent to the fourth spacer layer. 12 . The method for manufacturing a semiconductor structure according to claim 11 , wherein the oxidation process is a plasma oxidation process. 13 . The method for manufacturing a semiconductor structure according to claim 12 , wherein the plasma oxidation process comprises an O 2 and H 2 N 2 plasma oxidation process. 14 . The method for manufacturing a semiconductor structure according to claim 12 , wherein the third spacer layer has a first thickness before performing the oxidation process, and has a second thickness after performing the oxidation process, and the second thickness is less than the first thickness. 15 . The method for manufacturing a semiconductor structure according to claim 11 , wherein the third spacer layer comprises an insulating oxide. 16 . The method for manufacturing a semiconductor structure according to claim 11 , wherein the fourth spacer layer comprises insulating nitride. 17 . The method for manufacturing a semiconductor structure according to claim 11 , wherein performing the oxidation process to oxidize the second portion of the second spacer is performed before forming the fourth spacer on the third sidewall of the third spacer.