Semiconductor devices

Abstract

The present invention relates to a semiconductor device. A semiconductor device for suppressing light degradation is provided. The semiconductor device comprises: a light shielding layer; a first silicon nitride insulating layer having a first interface and connected to the light shielding layer; a first silicon oxide insulating layer having a second interface and connected to the first silicon nitride insulating layer; an oxide semiconductor layer on the first silicon oxide insulating layer; a second silicon oxide insulating layer on the oxide semiconductor layer; a gate electrode on the second silicon oxide insulating layer; and a second silicon nitride insulating layer on the gate electrode, wherein the entire channel region of the oxide semiconductor layer overlaps with the light shielding layer when viewed from above, the first silicon oxide insulating layer is connected to the second silicon oxide insulating layer, and the film thickness t of the first silicon nitride insulating layer satisfies the following condition: when light with a wavelength of 450 nm is incident on the first silicon nitride insulating layer at 60 degrees relative to the normal direction of the second interface, the light reflected at the first interface and the light reflected at the second interface attenuate each other.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor film as a channel. Background Art

[0002] In recent years, development of semiconductor devices using oxide semiconductor films as channels instead of silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon, and single crystal silicon is underway (for example, see Patent Documents 1 to 6). Like semiconductor devices including amorphous silicon films, semiconductor devices including oxide semiconductor films can be formed with a simple structure and a low-temperature process. In addition, it is known that semiconductor devices including oxide semiconductor films have higher field effect mobility than semiconductor devices including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] Since an oxide semiconductor film has light-transmitting properties in the visible light region, a semiconductor device including an oxide semiconductor film has less light degradation than a semiconductor device including a silicon semiconductor film. However, it is also desired to further suppress light degradation in a semiconductor device including an oxide semiconductor film.

[0013] One object of one embodiment of the present invention is to provide a semiconductor device that suppresses light degradation.

[0014] Means for solving problems

[0015] A semiconductor device according to one embodiment of the present invention comprises: a light shielding layer; a first silicon nitride insulating layer on the light shielding layer and in contact with the light shielding layer; a first silicon oxide insulating layer on the first silicon nitride insulating layer and in contact with the first silicon nitride insulating layer; an oxide semiconductor layer on the first silicon oxide insulating layer, the oxide semiconductor layer comprising a channel region, a source region, and a drain region; a second silicon oxide insulating layer on the oxide semiconductor layer; a gate electrode on the second silicon oxide insulating layer; and a second silicon nitride insulating layer on the gate electrode, wherein a first interface is formed at Between the light-shielding layer and the first silicon nitride insulating layer, the second interface is formed between the first silicon nitride insulating layer and the first silicon oxide layer. When observed from above, the entire channel region overlaps with the light-shielding layer, the first silicon oxide insulating layer is connected to the second silicon oxide insulating layer, and the film thickness t of the first silicon nitride insulating layer satisfies the following conditions: when light with a wavelength of 450nm is incident on the first silicon nitride insulating layer at 60 degrees relative to the normal direction of the second interface, the first light reflected at the first interface and the second light reflected at the second interface weaken each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] [ Figure 1 ] is a schematic cross-sectional view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0017] [ Figure 2 ] is a schematic top view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0018] [ Figure 3 ] is a flow chart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0019] [ Figure 4 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0020] [ Figure 5 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0021] [ Figure 6 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0022] [ Figure 7 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0023] [ Figure 8 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0024] [ Fig. 9] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0025] [ Fig.10 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0026] [ Fig.11 ] is a schematic cross-sectional view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0027] [ Fig.12 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0028] [ Fig.13 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0029] [ Fig.14 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0030] [ Fig.15 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0031] [ Fig.16 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0032] [ Fig.17 ] is a graph showing the variation in threshold voltage in the NBTIS test relative to the film thickness of the first silicon nitride insulating layer and the film thickness of the first silicon oxide insulating layer.

[0033] [ Fig.18 ] is a simulation result showing the incident angle dependency of the reflectivity of the first silicon nitride insulating layer.

[0034] Description of Reference Numerals

[0035] 10, 20: semiconductor device, 100: substrate, 105: light shielding layer, 110: first silicon nitride insulating layer, 120: first silicon oxide insulating layer, 130: metal oxide layer, 135: metal oxide film, 140: oxide semiconductor layer, 145: oxide semiconductor film, 150: second silicon oxide insulating layer, 160: gate electrode, 170: second silicon nitride insulating layer, 171: opening, 173: opening, 180: third silicon oxide insulating layer, 200: source / drain electrodes, 201: source electrode, 203: drain electrode DETAILED DESCRIPTION

[0036] The following describes various embodiments of the present invention with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily thought of by those skilled in the art while maintaining the spirit of the invention and by appropriately changing the configuration of the embodiment is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, thickness and shape of the constituent elements are sometimes schematically indicated compared to the actual method. However, the illustrated shape is only an example and does not limit the interpretation of the present invention. In this specification and the accompanying drawings, for the constituent elements that are the same as the constituent elements described in the accompanying drawings that have already appeared, there is a case where the same figure mark is marked and the detailed description is appropriately omitted.

[0037] In this specification, etc., the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Like this, for the convenience of explanation, the phrases "above" or "below" are used for explanation, and the up-and-down relationship between the substrate and the oxide semiconductor layer can also be configured in the opposite direction to that shown in the figure. In addition, as for the expression "oxide semiconductor layer on the substrate", it is only to explain the up-and-down relationship between the substrate and the oxide semiconductor layer, and other components can also be configured between the substrate and the oxide semiconductor layer. Above or below refers to the stacking order in a structure in which multiple layers are stacked. In the case of expressing "pixel electrode above the semiconductor device", it can also be a positional relationship in which the semiconductor device and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of expressing "pixel electrode vertically above the semiconductor device", it indicates the positional relationship in which the semiconductor device and the pixel electrode overlap when viewed from above. It should be noted that the top view refers to observation from a direction perpendicular to the surface of the substrate.

[0038] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C. Furthermore, these expressions do not exclude the case where α includes other constituent elements.

[0039] In this specification, "semiconductor device" refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are included in one embodiment of a semiconductor device. The semiconductor device of the embodiment shown below can be, for example, a display device, an integrated circuit (IC) such as a microprocessor (MPU), or a transistor used in a memory circuit.

[0040] In this specification, etc., "display device" refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure on which other optical components (such as a polarizing component, a backlight source, a touch panel, etc.) are installed on a display unit. As long as there is no technical contradiction, the "electro-optical layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, in the embodiment, as a display device, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are described as examples. However, the structure described in the embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0041] In this specification and the like, the term "film" and the term "layer" can be used interchangeably as appropriate.

[0042] It should be noted that the following embodiments can be combined with each other as long as there is no technical contradiction.

[0043] <First embodiment>

[0044] Reference Figures 1 to 10 A semiconductor device 10 according to an embodiment of the present invention will be described.

[0045] [1. Configuration of Semiconductor Device 10]

[0046] Reference Figure 1 and Figure 2 The configuration of a semiconductor device 10 according to an embodiment of the present invention will be described. Figure 1 It is a schematic cross-sectional view showing the structure of a semiconductor device 10 according to one embodiment of the present invention. Figure 2 1 is a schematic top view showing the structure of a semiconductor device according to one embodiment of the present invention. Specifically, Figure 1 For along Figure 2 A cross-sectional view taken along line A-A'.

[0047] like Figure 1As shown, the semiconductor device 10 includes a substrate 100, a light shielding layer 105, a first silicon nitride insulating layer 110, a first silicon oxide insulating layer 120, an oxide semiconductor layer 140, a second silicon oxide insulating layer 150, a gate electrode 160, a second silicon nitride insulating layer 170, a third silicon oxide insulating layer 180, a source electrode 201, and a drain electrode 203. The light shielding layer 105 is disposed on the substrate 100. The first silicon nitride insulating layer 110 covers the upper surface and end surface of the light shielding layer 105 and is disposed on the substrate 100. The first silicon oxide insulating layer 120 is disposed on the first silicon nitride insulating layer 110. The oxide semiconductor layer 140 is disposed on the first silicon oxide insulating layer 120. The second silicon oxide insulating layer 150 covers the upper surface and end surface of the oxide semiconductor layer 140 and is disposed on the first silicon oxide insulating layer 120. The gate electrode 160 overlaps with the oxide semiconductor layer 140 and is provided on the second silicon oxide insulating layer 150. The second silicon nitride insulating layer 170 covers the upper surface and end surface of the gate electrode 160 and is provided on the second silicon oxide insulating layer 150. The third silicon oxide insulating layer 180 is provided on the second silicon nitride insulating layer 170. In the second silicon oxide insulating layer 150, the second silicon nitride insulating layer 170 and the third silicon oxide insulating layer 180, openings 171 and 173 that expose a portion of the upper surface of the oxide semiconductor layer 140 are provided. The source electrode 201 is provided on the third silicon oxide insulating layer 180 and inside the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the third silicon oxide insulating layer 180 and inside the opening 173, and is in contact with the oxide semiconductor layer 140. It should be noted that, hereinafter, when the source electrode 201 and the drain electrode 203 are not particularly distinguished, they may be collectively referred to as the source / drain electrode 200 .

[0048] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH with the gate electrode 160 as a reference. That is, the oxide semiconductor layer 140 includes: a channel region CH overlapping with the gate electrode 160; and a source region S and a drain region D not overlapping with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH is roughly consistent with the end of the gate electrode 160. The channel region CH has the properties of a semiconductor. The source region S and the drain region D each have the properties of a conductor. Therefore, the conductivity of the source region S and the drain region D is greater than the conductivity of the channel region CH. The source electrode 201 and the drain electrode 203 are respectively connected to the source region S and the drain region D, and are electrically connected to the oxide semiconductor layer 140. In addition, the oxide semiconductor layer 140 can be a single-layer structure or a stacked structure.

[0049] like Figure 2As shown, the light shielding layer 105 and the gate electrode 160 each have a certain width in the D1 direction and extend in the D2 direction orthogonal to the D1 direction. In the D1 direction, the width of the light shielding layer 105 is greater than the width of the gate electrode 160. In addition, the entire channel region CH overlaps with the light shielding layer 105. In the semiconductor device 10, the D1 direction corresponds to the direction in which the current flows from the source electrode 201 to the drain electrode 203 via the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0050] The substrate 100 can support each layer constituting the semiconductor device 10. For example, as the substrate 100, a glass substrate, a quartz substrate, or a sapphire substrate, etc., a rigid substrate having light transparency can be used. In addition, as the substrate 100, a silicon substrate, etc., a rigid substrate having no light transparency can also be used. In addition, as the substrate 100, a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate, etc., a flexible substrate having light transparency can be used. In order to improve the heat resistance of the substrate 100, impurities can be introduced into the above-mentioned resin substrate. It should be noted that a substrate having a silicon oxide film or a silicon nitride film formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0051] The light shielding layer 105 can reflect or absorb external light. As described above, the light shielding layer 105 is set to have an area larger than the channel region CH of the oxide semiconductor layer 140, so that it can block the external light incident on the channel region CH from the substrate 100 side. As the light shielding layer 105, a metal material can be used. Specifically, as the light shielding layer 105, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo) or tungsten (W), or their alloys can be used. For example, the alloy used in the light shielding layer 105 is molybdenum tungsten (MoW), but is not limited thereto.

[0052] The first silicon nitride insulating layer 110, the first silicon oxide insulating layer 120, the second silicon nitride insulating layer 170, and the third silicon oxide insulating layer 180 can prevent impurities from diffusing into the oxide semiconductor layer 140. Specifically, the first silicon nitride insulating layer 110 and the first silicon oxide insulating layer 120 can prevent the diffusion of impurities contained in the substrate 100, and the second silicon nitride insulating layer 170 and the third silicon oxide insulating layer 180 can prevent the diffusion of impurities (for example, water, etc.) intruding from the outside. For example, silicon nitride (SiN x ) or silicon oxide nitride (SiN x O y) etc. In addition, silicon oxide (SiO x ) or silicon oxide nitride (SiO x N y ) etc. Here, silicon nitride oxide (SiN x O y ) is a silicon compound containing oxygen at a ratio (x>y) less than nitrogen. x N y ) is a silicon compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O).

[0053] Each of the first silicon nitride insulating layer 110, the first silicon oxide insulating layer 120, the second silicon nitride insulating layer 170, and the third silicon oxide insulating layer 180 may have a planarization function. In addition, the first silicon oxide insulating layer 120 may have a function of releasing oxygen by heat treatment. When the first silicon oxide insulating layer 120 has a function of releasing oxygen by heat treatment, oxygen is released from the first silicon oxide insulating layer 120 by heat treatment performed in the manufacturing process of the semiconductor device 10, and the released oxygen can be supplied to the oxide semiconductor layer 140.

[0054] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys thereof can be used for each of the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a stacked structure.

[0055] The second silicon oxide insulating layer 150 functions as a gate insulating layer. For example, silicon oxide (SiO x ) or silicon oxide nitride (SiO x N y ) etc. The second silicon oxide insulating layer 150 preferably has a composition close to the stoichiometric ratio. In addition, the second silicon oxide insulating layer 150 preferably has few defects. Specifically, the second silicon oxide insulating layer 150 preferably has no defects observed when evaluated by electron spin resonance (ESR).

[0056] As the oxide semiconductor layer 140, an oxide semiconductor containing two or more metal elements including indium (In) can be used. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr) and lanthanide elements can be used. The oxide semiconductor layer 140 may have an amorphous structure or a polycrystalline structure. However, in order to improve electrical characteristics, the oxide semiconductor layer 140 preferably has a polycrystalline structure.

[0057] When the oxide semiconductor layer 140 has a polycrystalline structure, it is preferred to use an oxide semiconductor in which the ratio of indium to all metal elements is 50% or more in atomic ratio as the oxide semiconductor layer 140. If the ratio of indium increases, the oxide semiconductor layer 140 is easily crystallized. In addition, as a metal element other than indium, gallium is preferably included. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 140 is not hindered by gallium, and the oxide semiconductor layer 140 has a polycrystalline structure.

[0058] The detailed manufacturing method of the oxide semiconductor layer 140 is described in the manufacturing method of the semiconductor device 10 described later, but the oxide semiconductor layer 140 can be formed by sputtering. The composition of the oxide semiconductor layer 140 formed by sputtering depends on the composition of the sputtering target. When the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the sputtering target is roughly consistent with the composition of the oxide semiconductor layer 140. In this case, the composition of the metal elements of the oxide semiconductor layer 140 can be determined based on the composition of the metal elements of the sputtering target. In addition, when the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the oxide semiconductor layer 140 can be determined by X-ray diffraction (XRD) method. Specifically, the composition of the metal elements of the oxide semiconductor layer 140 can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer 140 obtained by the XRD method. In addition, the composition of the metal elements of the oxide semiconductor layer 140 can also be determined using fluorescent X-ray analysis or electron probe micro analyzer (Electron Probe Micro Analyzer: EPMA) analysis, etc. It should be noted that the amount of oxygen contained in the oxide semiconductor layer 140 varies depending on the process conditions of sputtering and the like, and is therefore not limited.

[0059] As described above, the oxide semiconductor layer 140 may have an amorphous structure or a polycrystalline structure, preferably a polycrystalline structure. An oxide semiconductor having a polycrystalline structure may be produced using Poly-OS (Poly-crystalline Oxide Semiconductor, polycrystalline silicon oxide semiconductor) technology. Hereinafter, when distinguishing an oxide semiconductor having an amorphous structure from an oxide semiconductor having an amorphous structure, an oxide semiconductor having a polycrystalline structure is sometimes described as Poly-OS.

[0060] The above is a description of the structure of the semiconductor device 10, which is a so-called top-gate transistor. The semiconductor device 10 can be variously modified. For example, when the light shielding layer 105 is conductive, the semiconductor device 10 can be a structure in which the light shielding layer 105 functions as a gate electrode, and the first silicon nitride insulating layer 110 and the first silicon oxide insulating layer 120 function as gate insulating layers. In this case, the semiconductor device 10 is a so-called dual-gate transistor. In addition, when the light shielding layer 105 is conductive, the light shielding layer 105 can be a floating electrode or can be connected to the source electrode 201. In addition, the semiconductor device 10 can also be a so-called bottom-gate transistor in which the light shielding layer 105 functions as a main gate electrode.

[0061] [2. Method for Manufacturing Semiconductor Device 10]

[0062] Reference Figures 3 to 10 A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described. Figure 3 1 is a flowchart showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. Figures 4 to 10 It is a schematic cross-sectional view showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention.

[0063] like Figure 3 As shown, the method for manufacturing the semiconductor device 10 includes steps S1010 to S1110. Steps S1010 to S1110 are described in sequence below, but the order of the steps of the method for manufacturing the semiconductor device 10 may be changed. In addition, the method for manufacturing the semiconductor device 10 may include further steps.

[0064] In step S1010, a light shielding layer 105 having a predetermined pattern is formed on the substrate 100. The light shielding layer 105 is patterned by photolithography. In addition, a first silicon nitride insulating layer 110 and a first silicon oxide insulating layer 120 are formed on the light shielding layer 105 (see Figure 4). The first silicon nitride insulating layer 110 and the first silicon oxide insulating layer 120 are formed by a CVD method. For example, silicon nitride and silicon oxide are formed as the first silicon nitride insulating layer 110 and the first silicon oxide insulating layer 120, respectively. When silicon nitride is used as the first silicon nitride insulating layer 110, the first silicon nitride insulating layer 110 can block impurities diffused from the substrate 100 side to the oxide semiconductor layer 140. When silicon oxide is used as the first silicon oxide insulating layer 120, the first silicon oxide insulating layer 120 can release oxygen by heat treatment.

[0065] Light incident on the first silicon nitride insulating layer 110 is reflected not only at the interface between the light shielding layer 105 and the first silicon nitride insulating layer 110 (hereinafter referred to as the "first interface"), but also at the interface between the first silicon nitride insulating layer 110 and the first silicon oxide insulating layer 120 (hereinafter referred to as the "second interface"). Therefore, if light enhanced by the interference effect is incident on the channel region of the oxide semiconductor layer 140, the photodegradation of the oxide semiconductor layer 140 is promoted. Therefore, in the semiconductor device 10, the film thickness of the first silicon nitride insulating layer 110 is adjusted in such a way that it satisfies the following condition: when light with a wavelength of 450nm is incident on the first silicon nitride insulating layer at 60 degrees relative to the normal direction of the second interface, the light reflected at the first interface and the light reflected at the second interface weaken each other. Thus, the photodegradation of the oxide semiconductor layer 140 can be suppressed. For example, the film thickness t (nm) of the first silicon nitride insulating layer 110 is adjusted so as to satisfy t=150(a-1)+b (where a is a natural number and b is a constant). Here, the constant b is, for example, 75±12.5.

[0066] The thickness of the first silicon oxide insulating layer 120 is not particularly limited. For example, the thickness of the first silicon oxide insulating layer 120 is greater than the thickness of the first silicon nitride insulating layer 110 .

[0067] In step S1020, an oxide semiconductor film 145 is formed on the first silicon oxide insulating layer 120 (see Figure 5 The oxide semiconductor film 145 is formed by sputtering. The thickness of the oxide semiconductor film 145 is, for example, not less than 10 nm and not more than 100 nm, preferably not less than 15 nm and not more than 70 nm, and more preferably not less than 15 nm and not more than 40 nm.

[0068] The oxide semiconductor film 145 in step S1020 is amorphous. In the Poly-OS technology, in order to make the oxide semiconductor layer 140 have a uniform polycrystalline structure within the substrate surface, the oxide semiconductor film 145 after film formation and before heat treatment is preferably amorphous. Therefore, the film formation conditions of the oxide semiconductor film 145 are preferably conditions in which the oxide semiconductor layer 140 is as non-crystallized as possible just after film formation. In the case of forming the oxide semiconductor film 145 by sputtering, the oxide semiconductor film 145 is formed while the temperature of the film-forming object (substrate 100 and the layer formed on the substrate 100) is controlled to be below 100°C, preferably below 80°C, and more preferably below 50°C. In addition, the oxide semiconductor film 145 is formed under conditions of low oxygen partial pressure. The oxygen partial pressure is greater than 2% and less than 20%, preferably greater than 3% and less than 15%, and more preferably greater than 3% and less than 10%.

[0069] In step S1030, the oxide semiconductor film 145 is patterned (see Figure 6 ). The patterning of the oxide semiconductor film 145 is performed by photolithography. As the etching of the oxide semiconductor film 145, wet etching can be used, or dry etching can be used. In wet etching, etching can be performed using an acidic etchant. As the etchant, for example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid can be used.

[0070] In step S1040, the oxide semiconductor film 145 is heat treated. Hereinafter, the heat treatment performed in step S1040 is referred to as "OS annealing". In OS annealing, the oxide semiconductor film 145 is maintained at a specified reaching temperature for a specified time. The specified reaching temperature is greater than 300°C and less than 500°C, preferably greater than 350°C and less than 450°C. In addition, the holding time at the reaching temperature is greater than 15 minutes and less than 120 minutes, preferably greater than 30 minutes and less than 60 minutes. Through OS annealing, the oxide semiconductor film 145 is crystallized to form an oxide semiconductor layer 140 having a polycrystalline structure (i.e., an oxide semiconductor layer 140 containing Poly-OS).

[0071] The oxide semiconductor layer containing Poly-OS has excellent etching resistance. Specifically, with respect to the oxide semiconductor layer 140, the etching rate when etching is performed using an etching solution for wet etching is very small. This means that the oxide semiconductor layer 140 is hardly etched by the etching solution. When the oxide semiconductor layer 140 is etched using an etching solution containing phosphoric acid as a main component (hereinafter referred to as a "mixed acid etching solution") at 40°C, the etching rate is less than 3nm / min, less than 2nm / min, or less than 1nm / min. The proportion of phosphoric acid in the mixed acid etching solution is greater than 50%, greater than 60%, or greater than 70%. In addition to phosphoric acid, the mixed acid etching solution may also contain acetic acid and nitric acid. In an oxide semiconductor film that does not contain Poly-OS, such as an oxide semiconductor film 145 having an amorphous structure before heat treatment, the etching rate when the oxide semiconductor film 145 is etched using a mixed acid etching solution at 40°C is greater than 100nm / min. In addition, when the oxide semiconductor layer 140 is etched using a 0.5% hydrofluoric acid solution at room temperature, the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. It should be noted that in the oxide semiconductor film 145 that does not include Poly-OS, the etching rate when the oxide semiconductor film 145 is etched using a 0.5% hydrofluoric acid solution at room temperature is greater than 15 nm / min. Here, "40°C" refers to 40±5°C, which can be the temperature of the etching solution or the set temperature of the etching solution. In addition, "room temperature" refers to 25±5°C.

[0072] An embodiment of the etching rate of the oxide semiconductor layer 140 is shown in Table 1. Table 1 shows the etching rates of each sample produced in a mixed acid etching solution ("Mixed Acid AT-2F" manufactured by Rasa Industries, Ltd. in which the ratio of phosphoric acid in the mixed acid etching solution is 65%) and a 0.5% hydrofluoric acid solution. In addition, when etching each sample, the temperature of the mixed acid etching solution is 40°C, and the temperature of the 0.5% hydrofluoric acid solution is room temperature. In Table 1, sample 1 is an oxide semiconductor layer 140 including Poly-OS, sample 2 is an oxide semiconductor film 145 having an amorphous structure before heat treatment, and sample 3 is an oxide semiconductor film including indium gallium zinc oxide (IGZO) in which the ratio of indium is less than 50%.

[0073] [Table 1]

[0074] Mixed acid etching solution 0.5% hydrofluoric acid solution Sample 1 <0.1nm / min <2nm / min Sample 2 111nm / min >18nm / min Sample 3 162nm / min -

[0075] As shown in Table 1, for sample 1 (oxide semiconductor layer 140 containing Poly-OS), it is hardly etched using a mixed acid etching solution, and even using a 0.5% hydrofluoric acid solution, it is etched at a maximum rate of only 2 nm / min. In the etching using a mixed acid etching solution, the etching rate of sample 1 is less than 1 / 100 of the etching rate of sample 2 (oxide semiconductor film 145 having an amorphous structure before heat treatment). In the etching using a 0.5% hydrofluoric acid solution, the etching rate of sample 1 is less than about 1 / 10 of the etching rate of sample 2. In addition, in the etching using a mixed acid etching solution, the etching rate of sample 1 is less than 1 / 100 of the etching rate of sample 3 (oxide semiconductor film containing IGZO with an indium ratio of less than 50%). That is, compared with samples 2 and 3, sample 1 has significantly better etching resistance.

[0076] Such excellent etching resistance of the oxide semiconductor layer 140 including Poly-OS is a property that cannot be obtained by a conventional oxide semiconductor having a polycrystalline structure manufactured by a process below 500° C. Although the detailed mechanism of the excellent etching resistance of the oxide semiconductor layer 140 including Poly-OS is not clear, it is believed that Poly-OS has a polycrystalline structure different from the conventional one.

[0077] In step S1050, a second silicon oxide insulating layer 150 is formed on the oxide semiconductor layer 140 (see Figure 7 ). The second silicon oxide insulating layer 150 is formed by a CVD method. For example, as the second silicon oxide insulating layer 150, silicon oxide is formed into a film. In order to reduce defects in the second silicon oxide insulating layer 150, the second silicon oxide insulating layer 150 can be formed at a film forming temperature of 350°C or more. The thickness of the second silicon oxide insulating layer 150 is greater than 50nm and less than 300nm, preferably greater than 60nm and less than 200nm, and more preferably greater than 70nm and less than 150nm. After the second silicon oxide insulating layer 150 is formed, a process of introducing oxygen into a portion of the second silicon oxide insulating layer 150 can be performed.

[0078] The second silicon oxide insulating layer 150 is in contact with the first silicon oxide insulating layer 120 . The total thickness of the first silicon oxide insulating layer 120 and the second silicon oxide insulating layer 150 is preferably greater than the thickness of the first silicon nitride insulating layer 110 .

[0079] In step S1060, the oxide semiconductor layer 140 is heat treated. Hereinafter, the heat treatment performed in step S1060 is referred to as "oxidation annealing". If the second silicon oxide insulating layer 150 is formed on the oxide semiconductor layer 140, a large number of oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer 140. If the oxidation annealing is performed, oxygen is supplied from the first silicon oxide insulating layer 120 and the second silicon oxide insulating layer 150 to the oxide semiconductor layer 140, and the oxygen defects are repaired.

[0080] In step S1070, a gate electrode 160 having a predetermined pattern is formed on the second silicon oxide insulating layer 150 (see Figure 8 ) The gate electrode 160 is formed by sputtering or atomic layer deposition, and the gate electrode 160 is patterned by photolithography.

[0081] In step S1080, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see Figure 8 ). The source region S and the drain region D are formed by ion implantation. Specifically, using the gate electrode 160 as a mask, impurities are implanted into the oxide semiconductor layer 140 via the second silicon oxide insulating layer 150. As the implanted impurities, for example, argon (Ar), phosphorus (P) or boron (B) can be used. In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen defects are generated by ion implantation, and hydrogen is captured by the generated oxygen defects. As a result, the resistance of the source region S and the drain region D is reduced. On the other hand, in the channel region overlapping with the gate electrode 160, no impurities are implanted, so oxygen defects are not generated, and the resistance of the channel region CH is not reduced.

[0082] Note that in the semiconductor device 10 , impurities are implanted into the oxide semiconductor layer 140 via the second silicon oxide insulating layer 150 , and therefore the second silicon oxide insulating layer 150 may contain impurities such as argon (Ar), phosphorus (P), or boron (B).

[0083] In step S1090, a second silicon nitride insulating layer 170 and a third silicon oxide insulating layer 180 are formed on the second silicon oxide insulating layer 150 and the gate electrode 160 (see Fig. 9 ). The second silicon nitride insulating layer 170 and the third silicon oxide insulating layer 180 are formed by CVD. For example, silicon oxide and silicon nitride are formed as the second silicon nitride insulating layer 170 and the third silicon oxide insulating layer 180, respectively. The thickness of the second silicon nitride insulating layer 170 is greater than 50 nm and less than 500 nm. The thickness of the third silicon oxide insulating layer 180 is also greater than 50 nm and less than 500 nm.

[0084] In step S1100, openings 171 and 173 are formed in the second silicon oxide insulating layer 150, the second silicon nitride insulating layer 170, and the third silicon oxide insulating layer 180 (see Fig.10 ). By forming the openings 171 and 173 , the source region S and the drain region D of the oxide semiconductor layer 140 are exposed in the openings 171 and 173 .

[0085] In step S1110, the source electrode 201 is formed on the third silicon oxide insulating layer 180 and inside the opening 171, and the drain electrode 203 is formed on the third silicon oxide insulating layer 180 and inside the opening 173. The source electrode 201 and the drain electrode 203 are formed as the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning a conductive film that has been formed. Through the above steps, a Figure 1 A semiconductor device 10 is shown.

[0086] As mentioned above, the manufacturing method of the semiconductor device 10 is described, but the manufacturing method of the semiconductor device 10 is not limited to this.

[0087] In the semiconductor device 10 according to the present embodiment, light degradation can be suppressed by adjusting the film thickness of the first silicon nitride insulating layer 110 in contact with the light shielding layer 105 to a film thickness based on predetermined conditions.

[0088] <Second embodiment>

[0089] Reference Figures 11 to 16 A semiconductor device 20 according to an embodiment of the present invention will be described. When components of the semiconductor device 20 are the same as components of the semiconductor device 10 , description of the components of the semiconductor device 20 may be omitted.

[0090] [1. Configuration of Semiconductor Device 20]

[0091] Reference Fig.11 The configuration of a semiconductor device 20 according to an embodiment of the present invention will be described. Fig.11 2 is a schematic cross-sectional view showing the structure of a semiconductor device 20 according to an embodiment of the present invention. Specifically, Fig.11 For along Figure 2 A cross-sectional view taken along line A-A'.

[0092] like Fig.11As shown, the semiconductor device 10 includes a substrate 100, a light shielding layer 105, a first silicon nitride insulating layer 110, a first silicon oxide insulating layer 120, a metal oxide layer 130, an oxide semiconductor layer 140, a second silicon oxide insulating layer 150, a gate electrode 160, a second silicon nitride insulating layer 170, a third silicon oxide insulating layer 180, a source electrode 201, and a drain electrode 203. The metal oxide layer 130 is disposed on the first silicon oxide insulating layer 120. The oxide semiconductor layer 140 is disposed on the metal oxide layer 130. The end surface of the metal oxide layer 130 is substantially consistent with the end surface of the oxide semiconductor layer 140.

[0093] The metal oxide layer 130 can promote the crystallization of the oxide semiconductor layer 140. Therefore, if the metal oxide layer 130 is provided, the oxide semiconductor layer 140 is likely to include Poly-OS. As the metal oxide layer 130, for example, aluminum oxide (AlO x ) or aluminum oxide nitride (AlO x N y )wait.

[0094] [2. Method for Manufacturing Semiconductor Device 20]

[0095] Reference Figure 12 to Figure 16 A method for manufacturing the semiconductor device 20 according to one embodiment of the present invention will be described. Fig.12 It is a flowchart showing a method for manufacturing the semiconductor device 20 according to one embodiment of the present invention. Figure 13 to Figure 16 Schematic cross-sectional view showing a method for manufacturing a semiconductor device 20 according to an embodiment of the present invention. The method for manufacturing the semiconductor device 20 includes steps S2010 to S2120. Hereinafter, steps S2010 to S2120 will be described in sequence, but the order of the steps may be replaced in the method for manufacturing the semiconductor device 20. In addition, the method for manufacturing the semiconductor device 20 may also include further steps.

[0096] Step S2010 is the same as step S1010, so the description of step S2010 is omitted.

[0097] In step S2020, a metal oxide film 135 and an oxide semiconductor film 145 are sequentially formed on the first silicon oxide insulating layer 120 (see Fig.13 The metal oxide film 135 is formed by sputtering. The thickness of the metal oxide film 135 is, for example, not less than 1 nm and not more than 10 nm, and preferably not less than 1 nm and not more than 5 nm. It should be noted that the oxide semiconductor film 145 formed on the metal oxide film 135 is in an amorphous state.

[0098] Step S2030 is the same as step S1030. That is, the oxide semiconductor film 145 is patterned (see Fig.14 ).

[0099] Step S2040 is the same as step S1040, so the description of step S2040 is omitted.

[0100] In step S2050, the metal oxide film 135 is patterned to form a metal oxide layer 130 (see Fig.15 ). The oxide semiconductor layer 140 containing Poly-OS, which is fully crystallized by OS annealing, has high etching resistance. Therefore, when the metal oxide film 135 is patterned, the oxide semiconductor layer 140 does not disappear even if the oxide semiconductor layer 140 containing Poly-OS is used as a mask. Therefore, in the Poly-OS technology, the metal oxide layer 130 can be etched using the patterned oxide semiconductor layer 140 containing Poly-OS as a mask. By etching the metal oxide film 135 using the oxide semiconductor layer 140 as a mask, the photolithography process can be omitted. In this case, the end face of the metal oxide layer 130 is roughly consistent with the end face of the oxide semiconductor layer 140. As the etching of the metal oxide film 135, wet etching can be used, and dry etching can also be used. As wet etching, for example, diluted hydrofluoric acid (DHF) can be used.

[0101] Step S2060 is the same as step S1050. That is, the second silicon oxide insulating layer 150 is formed to cover the upper surface and end surface of the oxide semiconductor layer 140 and the end surface of the metal oxide layer 130 (see Fig.16 ).

[0102] Steps S2070 to S2120 are the same as steps S1060 to S1110 , and thus descriptions of steps S2070 to S2120 are omitted.

[0103] As mentioned above, the manufacturing method of the semiconductor device 20 is described, but the manufacturing method of the semiconductor device 20 is not limited to this.

[0104] In the semiconductor device 20 according to the present embodiment, light degradation can be suppressed by adjusting the film thickness of the first silicon nitride insulating layer 110 in contact with the light shielding layer 105 to a film thickness based on predetermined conditions.

[0105] Example

[0106] The semiconductor device 20 will be described in further detail based on the fabricated sample.

[0107] [1. Sample preparation]

[0108] The semiconductor device 20 was manufactured on a glass substrate using the manufacturing method described in the second embodiment. Specifically, a plurality of samples with different film thicknesses (25 nm, 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 175 nm, 200 nm, 225 nm, 250 nm, 275 nm, and 300 nm) of the first silicon nitride insulating layer 110 and film thicknesses (50 nm, 100 nm, and 200 nm) of the first silicon oxide insulating layer 120 were manufactured. The manufacturing conditions of the other layers are common, and the main materials and film thickness manufacturing conditions are shown in Table 2.

[0109] [Table 2]

[0110]

[0111] [2. Evaluation of samples]

[0112] [2-1. Electrical characteristics]

[0113] The electrical characteristics of each sample at the initial stage were measured. The measurement conditions of the electrical characteristics are shown in Table 3. In the measurement of the electrical characteristics, a sample having a channel width W / channel length L=4.5 μm / 3.0 μm was used. In addition, based on the electrical characteristics, the S value and field effect mobility (linear field effect mobility in the linear region) of each sample were calculated.

[0114] [Table 3]

[0115] Source-drain voltage 0.1V Gate voltage -15V~+15V Measurement environment room temperature, dark room

[0116] [2-2. NBTIS test]

[0117] In order to evaluate the photodegradation of each sample, the NBTIS (Negative Bias Temperature Illumination Stress) test was performed. In the NBTIS test, the semiconductor device 20 is irradiated with light for a specified time, and the photodegradation of the semiconductor device 20 can be evaluated based on the change in the threshold voltage of the semiconductor device 20 before and after the light irradiation. Specifically, when the photodegradation of the semiconductor device 20 is large, the variation in the threshold voltage of the semiconductor device 20 also becomes larger. The conditions for light irradiation in the NBTIS test are shown in Table 4. Samples with a channel width W / channel length L=4.5μm / 3.0μm are also used in the NBTIS test, and the electrical characteristics of the samples after light irradiation are measured under the measurement conditions shown in Table 3.

[0118] [Table 4]

[0119] Direction of light In the direction from the gate electrode 160 to the oxide semiconductor layer 140 light source White LED amount of light 7000lx temperature 85℃ Gate voltage -20V Source voltage, drain voltage 0V Irradiation time 1000 seconds

[0120] Fig.17Graphs showing the variation in threshold voltage in an NBTIS test with respect to the film thickness of the first silicon nitride insulating layer 110 and the film thickness of the first silicon oxide insulating layer 120 . Fig.17 The horizontal axis of shows the film thickness of the first silicon nitride insulating layer 110, Fig.17 The vertical axis shows the variation of the threshold voltage in the NBTIS test. Fig.17 In FIG. 1 , points plotted for each film thickness of the first silicon oxide insulating layer 120 are connected.

[0121] like Fig.17 As shown in FIG. 1 , the threshold variation of the semiconductor device 20 shows a periodic tendency with respect to the film thickness of the first silicon nitride insulating layer 110. More specifically, in the semiconductor device 20, the threshold variation decreases as the film thickness of the first silicon nitride insulating layer 110 reaches about 150 nm. In addition, the threshold variation of the semiconductor device 20 does not depend on the film thickness of the first silicon oxide insulating layer 120.

[0122] because Fig.17 The periodicity of the variation in the threshold value of the semiconductor device 20 shown depends on the film thickness of the first silicon nitride insulating layer 110, so it is considered that the optical interference effect is generated by the film thickness of the first silicon nitride insulating layer 110. Therefore, in order to investigate the influence of the optical interference effect generated by the first silicon nitride insulating layer 110, a simulation of the reflectivity when the incident angle (angle relative to the normal direction of the second interface) of the light incident on the first silicon nitride insulating layer 110 is changed is performed. In the simulation, an element formed by the first silicon oxide insulating layer 120 / the first silicon nitride insulating layer 110 / the light shielding layer 105 / glass is used, and the case where the incident light with a wavelength of 400 to 500 nm is reflected at the first interface and the second interface is calculated. It should be noted that, as Fig.17 As shown, since the film thickness dependency of the first silicon oxide insulating layer 120 is not observed, the calculation is performed assuming that light enters from the first silicon oxide insulating layer 120. In other words, the calculation is performed assuming that the film thickness of the first silicon oxide insulating layer 120 is infinite.

[0123] Fig.18 1 is a simulation result showing the incident angle dependency of the reflectivity of the first silicon nitride insulating layer 110 . Fig.18 , the reflectance when the incident angles are 0 degrees, 30 degrees, and 60 degrees is shown.

[0124] like Fig.18 As shown in FIG. 1 , the periodicity of the reflectivity is observed at any of the incident angles of 0, 30, and 60 degrees. In addition, as the incident angle changes from 0 to 60 degrees, the period of the periodicity of the reflectivity increases. Among them, the period at an incident angle of 60 degrees is 150 nm, which is similar to Fig.17The threshold voltage variation period in the NBTIS test shown in FIG. Fig.18 In the case where the film thickness of the first silicon nitride insulating layer 110 is about 75 nm and about 225 nm, the reflectivity becomes extremely small. Fig.17 In the case where the film thickness of the first silicon nitride insulating layer 110 is approximately 75 nm and approximately 225 nm, the variation in the threshold voltage also becomes extremely small.

[0125] The above results show that by setting the film thickness of the first silicon nitride insulating layer 110 so that the reflectivity of the light with a wavelength of 450 nm incident on the second interface at 60 degrees becomes extremely small, the variation of the threshold voltage in the NBTIS test can be suppressed. That is, by setting the film thickness of the first silicon nitride insulating layer 110 to satisfy the following condition, the optical degradation of the semiconductor device 20 can be suppressed: when the light with a wavelength of 450 nm is incident on the first silicon nitride insulating layer at 60 degrees relative to the normal direction of the second interface, the light reflected at the first interface and the light reflected at the second interface weaken each other.

[0126] For example, based on this embodiment, the film thickness t (nm) of the first silicon nitride insulating layer 110 is set to satisfy t=150(a-1)+b (where a is a natural number and b is a constant). Here, the constant b is, for example, 75±12.5. The value ±12.5 in the constant b is an error, which corresponds to 1 / 2 of 25 nm, which is a measured value or a simulated step number. In this way, the error can be calculated based on the step number.

[0127] It should be noted that, in the present embodiment, the evaluation of the sample using the semiconductor device 20 is described, but the same is true for the semiconductor device 10 .

[0128] As the embodiments of the present invention, the embodiments and variations described above can be appropriately combined and implemented as long as they do not contradict each other. In addition, the solutions obtained by those skilled in the art by appropriately adding, deleting, or changing the design of the components based on the embodiments and variations, or the solutions obtained by adding, omitting, or changing the conditions of the processes as long as they have the gist of the present invention, are also included in the scope of the present invention.

[0129] Even if there are other effects different from the effects brought about by the above-mentioned embodiments, effects that are clear from the description of this specification or effects that can be easily predicted by those skilled in the art should of course be regarded as effects brought about by the present invention.

Claims

1. A semiconductor device comprising: Shading layer; a first silicon nitride insulating layer on the light shielding layer and in contact with the light shielding layer; a first silicon oxide insulating layer on the first silicon nitride insulating layer and in contact with the first silicon nitride insulating layer; an oxide semiconductor layer on the first silicon oxide insulating layer, wherein the oxide semiconductor layer includes a channel region, a source region, and a drain region; a second silicon oxide insulating layer on the oxide semiconductor layer; a gate electrode on the second silicon oxide insulating layer; and a second silicon nitride insulating layer on the gate electrode, A first interface is formed between the light shielding layer and the first silicon nitride insulating layer. A second interface is formed between the first silicon nitride insulating layer and the first silicon oxide layer. In a plan view, the entire channel region overlaps with the light shielding layer. The first silicon oxide insulating layer is in contact with the second silicon oxide insulating layer. The film thickness t of the first silicon nitride insulating layer satisfies the following condition: when light with a wavelength of 450 nm is incident on the first silicon nitride insulating layer at 60 degrees relative to the normal direction of the second interface, the first light reflected at the first interface and the second light reflected at the second interface weaken each other.

2. The semiconductor device according to claim 1, wherein: The film thickness t of the first silicon nitride insulating layer satisfies t=150(a-1)+b, where a is a natural number and b is a constant.

3. The semiconductor device according to claim 2, wherein: The b is 75±12.

5.

4. The semiconductor device according to claim 1, wherein: The film thickness of the first silicon oxide insulating layer is greater than the film thickness t of the first silicon nitride insulating layer.

5. The semiconductor device according to claim 1, wherein: The total film thickness of the first silicon oxide insulating layer and the second silicon oxide insulating layer is greater than the film thickness t of the first silicon nitride insulating layer. 6 . The semiconductor device according to claim 1 , further comprising a metal oxide layer between the first silicon oxide insulating layer and the oxide semiconductor layer.

7. The semiconductor device according to claim 6, wherein: An end face of the metal oxide layer is substantially consistent with an end face of the oxide semiconductor layer.

8. The semiconductor device according to claim 6, wherein: The metal oxide layer has a thickness of 5 nm or less.

9. The semiconductor device according to claim 6, wherein: The metal oxide layer includes aluminum oxide.

10. The semiconductor device according to claim 1, wherein The oxide semiconductor layer contains a plurality of metal elements. The plurality of metal elements include indium, The atomic ratio of indium to the plurality of metal elements is 50% or more.

11. The semiconductor device according to claim 1, wherein: The oxide semiconductor layer has a polycrystalline structure.

12. The semiconductor device according to claim 1, wherein: Each of the source region and the drain region includes an element selected from the group consisting of boron, phosphorus, argon, and nitrogen.

Images