A bidirectional gate controlled silicon controlled structure

Abstract

The present invention discloses a bidirectional gate controlled thyristor structure, comprising a first P-type epitaxial layer, a second P-type epitaxial layer, a first N-type deep well doping type well region and a first N-type well doping type well region which are stacked; a first P-type high voltage doping type well region is provided on the first P-type epitaxial layer, a first P-type well doping type well region is provided inside one side of the first P-type high voltage doping type well region, a first P-type heavily doped active region is provided at the top of the other side of the first P-type high voltage doping type well region, a plurality of groups of second P-type heavily doped active regions and first N-type heavily doped active regions arranged in parallel are provided at the top of the first P-type well doping type well region, and the first P-type heavily doped active region and the plurality of groups of first P-type heavily doped active regions and first N-type heavily doped active regions arranged in parallel are isolated from each other. The ring-shaped gate controlled structure of the present invention adjusts the carrier transport path to a deeper level, solving the problems of low voltage maintenance and low current discharge efficiency of the existing thyristor structure.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a bidirectional gate-controlled thyristor structure. Background Art

[0002] High-voltage integrated circuits usually work in relatively harsh working environments, which puts higher design requirements on ESD (electrostatic discharge) protection devices. They need to not only withstand high voltage and large current, but also have a higher maintenance voltage that is higher than the normal operating voltage of the circuit, fundamentally eliminating the risk of latch-up effect.

[0003] The existing SCR (silicon controlled rectifier) ​​structure has a deep hysteresis characteristic, and its trigger voltage is generally much higher than the process gate oxide breakdown voltage, but it also has a very low holding voltage, which is prone to latch-up effect, which greatly limits its application in the field of high-voltage ICs. In addition, the existing thyristor structure may not be able to meet both high holding voltage and extremely high current discharge efficiency when dealing with scenarios that require extremely high current discharge efficiency.

[0004] Based on this, a new technical solution is needed to improve the maintenance voltage and current discharge efficiency of the thyristor structure. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a bidirectional gate-controlled thyristor structure to at least solve the problems of low maintenance voltage and low current discharge efficiency of the existing thyristor structure.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides a bidirectional gate controlled thyristor structure, comprising a first P-type epitaxial layer, a second P-type epitaxial layer, and a first N-type deep well doping type well region and a first N-type well doping type well region stacked between the first P-type epitaxial layer and the second P-type epitaxial layer;

[0008] A first P-type high-voltage doped well region is provided on the first P-type epitaxial layer, a first P-type well-doped well region is provided inside one side of the first P-type high-voltage doped well region, a first P-type heavily doped active region is provided at the top of the other side of the first P-type high-voltage doped well region, a plurality of groups of second P-type heavily doped active regions and first N-type heavily doped active regions arranged in parallel are provided at the top of the first P-type well-doped well region, and the first P-type heavily doped active region and the plurality of groups of the first P-type heavily doped active regions and first N-type heavily doped active regions arranged in parallel are isolated from each other;

[0009] A second P-type high-voltage doped well region is provided on the second P-type epitaxial layer, a second P-type well-doped well region is provided inside one side of the second P-type high-voltage doped well region, a third P-type heavily doped active region is provided at the top of the other side of the second P-type high-voltage doped well region, a plurality of groups of fourth P-type heavily doped active regions and second N-type heavily doped active regions arranged in parallel are provided at the top of the second P-type well-doped well region, and the second P-type heavily doped active region and the plurality of groups of second P-type heavily doped active regions and second N-type heavily doped active regions arranged in parallel are isolated from each other;

[0010] Among them, the first N-type heavily doped active area, the first P-type well doping type well area, the first P-type high voltage doping type well area, the first P-type epitaxial layer, the stacked first N-type deep well doping type well area and the first N-type well doping type well area form a first triode; the second N-type heavily doped active area, the second P-type well doping type well area, the second P-type high voltage doping type well area, the second P-type epitaxial layer, the stacked first N-type deep well doping type well area and the first N-type well doping type well area form a second triode; the first P-type heavily doped active area, the second P-type heavily doped active area, the first P-type well doping type well area, the first P-type high voltage doping type well area, the first P-type epitaxial layer, the stacked first N-type deep well doping type well area and the first N-type well doping type well area, the second P-type epitaxial layer, the second P-type high voltage doping type well area, the first P-type well doping type well area, the third P-type heavily doped active area and the fourth P-type heavily doped type well area form a third triode.

[0011] Further, the emitter of the first triode is connected to port T1, the emitter of the second triode is connected to port T2, the collectors of the first triode and the second triode are connected and then connected to the base of the third triode, and the two emitters of the third triode are respectively connected to the base of the first triode and the base of the second triode.

[0012] Furthermore, the first P-type epitaxial layer, the stacked first N-type deep well doping type well region and the first N-type well doping type well region, and the bottom ends of the second P-type epitaxial layer are provided with N-type heavily doped well regions, and the two ends of the N-type heavily doped well region are respectively provided with two second N-type deep well doping type well regions, and the tops of the two second N-type deep well doping type well regions are provided with two second N-type well doping type well regions, and the two second N-type deep well doping type well regions wrap the two second N-type well doping type well regions, and the two second N-type deep well doping type well regions are correspondingly located on both sides of the first P-type epitaxial layer and the second P-type epitaxial layer away from the stacked first N-type deep well doping type well region and the first N-type well doping type well region.

[0013] Furthermore, a third N-type heavily doped active region and a fourth N-type heavily doped active region are provided at the top of the two second N-type well-doping type well regions, and the third N-type heavily doped active region and the first P-type heavily doped active region, as well as the fourth N-type heavily doped active region and the third P-type heavily doped active region 207 are isolated by shallow trench isolation STI regions.

[0014] Furthermore, it also includes a first polysilicon gate, a second polysilicon ridge, a first metal layer and a second metal layer, wherein the first polysilicon ridge is arranged at the top of the shallow trench isolation STI region and surrounds the first P-type heavily doped active region and multiple groups of second P-type heavily doped active regions and first N-type heavily doped active regions arranged in parallel; the second polysilicon ridge is arranged at the top of the corresponding shallow trench isolation STI region and surrounds the third P-type heavily doped active region and the fourth P-type heavily doped active region and the second N-type heavily doped active region arranged in parallel;

[0015] The first metal layer is connected to the first polysilicon gate and the third N-type heavily doped active region respectively, and the second metal layer is connected to the second polysilicon gate and the fourth N-type heavily doped active region respectively.

[0016] Further, the first P-type heavily doped active region and the plurality of groups of the first P-type heavily doped active regions and the first N-type heavily doped active regions arranged in parallel are isolated and arranged by shallow trench isolation (STI) regions; the second P-type heavily doped active region and the plurality of groups of the second P-type heavily doped active regions and the second N-type heavily doped active regions arranged in parallel are isolated and arranged by shallow trench isolation (STI) regions;

[0017] A shallow trench isolation (STI) region is provided at the top of the first N-type well-doping type well region to isolate the first N-type heavily doped active region from the second N-type heavily doped active region.

[0018] Furthermore, the first polysilicon gate and the second polysilicon gate are both arranged in a ring shape;

[0019] The first polysilicon layer is disposed on one side of a shallow trench isolation STI region at the top of the first N-type well doping type well region and on the top of a shallow trench isolation STI region between the third N-type heavily doped active region and the first P-type heavily doped active region;

[0020] The second polysilicon is disposed on the other side of the shallow trench isolation STI region at the top of the first N-type well doping type well region and on the top of the shallow trench isolation STI region between the fourth N-type heavily doped active region and the third P-type heavily doped active region.

[0021] Further, the emitter region of the first transistor includes the first N-type heavily doped active region, and the first N-type heavily doped active region is connected to the port T1;

[0022] The base of the first transistor is connected to the port T1 through a first resistor.

[0023] Further, the emitter region of the second triode includes the second N-type heavily doped active region, and the second N-type heavily doped active region is connected to the port T2;

[0024] The base of the second transistor is connected to the port T2 via a second resistor.

[0025] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0026] A bidirectional gate-controlled thyristor structure of the present invention adopts a segmented structure to reduce the carrier transport efficiency to improve the holding voltage of the thyristor structure, and adopts a ring-shaped gate-controlled structure to adjust the carrier transport path to a deeper level to improve its current discharge capacity, thereby solving the problems of low holding voltage and low current discharge efficiency of the existing thyristor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A side cross-sectional view of a bidirectional gate-controlled thyristor structure according to an embodiment of the present invention;

[0029] Figure 2 A top view of a bidirectional gate-controlled thyristor structure according to an embodiment of the present invention;

[0030] Figure 3 is a circuit diagram of a first triode, a second triode and a third triode according to an embodiment of the present invention;

[0031] Figure 4 This is an IV diagram of a bidirectional gate-controlled thyristor structure according to an embodiment of the present invention.

[0032] The accompanying drawings of the present invention are as follows:

[0033] 101, second N-type deep well doping type well region; 102, second N-type well doping type well region; 103, third N-type heavily doped active region; 104, first P-type epitaxial layer; 105, first polysilicon gate; 106, first P-type high voltage doping type well region; 107, first P-type heavily doped active region; 108, second P-type heavily doped active region; 109, first P-type well doping type well region; 110, first N-type heavily doped active region;

[0034] 203, fourth N-type heavily doped active region; 204, second P-type epitaxial layer; 205, second polysilicon gate; 206, second P-type high voltage doping type well region; 207, third P-type heavily doped active region; 208, fourth P-type heavily doped active region; 209, second P-type well doping type well region; 210, second N-type heavily doped active region;

[0035] 301, N-type heavily doped well region; 302, shallow trench isolation STI region; 303, first N-type well doping type well region; 304, first N-type deep well doping type well region; 401, first metal layer; 402, second metal layer. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0037] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0038] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0039] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0040] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0041] Currently, the most common way to increase the holding voltage is to reduce the emitter injection efficiency to weaken the positive feedback effect of the parasitic transistor. However, these methods sacrifice the robustness of the device in exchange for a high holding voltage, and often increase the process level, sacrifice the layout area, and increase the manufacturing cost.

[0042] A more effective way to increase the holding voltage is to introduce a device shunt path in the SCR structure (silicon controlled rectifier) ​​to weaken the positive feedback effect of the parasitic NPN and PNP transistors, thereby achieving the purpose of increasing the holding voltage. In addition, the high holding voltage solutions currently proposed for single devices are often only effective for medium and low voltage windows, and are far from meeting the ESD (electrostatic discharge) design window requirements in high-voltage integrated circuits.

[0043] Another relatively effective method is the ESD device stacking technology. The stacking structure is composed of multiple ESD protection devices connected in series, and its maintenance voltage is the sum of the maintenance voltages of the multiple ESD protection devices used. This can effectively solve the problem of insufficient maintenance voltage of a single SCR structure. However, the stacking technology also has defects. As the number of stacked devices increases, its trigger voltage also increases, which may exceed the upper limit of the window of the protection device. In addition, due to the stacking of multiple ESD devices, its opening speed is reduced, and it is difficult to respond quickly to fast ESD events to play an effective role.

[0044] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0045] like Figures 1 to 4 As shown, a bidirectional gate-controlled thyristor structure of the present invention can be applied to conventional size processes, such as 90nmBCD, 130nmBCD processes, and 180nmBCD processes, and a high-maintenance voltage SCR device for ESD protection of high-voltage integrated circuits can meet the design requirements of high maintenance voltage in actual ESD protection, and has extremely high current discharge efficiency. The carrier transport efficiency is reduced by adopting a segmented structure, thereby increasing the maintenance voltage, and the ring-gated structure is used to adjust the carrier transport path to a deeper level, thereby improving its current discharge capacity.

[0046] The bidirectional gate thyristor structure includes a P-type epitaxial layer disposed on a substrate 100 , and the P-type epitaxial layer is divided into a first P-type epitaxial layer 104 and a second P-type epitaxial layer 204 according to different transistors to be formed.

[0047] Specifically, the bidirectional gate controlled thyristor structure includes a first P-type epitaxial layer 104, a second P-type epitaxial layer 204, and a first N-type well doping type well region 303 and a first N-type deep well doping type well region 304 located between the first P-type epitaxial layer 104 and the first P-type epitaxial layer 104 and stacked; a first P-type high-voltage doping type well region 106 is provided on the first P-type epitaxial layer 104, a first P-type well doping type well region 109 is provided inside one side of the first P-type high-voltage doping type well region 106, a first P-type heavily doped active region 107 is provided at the top of the other side of the first P-type high-voltage doping type well region 106, and a first P-type well doping type well region 109 is provided at the top of the first P-type high-voltage doping type well region 106. 9, a plurality of groups of second P-type heavily doped active regions 108 and first N-type heavily doped active regions 110 are provided at the top thereof in parallel, and the first P-type heavily doped active region 107 and the plurality of groups of first P-type heavily doped active regions 107 and first N-type heavily doped active regions 110 are isolated from each other; a second P-type high voltage doping type well region 206 is provided on the second P-type epitaxial layer 204, a second P-type well doping type well region 209 is provided inside one side of the second P-type high voltage doping type well region 206, a third P-type heavily doped active region 207 is provided at the top thereof on the other side, and a plurality of groups of second P-type well doping type well region 209 are provided at the top thereof in parallel. The fourth P-type heavily doped active region 208 and the second N-type heavily doped active region 210, and the second P-type heavily doped active region 108 and the plurality of groups of second P-type heavily doped active regions 108 and second N-type heavily doped active regions 210 arranged in parallel are isolated and arranged; wherein the first N-type heavily doped active region 110, the first P-type well doping type well region 109, the first P-type high voltage doping type well region 106, the first P-type epitaxial layer 104, the stacked first N-type well doping type well region 303 and the first N-type deep well doping type well region 304 form a first triode; the second N-type heavily doped active region 210, the second P-type well doping type well region 209, the second ... The first P-type heavily doped active area 107, the second P-type heavily doped active area 108, the first P-type well-doped type well area 109, the first P-type high-voltage doped type well area 106, the first P-type epitaxial layer 104, the first N-type well-doped well area, the second P-type epitaxial layer 204, the second P-type high-voltage doped type well area 206, the first P-type well-doped type well area 109, the third P-type heavily doped active area 207 and the fourth P-type heavily doped type well area form a third transistor Q3.

[0048] The first P-type epitaxial layer 104 and the second P-type epitaxial layer 204 are both P-type epitaxial layers inherent to the BCD process, and are disposed on the substrate 100 .

[0049] Specifically, an injection region is provided on one side of the first P-type epitaxial layer 104 and one side of the second P-type epitaxial layer 204, and the injection region is arranged along the length direction of the first P-type epitaxial layer 104 and the second P-type epitaxial layer 204, and the injection region on the first P-type epitaxial layer 104 is used to set the first P-type high-voltage doping type well region 106, and the injection region on the second P-type epitaxial layer 204 is used to set the second P-type high-voltage doping type well region 206.

[0050] More specifically, one side of the first P-type high-voltage doping type well region 106 and the second P-type high-voltage doping type well region 206 is provided with an injection region for forming a first P-type well-doping type well region 109 and a second P-type well-doping type well region 209, and the injection region is arranged along the length direction of the first P-type high-voltage doping type well region 106 and the second P-type high-voltage doping type well region 206.

[0051] The implantation region is a specific region in the single crystal silicon structure where N-type or P-type ions are implanted under a high energy electric field.

[0052] Among them, the first P-type heavily doped active area 107, the third P-type heavily doped active area 207, multiple groups of parallel-arranged fourth P-type heavily doped active areas 208 and the second N-type heavily doped active area 210 are all arranged along the length direction of the first P-type high-voltage doping type well area 106 and the second P-type high-voltage doping type well area 206.

[0053] Furthermore, the emitter of the first triode Q1 is connected to the port T1, the emitter of the second triode Q2 is connected to the port T2, the collectors of the first triode Q1 and the second triode Q2 are connected and then connected to the base of the third triode Q3, and the two emitters of the third triode Q3 are respectively connected to the base of the first triode Q1 and the base of the second triode Q2.

[0054] Furthermore, the first P-type epitaxial layer 104, the stacked first N-type well-doped type well region 303 and the first N-type deep well-doped type well region 304, and the bottom of the second P-type epitaxial layer 204 are provided with an N-type heavily doped well region 301, and two second N-type deep well-doped type well regions 101 are respectively provided at both ends of the N-type heavily doped well region 301, and two second N-type well-doped type well regions 102 are provided at the top of the two second N-type deep well-doped type well regions 101, the two second N-type deep well-doped type well regions 101 wrap the two second N-type well-doped type well regions 102, and the two second N-type deep well-doped type well regions 101 are correspondingly located on both sides of the first P-type epitaxial layer 104 and the second P-type epitaxial layer 204 away from the first N-type well-doped type well region 303.

[0055] Specifically, an implantation region is provided at the top of the second N-type deep well doping type well region 101 to form the second N-type well doping type well region 102 .

[0056] Furthermore, a third N-type heavily doped active region 103 and a fourth N-type heavily doped active region 203 are provided at the top of the two second N-type well-doping type well regions 102, and the third N-type heavily doped active region 103 and the first P-type heavily doped active region 107, and the fourth N-type heavily doped active region 203 and the third P-type heavily doped active region 207 are isolated by shallow trench isolation STI regions 302.

[0057] The widths of the third N-type heavily doped active region 103 and the fourth N-type heavily doped active region 203 are both smaller than the width of the corresponding second well-doping type well region 102 .

[0058] Furthermore, it also includes a first polysilicon gate 105, a second polysilicon gate 205, a first metal layer 401 and a second metal layer 402. The first polysilicon gate is arranged at the top of the shallow trench isolation STI region 302, and surrounds the first P-type heavily doped active area 107 and multiple groups of second P-type heavily doped active areas 108 and first N-type heavily doped active areas 110 arranged in parallel; the second polysilicon gate 205 is arranged at the top of the corresponding shallow trench isolation STI region 302, and surrounds the third P-type heavily doped active area 207 and the fourth P-type heavily doped active area 208 and the second N-type heavily doped active area 210 arranged in parallel; the first metal layer 401 is connected to the first polysilicon gate 105 and the third N-type heavily doped active area 103 respectively, and the second metal layer 402 is connected to the second polysilicon gate 205 and the fourth N-type heavily doped active area 203 respectively.

[0059] Furthermore, the first P-type heavily doped active region 107 and the multiple groups of first P-type heavily doped active regions 107 and first N-type heavily doped active regions 110 arranged in parallel are isolated by a shallow trench isolation STI region 302; the second P-type heavily doped active region 108 and the multiple groups of second P-type heavily doped active regions 108 and second N-type heavily doped active regions 210 arranged in parallel are isolated by a shallow trench isolation STI region 302; a shallow trench isolation STI region 302 is provided at the top of the first N-type well-doping type well region 303 to isolate the first N-type heavily doped active region 110 and the second N-type heavily doped active region 210.

[0060] Furthermore, the first polysilicon gate 105 and the second polysilicon gate 205 are both arranged in a ring shape; the first polysilicon gate is arranged on one side of the shallow trench isolation STI region 302 at the top of the first N-type well-doped type well region 303 and on the top of the shallow trench isolation STI region 302 between the third N-type heavily doped active region 103 and the first P-type heavily doped active region 107; the second polysilicon gate 205 is arranged on the other side of the shallow trench isolation STI region 302 at the top of the first N-type well-doped type well region 303 and on the top of the shallow trench isolation STI region 302 between the fourth N-type heavily doped active region 203 and the third P-type heavily doped active region 207.

[0061] Furthermore, the emitter region of the first transistor Q1 includes a first N-type heavily doped active region 110 , and the first N-type heavily doped active region 110 is connected to the port T1 ; the base of the first transistor Q1 is connected to the port T1 through the first resistor R1 .

[0062] Furthermore, the emitter region of the second transistor Q2 includes a second N-type heavily doped active region 210 , and the second N-type heavily doped active region 210 is connected to the port T2 ; the base of the second transistor Q2 is connected to the port T2 via a second resistor R2 .

[0063] The working principle of the present invention is as follows:

[0064] When a forward ESD pulse is applied from port T1, the diode formed by the first N-type well doped type well region 303 and the second P-type epitaxial layer 204 first undergoes avalanche breakdown, forming an avalanche current. In the process of the avalanche current flowing to the right end port, the potential of the N-type heavily doped well region 301N well is reduced, thereby causing the emitter junction of the third transistor Q3 to be forward-conducted, so that the third transistor Q3 is turned on. As the current increases, when a 0.7V voltage drop is generated on the second resistor R2, the emitter junction of the second transistor Q2 is forward-biased and turned on. At this time, the second diode Q2 is turned on. After that, the second transistor Q2 and The third transistor Q3 forms a positive current feedback, thereby constructing a low-resistance SCR discharge path. At the same time, the positive ESD pulse applied at the port T1 is forward biased in the first P-type high-voltage doped well area 106 and the PN junction of the first P-type epitaxial layer 104, so that the third N-type heavily doped active area 103 forms a positive high potential, so that the first polysilicon gate 105 connected thereto through the first metal layer 401 has the same high potential, which makes the P-type doped area under the first polysilicon gate 105 form a downward electric field, so that holes are transported from a deeper level, thereby improving its carrier transportation efficiency. Similarly, when a negative ESD pulse enters from the left end T1, the first transistor Q1 and the third transistor Q3 will form a low-resistance SCR path with positive current feedback.

[0065] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0066] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A bidirectional gate-controlled thyristor structure, characterized in that: It includes a first P-type epitaxial layer, a second P-type epitaxial layer, and a first N-type deep well-doping type well region and a first N-type well-doping type well region stacked between the first P-type epitaxial layer and the first P-type epitaxial layer; A first P-type high-voltage doped well region is provided on the first P-type epitaxial layer, a first P-type well-doped well region is provided inside one side of the first P-type high-voltage doped well region, a first P-type heavily doped active region is provided at the top of the other side of the first P-type high-voltage doped well region, a plurality of groups of second P-type heavily doped active regions and first N-type heavily doped active regions arranged in parallel are provided at the top of the first P-type well-doped well region, and the first P-type heavily doped active region and the plurality of groups of the first P-type heavily doped active regions and first N-type heavily doped active regions arranged in parallel are isolated from each other; A second P-type high-voltage doped well region is provided on the second P-type epitaxial layer, a second P-type well-doped well region is provided inside one side of the second P-type high-voltage doped well region, a third P-type heavily doped active region is provided at the top of the other side of the second P-type high-voltage doped well region, a plurality of groups of fourth P-type heavily doped active regions and second N-type heavily doped active regions arranged in parallel are provided at the top of the second P-type well-doped well region, and the second P-type heavily doped active region and the plurality of groups of second P-type heavily doped active regions and second N-type heavily doped active regions arranged in parallel are isolated from each other; Among them, the first N-type heavily doped active area, the first P-type well doping type well area, the first P-type high voltage doping type well area, the first P-type epitaxial layer, the stacked first N-type deep well doping type well area and the first N-type well doping type well area form a first triode; the second N-type heavily doped active area, the second P-type well doping type well area, the second P-type high voltage doping type well area, the second P-type epitaxial layer, the stacked first N-type deep well doping type well area and the first N-type well doping type well area form a second triode; the first P-type heavily doped active area, the second P-type heavily doped active area, the first P-type well doping type well area, the first P-type high voltage doping type well area, the first P-type epitaxial layer, the stacked first N-type deep well doping type well area and the first N-type well doping type well area, the second P-type epitaxial layer, the second P-type high voltage doping type well area, the first P-type well doping type well area, the third P-type heavily doped active area and the fourth P-type heavily doped type well area form a third triode.

2. The bidirectional gate controlled thyristor structure according to claim 1, characterized in that: The emitter of the first triode is connected to the port T1, the emitter of the second triode is connected to the port T2, the collectors of the first triode and the second triode are connected and then connected to the base of the third triode, and the two emitters of the third triode are respectively connected to the base of the first triode and the base of the second triode.

3. The bidirectional gate controlled thyristor structure according to claim 2, characterized in that: The first P-type epitaxial layer, the stacked first N-type deep well doping type well region and the first N-type well doping type well region, and the bottom of the second P-type epitaxial layer are provided with an N-type heavily doped well region, and the two ends of the N-type heavily doped well region are respectively provided with two second N-type deep well doping type well regions, and the tops of the two second N-type deep well doping type well regions are provided with two second N-type well doping type well regions, and the two second N-type deep well doping type well regions wrap the two second N-type well doping type well regions, and the two second N-type deep well doping type well regions are correspondingly located on both sides of the first P-type epitaxial layer and the second P-type epitaxial layer away from the stacked first N-type deep well doping type well region and the first N-type well doping type well region.

4. The bidirectional gate controlled thyristor structure according to claim 3, characterized in that: A third N-type heavily doped active region and a fourth N-type heavily doped active region are provided at the tops of the two second N-type well-doping type well regions, and the third N-type heavily doped active region and the first P-type heavily doped active region, as well as the fourth N-type heavily doped active region and the third P-type heavily doped active region are isolated by shallow trench isolation (STI) regions.

5. The bidirectional gate controlled thyristor structure according to claim 4, characterized in that: It also includes a first polysilicon gate, a second polysilicon silo, a first metal layer and a second metal layer, wherein the first polysilicon silo is arranged at the top of the shallow trench isolation STI region and surrounds the first P-type heavily doped active region and multiple groups of second P-type heavily doped active regions and first N-type heavily doped active regions arranged in parallel; the second polysilicon silo is arranged at the top of the corresponding shallow trench isolation STI region and surrounds the third P-type heavily doped active region and the fourth P-type heavily doped active region and the second N-type heavily doped active region arranged in parallel; The first metal layer is connected to the first polysilicon gate and the third N-type heavily doped active region respectively, and the second metal layer is connected to the second polysilicon gate and the fourth N-type heavily doped active region respectively.

6. The bidirectional gate controlled thyristor structure according to claim 5, characterized in that: The first P-type heavily doped active region and the plurality of groups of the first P-type heavily doped active regions and the first N-type heavily doped active regions arranged in parallel are isolated by a shallow trench isolation (STI) region; the second P-type heavily doped active region and the plurality of groups of the second P-type heavily doped active regions and the second N-type heavily doped active regions arranged in parallel are isolated by a shallow trench isolation (STI) region; A shallow trench isolation (STI) region is provided at the top of the first N-type well-doping type well region to isolate the first N-type heavily doped active region from the second N-type heavily doped active region.

7. The bidirectional gate controlled thyristor structure according to claim 6, characterized in that: The first polysilicon gate and the second polysilicon gate are both arranged in a ring shape; The first polysilicon layer is disposed on one side of a shallow trench isolation STI region at the top of the first N-type well doping type well region and on the top of a shallow trench isolation STI region between the third N-type heavily doped active region and the first P-type heavily doped active region; The second polysilicon is disposed on the other side of the shallow trench isolation STI region at the top of the first N-type well doping type well region and on the top of the shallow trench isolation STI region between the fourth N-type heavily doped active region and the third P-type heavily doped active region.

8. The bidirectional gate controlled thyristor structure according to any one of claims 1 to 7, characterized in that: The emitter region of the first transistor includes the first N-type heavily doped active region, and the first N-type heavily doped active region is connected to the port T1; The base of the first transistor is connected to the port T1 through a first resistor.

9. The thyristor structure according to claim 8, characterized in that: The emitter region of the second triode includes the second N-type heavily doped active region, and the second N-type heavily doped active region is connected to the port T2; The base of the second transistor is connected to the port T2 via a second resistor.

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