Light emitting diode epitaxial wafer and preparation method thereof
By setting a specific structure of ohmic contact layer on the P-type GaN layer of the LED, the problem of the existing LED ohmic contact layer structure affecting the lattice quality is solved, lower operating voltage and higher luminous efficiency are achieved, and anti-static ability is enhanced.
Patent Information
- Application Number
- CN202411839851.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-08
AI Technical Summary
The ohmic contact layer structure of existing LEDs affects the quality of the lattice, resulting in high contact resistance, high power consumption, low luminous efficiency, and insufficient anti-static ability.
An ohmic contact layer consisting of a heavily doped Mg-doped PP layer, a P-doped InnGa1-nN layer and a P-doped SnyInzGa1-y-zN layer are used to form a good ohmic contact through a high doping form, which improves hole concentration and luminous efficiency, and enhances anti-static ability.
It improves the crystal quality of the LED, increases ohmic contact, reduces the working voltage, improves the luminous efficiency, and enhances the anti-static ability.
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Figure CN119789638A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of light emitting diodes, and in particular to a light emitting diode epitaxial wafer and a preparation method thereof. Background Art
[0002] LED (Light Emitting Diode) is a solid-state lighting source. Nowadays, light-emitting diodes (LEDs), especially GaN-based light-emitting diodes, have been widely used in the fields of solid-state lighting and display, and have been industrialized and used in backlight sources, lighting, landscape lights, etc.
[0003] LED ohmic contact refers to a low-resistance, linear electrical contact formed between metal and semiconductor, which has a vital impact on the performance of LED. Good ohmic contact can make the current pass smoothly between metal and semiconductor, reduce the energy loss caused by contact resistance, thereby reducing the overall power consumption of LED and improving energy efficiency. When the contact resistance is small, the current can be more evenly distributed in the active area of the LED, so that electrons and holes can more effectively recombine to produce photons, thereby improving the luminous efficiency and brightness of the LED. Stable ohmic contact can reduce problems such as local overheating and current crowding caused by poor contact, reduce the failure probability of LED chips during operation, extend their service life, and improve product reliability; at the same time, good ohmic contact can enable the LED to accurately control the luminous intensity and color under the drive of the display signal, and improve the display quality. For example, in a high-definition micro-LED display, the difference in ohmic contact between tiny-sized LED chips may cause uneven display brightness and color, affecting the visual effect.
[0004] Nowadays, the commonly used ohmic contact layer of LEDs is a Mg-doped GaN structure. On the one hand, it will affect the lattice quality and the ohmic contact characteristics need to be further improved; on the other hand, part of the light emitted from the multi-quantum well layer will be absorbed by the P-type GaN layer when passing through the Mg-doped GaN layer, which will also affect the luminous efficiency of the light-emitting diode. Summary of the invention
[0005] The technical problem to be solved by the present invention is: to overcome the deficiencies of the prior art and provide a light-emitting diode epitaxial wafer and a preparation method thereof, which can increase ohmic contact, reduce operating voltage, and effectively increase hole concentration, improve luminous efficiency, and increase antistatic ability.
[0006] The technical solution of the present invention is:
[0007] On the one hand, the present invention provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, an undoped U-GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type GaN layer and an ohmic contact layer are sequentially arranged; wherein the ohmic contact layer comprises a heavily Mg-doped PP layer, a P-type doped In layer, and a P-type GaN layer. n Ga 1-n N layer and P-type doped Sn y In z Ga 1-y-z N layer, n=0.25-0.55, y=0.04-0.25, z=0.05-0.18.
[0008] The ohmic contact layers described in the present invention are all heavily doped P-type layers. Since the surface of the semiconductor material has a high surface state density, it forms a potential barrier when in contact with the metal, and the heavily doped PN junction can generate significant tunnel current. The ohmic contact can be manufactured using the principle of the tunnel effect.
[0009] Heavily doped Mg-doped PP layer and P-type doped In n Ga 1-n The N layer forms a good ohmic contact through high doping. In addition to providing holes, the highly doped Mg atoms can also easily serve as replacement atoms to avoid excessive defects during filling. n Ga 1-n Doping the N layer with an appropriate amount of indium can increase the hole concentration in the P-type semiconductor, thereby improving the hole mobility and further improving the luminous efficiency of the product.
[0010] Preferably, the P-type doped In n Ga 1-n The doping element in the N layer is Mg, and the doping concentration is 1×10 18 -1×10 20 atoms / cm 3 .
[0011] GaN is a wide bandgap semiconductor with high electron mobility and breakdown electric field. The surface state of GaN affects the charge transfer when the metal contacts it. y In z Ga 1-y-z An appropriate amount of Sn metal material in the N layer can adapt well to the surface state of GaN, reduce the Fermi level pinning phenomenon caused by the surface state, and thus reduce the contact resistance.
[0012] Preferably, the P-type doped Sn y In z Ga 1-y-z The doping element in the N layer is Mg, and the doping concentration is 1×10 19 -1×1021 atoms / cm 3 .
[0013] Preferably, the P-type doped In n Ga 1-n The thickness of the N layer is 1.5-4.5 nm.
[0014] Preferably, the P-type doped Sn y In z Ga 1-y-z The thickness of the N layer is 1.5-4.5 nm.
[0015] Preferably, the P-type doped In n Ga 1-n The growth temperature of the N layer is 880-1000°C, the growth pressure is 80-260 torr, and H2 and N2 are introduced as carrier gases.
[0016] Preferably, the P-type doped Sn y In z Ga 1-y-z The growth temperature of the N layer is 700-1000°C, the growth pressure is 80-260 torr, and H2 and N2 are introduced as carrier gases.
[0017] In another aspect, the present invention provides a method for preparing the above-mentioned light-emitting diode epitaxial wafer, comprising the following steps:
[0018] S1 deposits a buffer layer on a substrate;
[0019] S2 deposits an undoped U-GaN layer on the buffer layer;
[0020] S3 deposits an N-type GaN layer on the undoped U-GaN layer;
[0021] S4 deposits a multi-quantum well layer on the N-type GaN layer;
[0022] S5 depositing an electron blocking layer on the multi-quantum well layer;
[0023] S6 depositing a P-type GaN layer on the electron blocking layer;
[0024] S7 deposits an ohmic contact layer on the P-type GaN layer.
[0025] Compared with the prior art, the present invention has the following beneficial effects:
[0026] The light emitting diode epitaxial wafer of the present invention is provided with an ohmic contact layer on the P-type GaN layer, and the ohmic contact layer comprises a heavily Mg-doped PP layer, a P-type doped In layer and a P-type GaN layer. n Ga 1-n N layer and P-type doped Sny In z Ga 1-y-z The N layer is beneficial to improving crystal quality, increasing ohmic contact, and reducing operating voltage; at the same time, it effectively increases hole concentration, improves luminous efficiency, and increases anti-static ability. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is a structural schematic diagram of the light emitting diode epitaxial wafer of the present invention.
[0028] In the figure, 100, substrate; 200, buffer layer; 300, undoped U-GaN layer; 400, N-type GaN layer; 500, multi-quantum well layer; 600, electron blocking layer; 700, P-type GaN layer; 800, ohmic contact layer; 810, PP layer heavily doped with Mg; 820, P-type doped In n Ga 1-n N layer; 830, P-type doped Sn y In z Ga 1-y-z N layers. DETAILED DESCRIPTION
[0029] In order to enable persons skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention.
[0030] The method for preparing a light emitting diode epitaxial wafer of the present invention comprises the following steps:
[0031] S1 provides a substrate 100, which may be a sapphire substrate 100, a Si substrate 100, etc. The substrate 100 needs to be processed, and the processing includes: controlling the temperature of the reaction chamber to 1020-1200° C., performing high-temperature annealing for 2-7 minutes on the substrate 100 in a H2 atmosphere, and cleaning particles and oxides on the surface of the substrate 100;
[0032] S2 deposits a buffer layer 200 on the substrate 100. The buffer layer 200 is an AlGaN buffer layer 200, which is used to provide a seed crystal, alleviate the lattice mismatch between the substrate 100 and the epitaxial layer, and improve the lattice quality of the epitaxial wafer. The thickness of the buffer layer 200 is 20-60nm. The growth conditions of the buffer layer 200 are: the temperature of the reaction chamber is controlled at 620-900°C, the pressure is 50-400torr, the speed of the graphite base is 600-1100r / min, N2 and H2 are used as carrier gases, and N source, Ga source, and Al source are introduced for deposition growth.
[0033] S3 deposits an undoped U-GaN layer 300 on the buffer layer 200, and the thickness of the undoped U-GaN layer 300 is 300-1800nm; the growth conditions are: the temperature of the reaction chamber is controlled at 1000-1150°C, the pressure is 100-500torr; the rotation speed of the graphite base is controlled at 600-1100r / min, N2 and H2 are used as carrier gases, and N source and Ga source are introduced to perform deposition growth;
[0034] S4: depositing an N-type GaN layer 400 on the undoped U-GaN layer 300; the thickness of the N-type GaN layer 400 is 1.2-3 μm; the doping element of the N-type GaN layer 400 is Si; and the doping concentration of Si is 1×10 17 -1×10 20 atoms / cm 3 , mainly used to provide electrons; the growth conditions are: the temperature of the reaction chamber is controlled at 1050-1180℃, the pressure is 100-450torr; the speed of the graphite base is controlled at 600-1100r / min, N2 and H2 are used as carrier gases, and N source, Ga source and Si source are introduced for deposition growth;
[0035] S5 deposits a multi-quantum well layer 500 on the N-type GaN layer 400. The multi-quantum well layer 500 is a periodic structure of alternately stacked InGaN quantum well layers and GaN quantum barrier layers, with a stacking period number of 5-15, wherein the thickness of the InGaN quantum well layer is 2-5nm, and the In component is 0.1-0.35; the thickness of the GaN quantum barrier layer is 6-15nm; the multi-quantum well layer 500 is the region where electrons and holes recombine, and a reasonable structural design can significantly increase the overlap of electron and hole wave functions, thereby improving the luminous efficiency of LED devices; the multi-quantum well layer The growth conditions of 500 (500) are as follows: the reaction chamber pressure is controlled to be 100-500torr, the rotation speed is 600-1000r / min; the reaction chamber temperature is controlled to be 700-830°C, N2 is used as a carrier gas, and N source, Ga source and In source are introduced to grow the InGaN quantum well layer; then, the reaction chamber temperature is controlled to be 800-990°C, the In source is turned off, and Ga source and N source are introduced to grow the GaN quantum barrier layer to complete a cycle of growth; then, the InGaN quantum well layer and the GaN quantum barrier layer are continued to be repeatedly stacked and grown periodically;
[0036] S6: depositing an electron blocking layer 600 on the multi-quantum well layer 500, wherein the electron blocking layer 600 is a periodic structure of an AlGaN layer and an InGaN layer grown alternately, and the number of periods is 3-15; wherein the Al component in the AlGaN layer is 0.05-0.2, and the thickness is 5-10nm; the In component in the InGaN layer is 0.1-0.5, and the thickness is 3-8nm; the growth conditions of the electron blocking layer 600 are: controlling the growth temperature of the reaction chamber to 900-1050°C, the pressure to 100-500torr, the rotation speed to 600-1200r / min, using N2 as a carrier gas, introducing N source, Ga source and Al source to grow the AlGaN layer, then closing the Al source, opening the In source, growing the InGaN layer, completing a growth cycle, and then continuing the periodic growth;
[0037] S7: depositing a P-type GaN layer 700 on the electron blocking layer 600; the thickness of the P-type GaN layer 700 is 200-300 nm; the doping element of the P-type GaN layer 700 is Mg; the doping concentration of Mg is 5×10 17 -1×10 20 atoms / cm 3 ; Too high Mg doping concentration will damage the crystal quality, while low doping concentration will affect the hole concentration; the growth conditions of the P-type GaN layer 700 are: controlling the growth temperature of the reaction chamber to 800-1050°C, the pressure to 120-300torr, the rotation speed to 800-1100r / min, H2 and N2 as carrier gases, and introducing N source, Ga source and Mg source to grow the P-type GaN layer 700;
[0038] S8 depositing an ohmic contact layer 800 on the P-type GaN layer 700:
[0039] S81 The growth temperature of the heavily Mg-doped PP layer 810 is 880-1000° C., exemplarily 880° C., 920° C., 940° C., 980° C., 1000° C., but not limited thereto; the growth pressure is 50-200 torr, exemplarily 50 torr, 100 torr, 150 torr, 200 torr, but not limited thereto; H2 and N2 are introduced as carrier gases;
[0040] S82 P-type doping In n Ga 1-n The growth temperature of the N layer 820 is 880-1000° C., exemplarily 900° C., 940° C., 960° C., 980° C., 990° C., 1000° C., but not limited thereto; the growth pressure is 50-200 torr, exemplarily 50 torr, 100 torr, 150 torr, 200 torr, but not limited thereto; H2 and N2 are introduced as carrier gases;
[0041] S83 P-type doped Sn y In z Ga 1-y-z The growth temperature of the N layer 830 is 700-1000°C, and exemplary ones are 800°C, 840°C, 880°C, 920°C, 980°C, and 1000°C, but not limited thereto; the growth pressure is 50-200torr, and exemplary ones are 50torr, 100torr, 150torr, and 200torr, but not limited thereto; H2 and N2 are introduced as carrier gases.
[0042] Example 1
[0043] The light emitting diode epitaxial wafer of this embodiment is as follows: Figure 1 As shown, the present invention comprises a substrate 100, and a buffer layer 200, an undoped U-GaN layer 300, an N-type GaN layer 400, a multi-quantum well layer 500, an electron blocking layer 600, a P-type GaN layer 700 and an ohmic contact layer 800 sequentially stacked on the substrate 100; wherein the ohmic contact layer 800 comprises a heavily Mg-doped PP layer 810, a P-type doped In layer 810 sequentially stacked on the P-type GaN layer 700, and a P-type doped In layer 810. n Ga 1-n N layer 820 and P-type doped Sn y In z Ga 1-y-z N layer 830.
[0044] The method for preparing a light emitting diode epitaxial wafer of the present embodiment comprises the following steps:
[0045] S1 provides a sapphire substrate 100, and the substrate 100 undergoes the following treatments: the temperature of the reaction chamber is controlled to be 1100° C., and the substrate 100 is subjected to high temperature annealing for 7 minutes in a H2 atmosphere to clean particles and oxides on the surface of the substrate 100;
[0046] S2 deposits a 50 nm thick buffer layer 200 on the substrate 100. The specific growth conditions are: the reaction chamber temperature is controlled at 800°C, the pressure is 100 torr, the rotation speed is 1000 r / min, N2 and H2 are used as carrier gases, NH3 is introduced to provide N source, TMGa is introduced as Ga source, TMAl is introduced as Al source, and AlGaN buffer layer 200 is deposited;
[0047] S3 deposits an 800 nm thick undoped U-GaN layer 300 on the buffer layer 200. The specific growth conditions are: the temperature of the reaction chamber is controlled at 1050°C and the pressure is 100 torr; the rotation speed is controlled at 700 r / min, N2 and H2 are used as carrier gases, NH3 is introduced to provide N source, TMGa is introduced as Ga source, and the undoped U-GaN layer 300 is deposited;
[0048] S4: Deposit a 2 μm thick N-type GaN layer 400 on the undoped U-GaN layer 300, with Si as the doping element and Si doping concentration of 1×10 19 atoms / cm 3 The specific growth conditions are as follows: the temperature of the reaction chamber is controlled at 1060°C and the pressure is 150 torr; the rotation speed is controlled at 1000 r / min, N2 and H2 are used as carrier gases, NH3 is introduced to provide N source, TMGa is introduced as Ga source, SiH4 is introduced as Si source, and the flow rate of Ga source is 660 sccm for deposition growth;
[0049] S5 deposits a multi-quantum well layer 500 on the N-type GaN layer 400, the multi-quantum well layer 500 is a periodic structure of alternately stacked InGaN quantum well layers and GaN quantum barrier layers, the number of stacking periods is 11, wherein the thickness of the InGaN quantum well layer is 2.8nm, the In component is 0.25, and the thickness of the GaN quantum barrier layer is 10nm; the specific growth conditions are: controlling the temperature of the reaction chamber to 790°C, controlling the pressure of the reaction chamber to 200torr, the rotation speed to 600r / min, N2 as a carrier gas, introducing NH3 to provide an N source, introducing TMGa as a Ga source and TMIn as an In source to grow the InGaN quantum well layer; then, controlling the temperature of the reaction chamber to 880°C, turning off the In source, introducing the Ga source and the N source to grow the GaN quantum barrier layer, completing one cycle of growth; then continuing to repeatedly stack the InGaN quantum well layer and the GaN quantum barrier layer to grow periodically;
[0050] S6: depositing an electron blocking layer 600 on the multi-quantum well layer 500, wherein the electron blocking layer 600 is a periodic structure of an AlGaN layer and an InGaN layer grown alternately, and the number of periods is 6; wherein the Al component in the AlGaN layer is 0.1, and the thickness is 10 nm, and the In component in the InGaN layer is 0.3, and the thickness is 8 nm; the specific growth conditions are: controlling the growth temperature of the reaction chamber to 950°C, the pressure to 200 torr, the rotation speed to 1000 r / min, N2 as a carrier gas, introducing NH3 to provide an N source, introducing TMGa as a Ga source and TMAl as an Al source to grow the AlGaN layer; then closing the Al source, continuing to introduce the Ga source and the N source, opening the In source, and using TMIn as an In source to grow the InGaN layer, completing a growth cycle, and then continuing the periodic growth;
[0051] S7: Deposit a 250 nm thick P-type GaN layer 700 on the electron blocking layer 600, and dope the layer with Mg at a concentration of 5×10 18 atoms / cm 3The specific growth conditions are as follows: the growth temperature of the reaction chamber is controlled to be 950° C., the pressure is 200 torr, the rotation speed is 1000 r / min, H2 and N2 are used as carrier gases, NH3 is introduced to provide a N source, TMGa is introduced as a Ga source and Cp2Mg is introduced as a Mg source, and the P-type GaN layer 700 is grown;
[0052] S8: depositing an ohmic contact layer 800 on the P-type GaN layer 700, with specific growth conditions as follows:
[0053] S81 controls the growth temperature of the reaction chamber to 920°C, the pressure to 200 torr, the rotation speed of the graphite susceptor carrying the substrate 100 to 1000 r / min, H2 and N2 as carrier gases, NH3 as N source, TMGa as Ga source and Cp2Mg as Mg source, and grows the heavily Mg-doped PP layer 810 with a thickness of 4 nm and a Mg doping concentration of 8×10 18 atoms / cm 3 ;
[0054] S82: Keep H2 and N2 flowing, control the growth temperature of the reaction chamber to 920℃, the pressure to 200torr, introduce NH3 to provide N source, TMGa as Ga source, TMAl as Al source, TMIn as In source, Cp2Mg as Mg source, and grow P-type doped In n Ga 1-n N layer 820, thickness is 3nm, where n=0.3, Mg doping concentration is 1×10 19 atoms / cm 3 ;
[0055] S83: Keep H2 and N2 flowing, control the growth temperature of the reaction chamber to 920℃, pressure to 200torr, introduce NH3 to provide N source, TMGa as Ga source, TMAl as Al source, TMIn as In source, C8H 20 Sn is used as Sn source, Cp2Mg is used as Mg source, and P-type doped Sn is grown. y In z Ga 1-y-z N layer 830, thickness is 3nm, where y=0.2, z=0.15, Mg doping concentration is 8×10 19 atoms / cm 3 .
[0056] Example 2
[0057] The difference from Example 1 is that: P-type doping In n Ga 1-n In the N layer 820, n=0.4, and the Mg doping concentration is 2×10 19 atoms / cm 3; P-type doped Sn y In z Ga 1-y-z In the N layer 830, y=0.15, z=0.13, and the Mg doping concentration is 9×10 19 atoms / cm 3 .
[0058] Example 3
[0059] The difference from Example 1 is that: P-type doping In n Ga 1-n In the N layer 820, n=0.35, and the Mg doping concentration is 2×10 19 atoms / cm 3 ; P-type doped Sn y In z Ga 1-y-z In the N layer 830, y=0.1, z=0.11, and the Mg doping concentration is 5×10 19 atoms / cm 3 .
[0060] Example 4
[0061] The difference from Example 1 is that: P-type doping In n Ga 1-n In the N layer 820, n=0.45, and the Mg doping concentration is 2×10 19 atoms / cm 3 ; P-type doped Sn y In z Ga 1-y-z In the N layer 830, y=0.11, z=0.14, and the Mg doping concentration is 1×10 20 atoms / cm 3 .
[0062] Example 5
[0063] The difference from Example 1 is that: P-type doping In n Ga 1-n In the N layer 820, n=0.5, and the Mg doping concentration is 3×10 19 atoms / cm 3 ; P-type doped Sn y In z Ga 1-y-z In the N layer 830, y=0.12, z=0.13, and the Mg doping concentration is 1×10 20 atoms / cm 3 .
[0064] Comparative Example 1
[0065] The difference from the first embodiment is that the ohmic contact layer 800 includes a heavily Mg-doped PP layer 810 and a P-type doped In layer 810 sequentially stacked on the P-type GaN layer 700. n Ga 1-n N layer 820.
[0066] Comparative Example 2
[0067] The difference from the first embodiment is that the ohmic contact layer 800 includes a heavily Mg-doped PP layer 810 and a P-type doped Sn-doped P-type GaN layer 700 sequentially stacked on the P-type GaN layer 700. y In z Ga 1-y-z N layer 830.
[0068] Comparative Example 3
[0069] The difference from the first embodiment is that the ohmic contact layer 800 is a P-type GaN layer 700 .
[0070] Comparative Example 4
[0071] The difference from the first embodiment is that the ohmic contact layer 800 includes a heavily Mg-doped PP layer 810, a P-type doped Sn layer 810, and a P-type GaN layer 700. a In b Ga 1-a-b N layer and P-type doped Sn y In z Ga 1-y-z N layer, where a=0.3, b=0.1, y=0.2, z=0.15, P-type doped Sn a In b Ga 1-a-b The Mg doping concentration of the N layer is 1×10 19 atoms / cm 3 , P-type doped Sn y In z Ga 1-y-z The Mg doping concentration of the N layer is 8×10 19 atoms / cm 3 .
[0072] Comparative Example 5
[0073] The difference from the first embodiment is that the ohmic contact layer 800 includes a Si3N4 layer, a three-dimensional InN layer, a metal reflective layer, a P-type doped Al layer, and a P-type GaN layer. x In y Ga 1-x-y N layer and P-type doped Al a In b Ga1- a-bN layer. The thickness of the Si3N4 layer is 3nm, the thickness of the three-dimensional InN layer is 2.5nm, the thickness of the metal reflective layer is 1nm, and the P-type doped Al x In y Ga 1-x-y The thickness of the N layer is 3 nm, x = 0.4, y = 0.07, and the Mg doping concentration is 4×10 18 atoms / cm 3 ; P-type doped Al a In b Ga 1-a- b The thickness of the N layer is 3 nm, a = 0.1, b = 0.13, and the Mg doping concentration is 1×10 20 toms / cm 3 .
[0074] The growth conditions of the ohmic contact layer 800 of Comparative Example 5 are:
[0075] S81: Control the growth temperature of the reaction chamber to 950°C, the pressure to 100 torr, the rotation speed of the graphite susceptor carrying the substrate 100 to 1000 r / min, use H2 and N2 as carrier gases, introduce NH3 to provide N source, and introduce SiH4 to provide Si source to grow a Si3N4 layer;
[0076] S82: H2 is then turned off, the growth temperature of the reaction chamber is controlled to be 600°C, the pressure is 450 torr, NH3 is introduced to provide the N source, and TMIn is introduced as the In source to grow a three-dimensional InN layer;
[0077] S83: Keep H2 off, control the growth temperature of the reaction chamber to 900°C, the pressure to 125 torr, and introduce TMAl as an Al source to grow a metal reflective layer;
[0078] S84 re-introduces H2 and N2 as carrier gases, controls the growth temperature of the reaction chamber to 975°C, the pressure to 100 torr, introduces NH3 to provide N source, TMGa as Ga source, TMAl as Al source, TMIn as In source, and CP2Mg as Mg source to grow the P-type doped Al x In y Ga 1-x-y N layers;
[0079] S85 keeps H2 and N2 flowing, controls the growth temperature of the reaction chamber to 975℃, the pressure to 100torr, introduces NH3 to provide N source, TMGa as Ga source, TMAl as Al source, TMIn as In source, and CP2Mg as Mg source to grow P-type doped Al a In b Ga 1-a- b N layers.
[0080] The epitaxial wafers obtained in Examples 1-5 and Comparative Examples 1-5 were made into 10mil×24mil chips, and the photoelectric performance was tested, and the luminous brightness and working voltage of the obtained chips were tested; and the antistatic performance of the chips was tested: the antistatic performance of the chips was tested using an electrostatic meter under the HBM (Human Body Model) model, that is, the ESD yield of the chips was tested. The test results are shown in Table 1:
[0081] Table 1 Performance test results of epitaxial wafers obtained in Examples 1-5 and Comparative Examples 1-5
[0082] Working voltage(V) Brightness(mW) ESD yield (%) Example 1 3.075 202.4 99.18 Example 2 3.084 202.7 99.25 Example 3 3.081 203.6 99.17 Example 4 3.091 202.3 99.05 Example 5 3.088 202.9 99.12 Comparative Example 1 3.161 196.9 97.75 Comparative Example 2 3.175 196.5 97.23 Comparative Example 3 3.182 195.6 98.62 Comparative Example 4 3.115 200.9 97.8 Comparative Example 5 3.11 199.8 98.9
[0083] As can be seen from Table 1, the present invention sets an ohmic contact layer 800 on the P-type GaN layer 700, and the ohmic contact layer 800 includes a heavily Mg-doped PP layer 810, a P-type doped In n Ga 1-n N layer 820 and P-type doped Sn y In z Ga 1-y-b The N layer 830 is beneficial to improving crystal quality, increasing ohmic contact, and reducing operating voltage; at the same time, it effectively increases hole concentration, improves luminous efficiency, and increases anti-static ability.
Claims
1. A light emitting diode epitaxial wafer, characterized in that: The invention comprises a substrate (100), on which a buffer layer (200), an undoped U-GaN layer (300), an N-type GaN layer (400), a multi-quantum well layer (500), an electron blocking layer (600), a P-type GaN layer (700) and an ohmic contact layer (800) are sequentially arranged; wherein the ohmic contact layer (800) comprises a heavily Mg-doped PP layer (810), a P-type doped In-doped PP layer (810) and a P-type GaN layer (810) which are sequentially arranged on the P-type GaN layer (700). n Ga 1-n N layer (820) and P-type doped Sn y In z Ga 1-y-z N layer (830), n=0.25-0.55, y=0.04-0.25, z=0.05-0.
18.
2. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The P-type doped In n Ga 1-n The doping element in the N layer (820) is Mg, and the doping concentration is 1×10 18 -1×10 20 atoms / cm 3 .
3. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The P-type doped Sn y In z Ga 1-y-z The doping element in the N layer (830) is Mg, and the doping concentration is 1×10 19 -1×10 21 atoms / cm 3 .
4. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The P-type doped In n Ga 1-n The thickness of the N layer (820) is 1.5-4.5 nm.
5. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The P-type doped Sn y In z Ga 1-y-z The thickness of the N layer (830) is 1.5-4.5 nm.
6. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The P-type doped In n Ga 1-n The growth temperature of the N layer (820) is 880-1000°C, the growth pressure is 80-260 torr, and H2 and N2 are introduced as carrier gases.
7. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The P-type doped Sn y In z Ga 1-y-z The growth temperature of the N layer (830) is 700-1000°C, the growth pressure is 80-260 torr, and H2 and N2 are introduced as carrier gases.
8. The method for preparing a light emitting diode epitaxial wafer according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1 depositing a buffer layer (200) on a substrate (100); S2 depositing an undoped U-GaN layer (300) on the buffer layer (200); S3 depositing an N-type GaN layer (400) on the undoped U-GaN layer (300); S4 depositing a multi-quantum well layer (500) on the N-type GaN layer (400); S5: depositing an electron blocking layer (600) on the multi-quantum well layer (500); S6: depositing a P-type GaN layer (700) on the electron blocking layer (600); S7: depositing an ohmic contact layer (800) on the P-type GaN layer (700).