Deep ultraviolet light emitting diode with light scattering structure and method of manufacturing the same

Abstract

The application discloses a deep ultraviolet light emitting diode with light scattering structure and a preparation method thereof. The light emitting diode comprises, in sequence along a wafer epitaxial growth direction, a substrate layer, a buffer layer and an N-type semiconductor transmission layer; wherein the N-type semiconductor transmission layer has an upper and lower part in shape, a multi-quantum well active layer, a P-type semiconductor transmission layer and a P-GaN contact layer are sequentially arranged on the surface of the upper part of the N-type semiconductor transmission layer; and a horizontal direction light scattering structure layer and a vertical direction light scattering structure are respectively arranged in the inner part of the upper and lower parts of the N-type semiconductor transmission layer. The application improves the scattering effect of light in the N-type semiconductor transmission layer, breaks the light waveguide effect of the N-type semiconductor transmission layer, effectively blocks the light propagation to the metal n electrode, simultaneously scatters the light, improves the bottom light extraction efficiency of the deep ultraviolet LED and improves the light extraction efficiency.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode semiconductor technology, and specifically to a deep ultraviolet light-emitting diode with a light-scattering structure. Background Technology

[0002] AlGaN-based deep ultraviolet light-emitting diodes (LEDs) typically use P-GaN material as the P-type ohmic contact layer. However, due to the absorption of deep ultraviolet light by P-GaN, a flip-chip structure is usually employed. This structure causes photons to emerge sequentially from the multi-quantum-well active region through the N-type semiconductor transport layer, buffer layer, and substrate from the bottom of the device, reducing light absorption. However, during photon propagation, an optical waveguide is formed, making it difficult for some light at a fixed angle to escape, which also limits the improvement of light extraction efficiency to some extent. Currently, fabricating micro / nanoscale structures to increase the light extraction efficiency of ultraviolet LEDs is the most common method.

[0003] Current technology proposes using nanospheres or anodic aluminum oxide pores as masks to etch the N-type semiconductor transport layer, roughening the Ga-surface N-type semiconductor transport layer between the mesa and n-electrode (Patent No.: CN112885933 B). Although this method improves the light extraction efficiency to some extent, since the depth of the micro-nano structure (perpendicular to the horizontal direction) of conventional dry etching is only 2-500 nm, and no through-holes are formed in the N-type semiconductor transport layer, a large number of photons will still be transported along the N-type semiconductor to the n-electrode and then absorbed.

[0004] Therefore, based on our group's previous research on the scattering structure of nAlGaN etching, we propose to use electrochemical etching technology to form a dense array of through-holes between the electrode and the mesa step, and inside the N-type semiconductor transport layer. This array can effectively block light from propagating to the metal n electrode, while also scattering light, thereby increasing the light extraction efficiency.

[0005] Invention Patent Content

[0006] The purpose of this invention is to address the shortcomings of current technologies by providing a method for fabricating a deep ultraviolet (LEV) light-emitting diode (LED) with a light-scattering structure. This method involves etching a mesa to expose the N-type semiconductor transport layer, followed by the sequential fabrication of N-type and P-type ohmic electrodes. Then, SiO2 deposition is performed. Holes are created in the SiO2 layer above the etched mesa of the exposed N-type semiconductor transport layer (not covered by the N-type ohmic electrodes), and horizontal and vertical electrochemical etching is performed. After etching, holes are created in the SiO2 layer above the N-type and P-type ohmic electrodes to expose them. This fabricates a LEV with a nanoscale horizontal light-scattering structure (between the N-type ohmic electrode and the mesa step, inside the N-type semiconductor transport layer) within the N-type semiconductor transport layer. This invention patent improves the scattering effect of light inside the N-type semiconductor transport layer, breaks the optical waveguide effect of the N-type semiconductor transport layer, effectively blocks light propagation to the metal n electrode, and at the same time can scatter light, improve the light extraction efficiency of the bottom of the deep ultraviolet LED, and improve the light extraction efficiency.

[0007] The technical solution adopted by this invention patent to solve this technical problem is as follows:

[0008] A deep ultraviolet light-emitting diode with a light-scattering structure, the light-emitting diode comprising, sequentially along the epitaxial growth direction of the chip, a substrate layer, a buffer layer, and an N-type semiconductor transport layer;

[0009] The N-type semiconductor transport layer is divided into two parts: the lower part completely covers the buffer layer, and the upper part consists of two terraces.

[0010] The lower part of the N-type semiconductor transport layer has a thickness of 1–3 μm; the upper part has a thickness of 0.1–3 μm; the angle between the edge length of the trapezoid and the bottom edge is 15–90°; and the rectangular area at the bottom of the trapezoid accounts for 50–90% of the area of ​​the N-type semiconductor transport layer.

[0011] The multi-quantum-well active layer, the P-type semiconductor transport layer, and the P-GaN contact layer are all stepped structures with the same gradient as the N-type semiconductor transport layer 103, and they are sequentially covered on the upper part of the surface of the N-type semiconductor transport layer from bottom to top.

[0012] The P-type ohmic electrode layer is located above the middle of the P-GaN contact layer terrace, and the N-type ohmic electrode layer is located above the middle of the exposed N-type semiconductor transport layer.

[0013] The areas not covered by the N-type ohmic electrode and the P-type ohmic electrode, the outer edge of the N-type ohmic electrode layer, the outer edge of the P-type ohmic electrode layer, and the sidewalls of the terrace are all covered with a SiO2 thin film.

[0014] The interior of the lower part of the N-type semiconductor transport layer, which is not covered by an N-type ohmic electrode layer and is located under the SiO2 thin film, has vertical light scattering structures distributed therein.

[0015] The vertical light scattering structure layer is an array-distributed nano-sized air cavity; the cross-sectional area of ​​the air cavity accounts for 10% to 80% of the exposed area in the lower part of the N-type semiconductor transport layer, and the hole diameter is 20 to 500 nm.

[0016] In the stepped structure of the upper part of the N-type semiconductor transport layer, there are horizontally distributed light scattering structures that penetrate horizontally.

[0017] The horizontal light scattering structure layer is an array-distributed nanoscale air cavity. The cross-sectional area of ​​the air cavity accounts for 10% to 80% of the vertical cross-sectional area of ​​the middle and side portions of the upper part of the N-type semiconductor transport layer, and the aperture diameter is 20 to 500 nm.

[0018] The thickness of the SiO2 thin film is

[0019] The N-type semiconductor transport layer is made of AlGaN, with an Al composition of 45-55% and a Si doping concentration of (1.0E17-9.9E19) / cm³. -3 The thickness of the N-type semiconductor transport layer is 1 to 5 μm, and the surface area of ​​the N-type semiconductor transport film is denoted as S1.

[0020] The exposed area of ​​the N-type semiconductor transport layer is 10% to 60% S1, and the dry etching depth (perpendicular to the horizontal direction) is 1 to 4 μm.

[0021] The N-type semiconductor transport layer is partially exposed, with pits distributed on its surface and a porous structure formed inside. An N-type ohmic electrode covers the exposed N-type semiconductor transport layer.

[0022] The exposed portion of the N-type semiconductor transport layer accounts for 10% to 60% of the total N-type semiconductor transport layer area;

[0023] The substrate is one of sapphire, Si, AlN, SiC or GaN, and the substrate can be a c-plane or a m-plane along the epitaxial growth direction.

[0024] The buffer layer material is Al x1 Ga 1-x1 N; where 0≤x1≤1, 0≤1-x1≤1, and the thickness is 1~5μm.

[0025] The active layer of the multi-quantum well is made of Al. x3 Ga 1-x3 N / Al x4 Ga1-x4 N; where 0≤x3≤1, 0≤1-x3≤1, 0≤x4≤1, 0≤1-x4≤1, the band gap of the quantum barrier should be higher than the band gap of the quantum well, and the number of quantum wells should be greater than or equal to 3; quantum well Al x3 Ga 1-x3 The thickness of N is 0.5–5 nm, and the quantum barrier Al x4 Ga 1-x4 The thickness of N is 3–50 nm.

[0026] The material of the P-type semiconductor transport layer is Al. x6 Ga 1-x6 N; where 0≤x6≤1, 0≤1-x6≤1, and the thickness is 50~250nm.

[0027] The P-GaN layer is made of P-type doped GaN and has a thickness of 2–20 nm.

[0028] The material of the P-type ohmic electrode is Ni / Au, Cr / Au, Pt / Au or Ni / Al, wherein the area of ​​the P-type ohmic electrode accounts for 10% to 80% of the area of ​​the N-type semiconductor transport layer.

[0029] The N-type ohmic electrode is made of Al / Au, Cr / Au, or Ti / Al / Ti / Au, wherein the area of ​​the N-type ohmic electrode accounts for 10% to 50% of the area of ​​the N-type semiconductor transport layer.

[0030] The method for fabricating the deep ultraviolet light-emitting diode with a light-scattering structure includes the following steps:

[0031] The first step involves using MOCVD (metal-organic chemical vapor deposition) technology to sequentially grow an AlN buffer layer, an N-type semiconductor transport layer, a multi-quantum-well active layer, a P-type semiconductor transport layer, and a p-GaN contact layer on a substrate.

[0032] The second step involves dry etching from the P-GaN contact layer to the N-type semiconductor transport layer using photolithography and etching processes, based on the epitaxial material prepared in the first step. The exposed area of ​​the N-type semiconductor transport layer accounts for 10% to 60% of the total N-type semiconductor transport layer area. Then, metal evaporation of the N-type ohmic electrode and the P-type ohmic electrode is performed sequentially.

[0033] The third step involves using a PECVD device to deposit SiO2 on the upper surface and sidewalls of the epitaxial wafer prepared in the second step, followed by dry etching, and then wet etching of the SiO2 film using BOE solution to expose the etching cross-section of the N-type semiconductor transport layer mesa.

[0034] The fourth step is horizontal electrochemical etching. Prepare an acidic electrolyte of 0.1–0.3 mol / L and prepare a conductive metal layer on the side of the epitaxial wafer. Clamp the conductive metal layer of the epitaxial wafer onto the working electrode, set the voltage to 10–30 V, and the electrochemical etching time to 5–60 min. After etching is completed, remove the conductive metal layer.

[0035] The fifth step involves depositing SiO2 on the upper surface and sidewalls of the epitaxial wafer prepared in the fourth step using a PECVD device; then, the SiO2 thin film is dry-etched to expose the etched cross section of the N-type semiconductor transport layer mesa.

[0036] Step 6: Vertical electrochemical etching. Prepare a 0.1–0.5 mol / L alkaline electrolyte and fabricate a conductive metal layer on the side of the epitaxial wafer. Clamp the conductive metal layer of the epitaxial wafer onto the working electrode and set the voltage to 30–50 V for 10–30 min. Then, reset the voltage to 10–30 V, use a 0.1–0.3 mol / L acidic or alkaline electrolyte, and set the electrochemical etching time to 1–60 min. After etching, remove the conductive metal layer.

[0037] Step 7: Based on the above steps, deposit a SiO2 thin film, use a SiO2 mask for photolithography, and perform dry etching after photolithography to expose the N-type ohmic electrode and the P-type ohmic electrode.

[0038] This results in a deep ultraviolet light-emitting diode with a light-scattering structure.

[0039] The beneficial effects of this invention patent are:

[0040] (1) This invention pre-deposits SiO on the N-type semiconductor transport surface. 2， Furthermore, openings are made in the pre-deposited SiO2 thin film layer, extending to the N-type semiconductor transport surface. On the one hand, this can effectively protect the epitaxial layers such as the N-type ohmic electrode, P-type ohmic electrode, and multi-quantum-well active layer from electrochemical corrosion. On the other hand, it guides electrons to preferentially etch the N-type semiconductor transport vertical direction along a specific path, and increases the controllability of the corrosion process.

[0041] (2) The present invention uses a step-by-step electrochemical etching method. On the one hand, acidic electrolyte is used to etch along the horizontal direction (perpendicular to the epitaxial growth direction) to prepare nano-voids in the N-type semiconductor transport layer along the horizontal direction. On the other hand, alkaline electrolyte is used to etch along the vertical direction (parallel to the epitaxial growth direction). First, high voltage and high concentration electrolyte are used to prepare large-diameter nano-voids with vertical orientation by short-time electrochemical etching. Then, low voltage, low concentration and long-time electrochemical etching is used to further guide the electrolyte into the nano-voids through the formed voids, thereby achieving shaping of the voids and homogenization between voids.

[0042] (3) Fabricating nanopores with light-scattering structures in the N-type semiconductor transport epitaxial layer enhances light scattering within the N-type semiconductor transport layer, breaks the optical waveguide effect of the N-type semiconductor transport layer, effectively alters the light propagation path, improves the bottom light extraction efficiency of deep ultraviolet LEDs, and enhances light extraction efficiency. Specifically, this manifests in: Figure 6 It can be seen that, compared with deep ultraviolet light-emitting diodes without scattering structures, deep ultraviolet light-emitting diodes with the light scattering structure described in this invention patent can improve the TE mode light extraction efficiency by 75% and the TM mode light extraction efficiency by 151%.

[0043] (4) The operation process in the preparation method of the deep ultraviolet light-emitting diode with light scattering structure of the present invention is possessed by those skilled in the art. The raw materials involved can be obtained through general means. The process is simple and reliable, highly repeatable, and has low production cost. It is suitable for industrial promotion and can be applied to the field of lasers. Attached Figure Description

[0044] The invention will now be further described with reference to the accompanying drawings.

[0045] Figure 1 This is a schematic diagram of the epitaxial structure of a deep ultraviolet light-emitting diode in current technology.

[0046] Figure 2 This is a schematic diagram of the horizontal electrochemical corrosion exposure portion of the N-type semiconductor transport layer.

[0047] Figure 3 This is a schematic diagram of the vertical electrochemical corrosion exposure portion of the N-type semiconductor transport layer.

[0048] Figure 4 This is a flowchart of the electrochemical etching process for the N-type semiconductor transport layer.

[0049] Figure 5 This is a schematic diagram of a deep ultraviolet light-emitting diode with a light-scattering structure.

[0050] Figure 6 The light extraction efficiency of a deep ultraviolet light-emitting diode with a light scattering structure.

[0051] Among them, 101. Sapphire substrate, 102. AlN buffer layer, 103. N-type semiconductor transport layer, 104. Multiple quantum well active layer, 105. P-type semiconductor transport layer, 106. P-GaN contact layer, 107. SiO2 thin film, 108. P-type ohmic electrode, 109. N-type ohmic electrode, 110. Horizontal light scattering structure, 111. Vertical light scattering structure. Detailed Implementation

[0052] The present invention will be further described below with reference to the embodiments and accompanying drawings, but this should not be construed as limiting the scope of protection of the claims of this application.

[0053] In the description of this invention, unless otherwise stated, "a plurality of" means two or more; the terms "center," "longitudinal," "lateral," "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0054] Example 1

[0055] Please see Figure 5 This invention provides a deep ultraviolet light-emitting diode with a light scattering structure, comprising: a substrate layer 101, a buffer layer 102, and an N-type semiconductor transport layer 103 sequentially along the epitaxial growth direction of the chip;

[0056] The N-type semiconductor transport layer 103 has two parts: the lower part completely covers the buffer layer 102 and has a height of 1.8 μm, denoted as H; the upper part of 103 consists of two rows of ladders (with a bottom spacing of 50.8 μm) and a height of 1.2 μm, denoted as h. The surface of the ladders is rectangular, square, etc. (specifically, a 508 μm * 508 μm square chip in this embodiment). The angle between the edge length of the ladder and the bottom edge is 25°, denoted as θ. The rectangular area at the bottom of the ladder accounts for approximately 70% of the area of ​​the N-type semiconductor transport layer 103.

[0057] The multi-quantum well active layer 104, the P-type semiconductor transport layer 105, and the P-GaN contact layer 106 are all stepped platforms with the same gradient as the N-type semiconductor transport layer 103, and they cover the upper part of the surface of the N-type semiconductor transport layer 103 from bottom to top.

[0058] Let L be the length of the bottom side of the aforementioned platform and W be the length of the top side. Then W = Lh / tanθ.

[0059] The surface area of ​​the N-type semiconductor transport film (i.e., the projected area of ​​the underlying layer) is denoted as S1;

[0060] The P-type ohmic electrode 108 layer is located above the middle of the P-GaN contact layer 106 terrace, and the N-type ohmic electrode layer 109 is located above the middle of the exposed N-type semiconductor transport layer (i.e., the lower part of the N-type semiconductor transport layer) 103.

[0061] The areas not covered by the N-type ohmic electrode and the P-type ohmic electrode, the outer edge of the N-type ohmic electrode layer 109, the outer edge of the P-type ohmic electrode layer 108, and the sidewalls of the terrace are all covered with a SiO2 thin film 107.

[0062] Inside the lower portion of the N-type semiconductor transport layer 103, which is not covered by the N-type ohmic electrode layer 109 and is located below the SiO2 thin film 107, there are vertical light scattering structures 111.

[0063] The vertical light scattering structure layer is located between the N-type ohmic electrode and the MESA etching mesa, extending from the upper surface of the portion exposed at 103 but not covered by the N-type ohmic electrode to the upper surface of 102. It consists of nanoscale air cavities with an array distribution. The cross-section of a single air cavity is rectangular, with an array air cavity surface area of ​​approximately (20±2)%S1, a width (parallel to the horizontal direction) of approximately 80–100 nm, a length (perpendicular to the horizontal direction) of approximately 1.8 μm, and a period (distance between the centers of adjacent rectangles) of 100 nm–300 nm.

[0064] In the stepped structure of the upper part of the N-type semiconductor transport layer 103, there are horizontal light scattering structures 110 distributed in the horizontal direction, which penetrate 103 in the horizontal direction.

[0065] The horizontal light scattering structure layer is located inside the N-type semiconductor transport layer. It consists of nano-sized air cavities with an array distribution feature. The cross-section of each air cavity is circular. The cross-sectional area of ​​the air cavity accounts for approximately (70±2)% of the vertical cross-sectional area of ​​the middle and side parts of the upper part of the N-type semiconductor transport layer. The diameter is approximately 40-60 nm, the period (center-to-center distance) is 40-80 nm, and the distribution area accounts for 4 / 5 of the thickness of the N-type semiconductor transport layer in the vertical direction.

[0066] The deep ultraviolet light-emitting diode with light scattering structure has a square shape when projected from top to bottom.

[0067] The sapphire substrate is square, with dimensions of 508*508μm, and a thickness of 430μm along the

[0001] direction;

[0068] The thickness of the SiO2 thin film 107 is

[0069] The N-type semiconductor transport layer contains an Al composition of (50±5)% and an n-type doping concentration of 1.0E18 / cm³. -3The thickness is 3μm, and the surface area of ​​the N-type semiconductor transport film is denoted as S1.

[0070] The exposed area of ​​the N-type semiconductor transport layer is 30%S1, and the dry etching depth (perpendicular to the horizontal direction) is 1.2μm.

[0071] The N-type ohmic electrode layer 109 has an area of ​​10% Si, and the P-type ohmic electrode layer 108 has an area of ​​60% Si.

[0072] The active layer of the multi-quantum well is made of Al. 0.7 Ga 0.3 N / Al 0.5 Ga 0.5 N; The band gap of the quantum barrier should be higher than the band gap of the quantum well. The number of quantum wells is equal to 3, and the number of quantum barriers is equal to 4; A single quantum well Al 0.7 Ga 0.3 The thickness of N is 4 nm, and the single quantum barrier Al 0.5 Ga 0.5 The thickness of N is 10 nm.

[0073] The material of the P-type semiconductor transport layer is Al. 0.5 Ga 0.5 N, with a thickness of 48nm.

[0074] The P-GaN layer is made of P-type doped GaN, with Mg as the doping agent and a doping concentration of approximately 1.0E18 / cm³. -3 The thickness is 10nm.

[0075] The above-mentioned deep ultraviolet LED chip structure with light scattering structure is fabricated as follows:

[0076] The first step involves using MOCVD (metal-organic chemical vapor deposition) technology to sequentially grow an AlN buffer layer, an N-type semiconductor transport layer, a multi-quantum well active layer, a P-type semiconductor transport layer, and a P-GaN contact layer on a c-plane sapphire substrate. These layers constitute the basic structure of the epitaxial wafer.

[0077] The second step involves dry etching from the P-GaN contact layer to the N-type semiconductor transport layer using photolithography and etching processes, based on the epitaxial material prepared in the first step. The dry etching depth of the N-type semiconductor transport layer is approximately 1.2 μm, and the exposed portion accounts for 30% of the N-type semiconductor transport layer. Then, Ti-Al-Ti-Au is deposited on the N-type ohmic electrode and Ni-Au is deposited on the P-type ohmic electrode in sequence.

[0078] The third step involves SiO2 deposition using a PECVD device, with a deposition thickness of [missing information]. Dry etching, followed by wet etching of the SiO2 film using BOE solution, such as... Figure 2 As shown.

[0079] The fourth step is horizontal electrochemical etching. Prepare a 0.1 mol / L HNO3 electrolyte and prepare a conductive metal layer (indium or tin) on the side of the epitaxial wafer. Clamp the conductive metal layer of the epitaxial wafer onto the working electrode, set the voltage to 30V, and set the electrochemical etching time to 5 minutes. After etching is completed, remove the conductive metal layer.

[0080] The mechanism is that, under the protection of the SiO2 insulating layer, conductive electrons are transversely transported along the N-type semiconductor transport layer above 103 that is not covered by SiO2, resulting in the minimum equivalent resistance. Furthermore, the electrolyte mass / ion transport direction is horizontal, thus causing corrosion in the horizontal direction. In this case, the corroded part of the sample is immersed in the electrolyte, while the conductive metal layer is not immersed.

[0081] The fifth step involves SiO2 deposition using a PECVD device, with a deposition thickness of [missing information]. Dry etching of SiO2 thin films, such as Figure 3 As shown.

[0082] Step 6: Vertical electrochemical etching. Prepare a 0.3 mol / L KOH electrolyte and prepare a conductive metal layer on the side of the epitaxial wafer. Clamp the conductive metal layer of the epitaxial wafer onto the working electrode, set the voltage to 40V, and the electrochemical etching time to 5min. Remove the sample, reset the voltage to 15V, use a 0.1 mol / L KOH solution as the electrolyte, and perform electrochemical etching for 30min. After etching is complete, remove the conductive metal layer.

[0083] The mechanism is as follows: under the protection of the SiO2 insulating layer, conductive electrons are transported from bottom to top along the N-type semiconductor transport layer between the N-type ohmic electrode and the MESA etching mesa. At this time, the equivalent resistance is the minimum, and the electrolyte mass / ion transport direction is along the vertical direction, so the corrosion is carried out in the vertical direction. First, a high voltage and a high concentration of electrolyte are used to prepare large-pore nanopores with vertical orientation through short-time electrochemical corrosion. Then, a low voltage and a low concentration are used to conduct a relatively mild reaction for a long time. Based on the first step of electrochemical corrosion, the electrolyte is preferentially guided into the nanopores through the formed pores, thereby achieving the shaping of the pores and the homogenization between pores.

[0084] Step 7: Based on the above steps, deposit a SiO2 thin film, use a SiO2 mask for photolithography, and perform dry etching after photolithography to expose the N-type ohmic electrode and the P-type ohmic electrode.

[0085] This results in a deep ultraviolet LED with a light scattering structure, as described in this embodiment. Figure 5 As shown.

[0086] In this embodiment, by fabricating nanopores with light-scattering structures in the N-type semiconductor transport epitaxial layer, the scattering of light within the N-type semiconductor transport layer is enhanced, breaking the optical waveguide effect of the N-type semiconductor transport layer. This effectively alters the light propagation path, improving the bottom light extraction efficiency of the deep ultraviolet LED and increasing light extraction efficiency. Figure 6 As shown (using 2D-FDTD simulation software), compared with deep ultraviolet light-emitting diodes without scattering structures, the deep ultraviolet light-emitting diodes with the light scattering structure described in this invention patent can improve the TE mode light extraction efficiency by 75% and the TM mode light extraction efficiency by 151%.

[0087] Example 2

[0088] The other steps are the same as in Example 1, except that the HNO3 solution is replaced with an oxalic acid solution at a concentration of 0.1 mol / L; the properties of the resulting material are similar.

[0089] All the raw materials involved in this invention patent can be obtained through known means, and the operation process in its preparation method can be mastered by those skilled in the art.

[0090] Any aspects not covered in this patent are applicable to the prior art.

Claims

1. A method for fabricating a deep ultraviolet light-emitting diode with a light-scattering structure, characterized in that, Includes the following steps: The first step involves using MOCVD (metal-organic chemical vapor deposition) technology to sequentially grow an AlN buffer layer, an N-type semiconductor transport layer, a multi-quantum-well active layer, a P-type semiconductor transport layer, and a p-GaN contact layer on a substrate. The second step involves dry etching from the P-GaN contact layer to the N-type semiconductor transport layer using photolithography and etching processes, based on the epitaxial material prepared in the first step. The exposed area of ​​the N-type semiconductor transport layer accounts for 10% to 60% of the total N-type semiconductor transport layer area. Then, metal evaporation is performed sequentially on the N-type ohmic electrode layer and the P-type ohmic electrode layer. The third step involves using a PECVD device to deposit SiO2 on the upper surface and sidewalls of the epitaxial wafer prepared in the second step, followed by dry etching, and then wet etching of the SiO2 film using BOE solution to expose the etching cross-section of the N-type semiconductor transport layer mesa. The fourth step is horizontal electrochemical etching. Prepare an acidic electrolyte of 0.1~0.3 mol / L, and prepare a conductive metal layer on the side of the epitaxial wafer. Clamp the conductive metal layer of the epitaxial wafer on the working electrode, set the voltage to 10~30V, and the electrochemical etching time to 5~60min. After etching is completed, remove the conductive metal layer. The fifth step involves depositing SiO2 on the upper surface and sidewalls of the epitaxial wafer prepared in the fourth step using a PECVD device; then, the SiO2 thin film is dry-etched to expose the etched cross section of the N-type semiconductor transport layer mesa. Step 6: Vertical electrochemical etching. Prepare a 0.1~0.5 mol / L alkaline electrolyte and fabricate a conductive metal layer on the side of the epitaxial wafer. Clamp the conductive metal layer of the epitaxial wafer onto the working electrode and set the voltage to 30~50V for 10s~30min. Then, reset the voltage to 10~30V, use a 0.1~0.3 mol / L acidic or alkaline electrolyte, and set the electrochemical etching time to 1~60min. After etching, remove the conductive metal layer. Step 7: Based on the above steps, deposit a SiO2 thin film, use a SiO2 mask for photolithography, and perform dry etching after photolithography to expose the N-type ohmic electrode layer and the P-type ohmic electrode layer.

2. The deep ultraviolet light-emitting diode with a light-scattering structure prepared by the method described in claim 1, characterized in that, The deep ultraviolet light-emitting diode comprises, along the epitaxial growth direction of the chip, a substrate layer, a buffer layer, and an N-type semiconductor transport layer. The N-type semiconductor transport layer is divided into two parts: the lower part completely covers the buffer layer, and the upper part consists of two terraces. The multi-quantum-well active layer, the P-type semiconductor transport layer, and the P-GaN contact layer are all stepped structures with the same gradient as the N-type semiconductor transport layer, and they are sequentially covered from bottom to top on the upper part of the N-type semiconductor transport layer. The P-type ohmic electrode layer is located above the middle of the P-GaN contact layer terrace, and the N-type ohmic electrode layer is located above the middle of the exposed N-type semiconductor transport layer. The areas not covered by the N-type ohmic electrode layer and the P-type ohmic electrode layer, the outer edge of the N-type ohmic electrode layer, the outer edge of the P-type ohmic electrode layer, and the sidewalls of the terrace are all covered with a SiO2 thin film. The interior of the lower part of the N-type semiconductor transport layer, which is not covered by an N-type ohmic electrode layer and is located under the SiO2 thin film, has vertical light scattering structures distributed therein. The vertical light scattering structure layer is an array-distributed nano-sized air cavity; the cross-sectional area of ​​the air cavity accounts for 10% to 80% of the exposed area in the lower part of the N-type semiconductor transport layer, and the hole diameter is 20 to 500 nm. In the stepped structure of the upper part of the N-type semiconductor transport layer, there are horizontally distributed light scattering structures that penetrate horizontally. The horizontal light scattering structure layer is an array-distributed nano-sized air cavity; the cross-sectional area of ​​the air cavity accounts for 10% to 80% of the vertical cross-sectional area of ​​the middle and side parts of the upper part of the N-type semiconductor transport layer, and the hole diameter is 20 to 500 nm.

3. The deep ultraviolet light-emitting diode with a light-scattering structure as described in claim 2, characterized in that, The N-type semiconductor transport layer is made of Al. X Ga 1-X N, where Al composition X = 45~55%, Si doping concentration (1.0E17~9.9E19) / cm³ -3 The thickness of the N-type semiconductor transport layer is 1~5μm; The exposed portion of the N-type semiconductor transport layer accounts for 10% to 60% of the total N-type semiconductor transport layer area.

4. The deep ultraviolet light-emitting diode with a light-scattering structure as described in claim 2, characterized in that, The lower part of the N-type semiconductor transport layer has a thickness of 1~3μm; the upper part has a thickness of 0.1~3μm; the angle between the edge length of the trapezoid and the bottom edge is 15~90°; the rectangular area at the bottom of the trapezoid accounts for 50~90% of the area of ​​the N-type semiconductor transport layer.

5. The deep ultraviolet light-emitting diode with a light-scattering structure as described in claim 2, characterized in that, The substrate is one of sapphire, Si, AlN, SiC or GaN, and the substrate is a c-plane or m-plane along the epitaxial growth direction; The buffer layer material is Al x1 Ga 1-x1 N; where 0≤x1≤1, 0≤1-x1≤1, and the thickness is 1~5μm; The active layer of the multi-quantum well is made of Al. x3 Ga 1-x3 N / Al x4 Ga 1-x4 N; where 0≤x3≤1, 0≤1-x3≤1, 0≤x4≤1, 0≤1-x4≤1, the band gap of the quantum barrier should be higher than the band gap of the quantum well, and the number of quantum wells should be greater than or equal to 3; quantum well Al x3 Ga 1-x3 The thickness of N is 0.5–5 nm, and the quantum barrier Al x4 Ga 1-x4 The thickness of N is 3–50 nm; The material of the P-type semiconductor transport layer is Al. x6 Ga 1x6 N; where 0 ≤ x6 ≤ 1, 0 ≤ 1 x6≤1, thickness is 50–250 nm; The thickness of the SiO2 thin film is ; The P-GaN contact layer is made of P-type doped GaN and has a thickness of 2–20 nm.

6. The deep ultraviolet light-emitting diode with a light-scattering structure as described in claim 2, characterized in that, The material of the P-type ohmic electrode layer is Ni / Au, Cr / Au, Pt / Au, or Ni / Al, wherein the area of ​​the P-type ohmic electrode layer accounts for 10% to 80% of the area of ​​the N-type semiconductor transport layer; The N-type ohmic electrode layer is made of Al / Au, Cr / Au, or Ti / Al / Ti / Au, wherein the area of ​​the N-type ohmic electrode layer accounts for 10% to 50% of the area of ​​the N-type semiconductor transport layer.

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