Transparent top gate type thin film synaptic transistor and manufacturing method thereof

Abstract

The invention discloses a transparent top gate type thin film synaptic transistor and a manufacturing method thereof. The thin film synapse transistor is of a top gate bottom contact structure and sequentially comprises a substrate, an active layer, an insulating layer and a gate electrode from bottom to top, the substrate comprises substrate glass and source and drain electrodes, the active layer is a P-type and N-type organic semiconductor polymer blended thin film layer, the insulating layer is a polymethyl methacrylate thin film layer, and the gate electrode is a gate electrode. And the gate electrode is a single-walled carbon nanotube metal electrode. According to the top gate type thin film synaptic transistor device manufactured by the invention, the material of the active layer is formed by blending two organic semiconductors of P and N, and due to the formation of a P and N heterojunction, charge capture and separation are realized, and the synaptic characteristic is shown.

Description

Technical Field

[0001] The invention belongs to the technical field of organic semiconductor manufacturing, and in particular relates to a transparent top-gate thin-film synaptic transistor and a manufacturing method thereof. Background Art

[0002] In the era of data explosion, traditional von Neumann architecture computers are difficult to handle the growing amount of data information. How to improve the efficiency of storage and computing has become a difficult problem that humans have to solve. Inspired by the human brain, scientists have begun to study the construction of brain-like computer systems similar to biological brains to replace traditional computer architecture systems. In recent years, various electronic devices have been discovered to realize synaptic bionic functions, including conductive bridges, memristors or two-terminal synaptic devices with ferroelectric mechanisms. These two-terminal synaptic devices show the advantages of simple structure and high compatibility, but their synaptic learning functions are very limited. Unlike two-terminal memristors, in a three-terminal synaptic transistor comprising a channel material, a source electrode, a gate electrode and a drain electrode, information can be transmitted through the channel between the source and the drain, and the synaptic weight can be adjusted through the gate, that is, the transmission of information and synaptic learning are separated, so they can be carried out simultaneously, and have the advantages of good reversibility, low power consumption and near-linear analog switching.

[0003] In addition, compared with bottom-gate transistors, top-gate transistors have a passivation effect because their insulating layer is on top of the semiconductor layer, which can improve the air stability of the device; the contact resistance between the semiconductor layer and the source and drain electrodes is small, which can improve device performance. Therefore, synaptic transistors based on top-gate thin-film transistor structure also have certain advantages.

[0004] Compared with traditional electronic devices, devices based on transparent electronic technology can be integrated on various transparent substrates, which will greatly expand the application space of electronic devices, such as transparent IC cards, window glass with transparent solar cells, and displays showing driving assistance information on the windshield of cars. Therefore, using the solution method to obtain transparent top-gate thin-film synaptic transistors at lower temperatures will have great application potential. Summary of the invention

[0005] The purpose of the present invention is to provide a transparent top-gate thin-film synaptic transistor and a method for manufacturing the same. By mixing two semiconductor solutions and spin-coating them as the active layer of the transistor, the active layer forms a heterojunction that can capture / release charges, and only one semiconductor layer is needed to achieve the synaptic function. At the same time, due to the top-gate structure, the device has better air stability.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0007] A transparent top-gate thin-film synaptic transistor, characterized in that the thin-film synaptic transistor is a top-gate bottom contact structure, and comprises, from bottom to top, a substrate, an active layer, an insulating layer and a gate electrode, the substrate comprises a substrate glass and a source-drain electrode, the active layer is a P-type and N-type organic semiconductor polymer blended thin film layer, the insulating layer is a polymethyl methacrylate thin film layer, and the gate electrode is a single-walled carbon nanotube metal electrode.

[0008] Furthermore, the substrate is glass patterned with a layer of indium tin oxide, and the indium tin oxide glass serves as a source and drain electrode.

[0009] Furthermore, the P-type organic semiconductor polymer is indenodithiophene co-benzothiadiazole copolymer (IDT-BT) or poly-3,6-dithiophene-2-yl-2,5-di(2-decyltetradecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione-alt-thienylvinylthiophene-2,5-diyl (PDVT-10) and the like.

[0010] Furthermore, the N-type organic semiconductor polymer is [6,6]-phenyl-C61-butyric acid isomethyl ester (PCBM), poly{[N,N′-bis(2-octyldodecyl)benzo[LMN][3,8]phenanthroline-1,3,6,8(2H,7H)-tetraone-4,9-diyl)([2,2′]dithienyl-5,5′-diyl)}(N2200), etc.

[0011] Furthermore, the thickness of the active layer is 20-100 nm, and the thickness of the gate electrode is 10-80 nm.

[0012] Furthermore, the method for manufacturing a transparent top-gate thin-film synaptic transistor comprises the following steps:

[0013] S1: Using a transparent glass substrate patterned with a layer of indium tin oxide as the substrate, ultrasonically treat it in acetone, isopropanol, and chloroform for 10 to 15 minutes respectively, blow dry it with nitrogen, and then perform plasma treatment for 20 to 30 seconds;

[0014] S2: dissolving a P-type semiconductor polymer and an N-type semiconductor polymer in a chlorobenzene solvent respectively, and heating them at 60-65° C. for 2 hours, and then mixing the two in equal proportions to obtain an active layer material, and spin-coating the active layer material on the substrate treated in step S1. After the active layer material is formed into a film, the substrate is placed in a glass container with a heating table and treated for a predetermined time to obtain an active layer;

[0015] S3: dissolving polymethyl methacrylate in an organic solvent, heating and stirring at 60-65° C. for 5-6 hours to obtain an insulating layer material, and spin-coating the insulating layer material on the active layer to obtain an insulating layer;

[0016] S4: Spraying single-walled carbon nanotubes onto the insulating layer to obtain a gate electrode.

[0017] Compared with the prior art, the three-terminal synaptic transistor prepared by the present invention does not require complicated functional layers or preparation processes, and only requires a layer of semiconductor mixing to realize the simulation function of artificial synapses, and has the following advantages:

[0018] 1. By mixing P-type and N-type semiconductors in a certain proportion as the active layer of the device, the two can form a PN heterojunction to achieve charge capture and separation, thereby realizing artificial synapse simulation without the need for other additional functional layers or cumbersome and complicated preparation processes.

[0019] 2. The active layer, insulating layer and gate material of the device are all solutions, which can be formed by simple spraying and spin coating without the need for large equipment such as mask plates. The process can be carried out in the atmosphere, and the preparation process is simple, convenient and low-cost.

[0020] 3. The device has a certain degree of transparency, and it will be improved under different lighting conditions, which is in line with the current development trend of transparent electronic devices.

[0021] The method for preparing the gate electrode by spraying solution described in the present invention is simple, does not require a mask plate, has low cost, and is suitable for large-scale preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the structure of the transparent thin film synaptic transistor of the present invention: wherein 100 is a glass sheet, 110 is an indium tin oxide source and drain electrode, 120 is an active layer, 130 is an insulating layer, and 140 is a gate electrode.

[0023] Figure 2 It is a schematic diagram of the spin coating and spray coating device used in the preparation of the transparent thin film synaptic transistor of the present invention.

[0024] Figure 3 3 is the electrical transfer characteristic curve of the thin film synaptic transistor prepared in Example 1.

[0025] Figure 4 3 is the excitatory postsynaptic current (EPSC) curve of the thin film synaptic transistor prepared in Example 1.

[0026] Figure 5 3 is the inhibitory postsynaptic current (IPSC) curve of the thin film synaptic transistor prepared in Example 1.

[0027] Figure 6 is the transparency curve of the thin film synaptic transistor prepared in Example 1. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings.

[0029] like Figure 1 As shown, a transparent top-gate thin-film synaptic transistor is a top-gate bottom contact structure, which includes, from bottom to top, a substrate 100, 110, an active layer 120, an insulating layer 130 and a gate electrode 140, wherein the substrate includes a substrate glass and a source-drain electrode, the active layer is a P-type and N-type organic semiconductor polymer blended thin film layer, the insulating layer is a polymethyl methacrylate thin film layer, and the gate electrode is a single-walled carbon nanotube metal electrode.

[0030] Furthermore, the substrate is glass patterned with a layer of indium tin oxide, and the indium tin oxide glass serves as a source and drain electrode.

[0031] Furthermore, the organic semiconductor polymer includes a P-type semiconductor polymer and an N-type semiconductor polymer.

[0032] Furthermore, the P-type semiconductor polymer is IDT-BT, PDVT-10, etc.

[0033] Furthermore, the N-type semiconductor polymer is PCBM, N2200, etc.

[0034] Furthermore, the thickness of the active layer is 20-100 nm, and the thickness of the gate electrode is 10-80 nm.

[0035] Furthermore, the method for manufacturing a transparent top-gate thin-film synaptic transistor comprises the following steps:

[0036] S1: Using a transparent glass substrate patterned with a layer of indium tin oxide as the substrate, ultrasonically treat it in acetone, isopropanol, and chloroform for 10 to 15 minutes respectively, blow dry it with nitrogen, and then perform plasma treatment for 20 to 30 seconds;

[0037] S2: dissolving a P-type semiconductor polymer and an N-type semiconductor polymer in a chlorobenzene solvent respectively, and heating them at 60-65° C. for 2 hours, and then mixing the two in equal proportions to obtain an active layer material, and spin-coating the active layer material on the substrate treated in step S1. After the active layer material is formed into a film, the substrate is placed in a glass container with a heating table and treated for 10-15 minutes to obtain an active layer;

[0038] S3: dissolving polymethyl methacrylate in an organic solvent, heating and stirring at 60-65° C. for 5-6 hours to obtain an insulating layer material, and spin-coating the insulating layer material on the active layer to obtain an insulating layer;

[0039] S4: Spraying single-walled carbon nanotubes onto the insulating layer to obtain a gate electrode.

[0040] Example 1

[0041] A method for manufacturing a transparent top-gate thin-film synaptic transistor comprises the following steps:

[0042] 1) A glass sheet with a size of about 2.0 cm×2.0 cm and a 80 nm thick indium tin oxide growth was ultrasonically cleaned in acetone, isopropanol, and chloroform for 10 minutes, and then dried with nitrogen gas to serve as a substrate;

[0043] 2) Plasma treatment of the substrate, with specific setting parameters: 320V, treatment for 20 to 30 seconds;

[0044] 3) dissolving the P-type semiconductor polymer IDT-BT or PDVT-10 in a chlorobenzene solvent at a ratio of 10 mg / mL, dissolving the N-type semiconductor polymer PCBM or N2200 in a chlorobenzene solvent at a ratio of 1 mg / mL, and heating at 60° C. for 2 hours to completely dissolve, then mixing the two in equal proportions as active layer materials, and spin-coating the active layer materials on the substrate treated in step 2) at a spin coating speed of 1500 rpm / min for 60 seconds. After the active layer material is formed into a film, the substrate is placed in a glass vessel with a heating table and treated for 10 minutes to obtain an active layer with a thickness of 20 to 100 nm;

[0045] 4) dissolving the polymer polymethyl methacrylate (PMMA) in a toluene solvent at a ratio of 80 mg / mL, and heating and stirring at 60° C. for 6 hours until it is completely dissolved, using the solution as the insulating layer material, and spin-coating the insulating layer material on the active layer at a spin coating speed of 1300 rpm / min for 45 seconds to obtain an insulating layer;

[0046] 5) Spraying single-walled carbon nanotubes on the insulating layer to obtain a gate electrode with a thickness of 10-80 mm.

[0047] The electrical transfer characteristic curve, excitatory postsynaptic current curve, inhibitory postsynaptic current curve and transparency of the transparent top-gate thin-film synaptic transistor prepared in Example 1 are shown in FIG. Figure 3 , 4 , 5, and 6. It can be seen from the figure that the device successfully regulates and simulates typical synaptic behaviors such as EPSC and IPSC, and the device has good transparency, and its transparency exceeds 80% in the visible light range. These synaptic behaviors do not depend on any functional layer, but are achieved by adding PCBM to IDTBT. By simply mixing p-type semiconductors and n-type semiconductors, a transparent top-gate synaptic transistor based on a heterojunction is prepared. Therefore, the present invention provides a new form of transparent synapses and brings new development ideas for the next generation of transparent organic electronic devices.

[0048] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be regarded as equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A transparent top-gate thin-film synaptic transistor, characterized in that: The thin film synaptic transistor is a top-gate bottom contact structure, which includes a substrate, an active layer, an insulating layer and a gate electrode from bottom to top. The substrate includes substrate glass and source-drain electrodes, the active layer is a P-type and N-type organic semiconductor polymer blended thin film layer, the insulating layer is a polymethyl methacrylate thin film layer, and the gate electrode is a single-walled carbon nanotube metal electrode.

2. The transparent top-gate thin film synaptic transistor according to claim 1, characterized in that: The substrate is glass patterned with a layer of indium tin oxide, and the indium tin oxide glass serves as a source and drain electrode.

3. The transparent top-gate thin film synaptic transistor according to claim 1, characterized in that: The P-type organic semiconductor polymer is an indenodithiophene co-benzothiadiazole copolymer or poly-3,6-dithiophene-2-yl-2,5-di(2-decyltetradecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione-alt-thienylvinylthiophene-2,5-diyl.

4. The transparent top-gate thin film synaptic transistor according to claim 1, characterized in that: The N-type organic semiconductor polymers are [6,6]-phenyl-C61-butyric acid isomethyl ester and poly{[N,N′-bis(2-octyldodecyl)benzo[LMN][3,8]phenanthroline-1,3,6,8 (2H,7H)-tetraone-4,9-diyl)([2,2′]dithienyl-5,5′-diyl)}.

5. The transparent top-gate thin film synaptic transistor according to claim 1, characterized in that: The thickness of the active layer is 20-100 nm, and the thickness of the gate electrode is 10-80 nm.

6. The method for manufacturing a transparent top-gate thin-film synaptic transistor according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1: A transparent glass substrate with a patterned layer of indium tin oxide was used as the substrate, and it was ultrasonicated in acetone, isopropanol, and chloroform for 10 to 15 minutes respectively, and dried with nitrogen, and then plasma treated for 20 to 30 seconds; S2: dissolving a P-type semiconductor polymer and an N-type semiconductor polymer in an organic solvent to obtain an active layer material, and spin-coating the active layer material on the substrate treated in step S1. After the active layer material is formed into a film, the substrate is placed in a glass vessel with a heating stage and treated for a predetermined time to obtain an active layer; S3: dissolving polymethyl methacrylate in an organic solvent, heating and stirring to obtain an insulating layer material, and spin-coating the insulating layer material on the active layer to obtain an insulating layer; S4: Spraying single-walled carbon nanotubes onto the insulating layer to obtain a gate electrode.

7. The method for manufacturing a transparent top-gate thin film synaptic transistor according to claim 6, characterized in that: In step S2, the P-type semiconductor polymer and the N-type semiconductor polymer are dissolved in chlorobenzene solvent respectively, and heated at 60-65° C. for 2 hours, and then the two are mixed in equal proportions to obtain an active layer material.

8. The method for manufacturing a transparent top-gate thin film synaptic transistor according to claim 6, characterized in that: In step S3, the heating and stirring is performed at a temperature of 60-65° C. for 5-6 hours.

Images