MX / WSe2 / SiNx / Si composite material, preparation thereof and application of MX / WSe2 / SiNx / Si composite material in preparation of field effect transistor

Abstract

The invention belongs to the field of field effect crystal materials, and particularly relates to an MX / WSe2 / SiNx / Si composite material which comprises a SiNx / Si substrate and an MX / WSe2 two-dimensional vertical heterojunction compounded on the surface of the SiNx / Si substrate, WSe2 of the MX / WSe2 two-dimensional vertical heterojunction is compounded on the SiNx surface of the SiNx / Si substrate, and WSe2 of the MX / WSe2 two-dimensional vertical heterojunction is compounded on the SiNx surface of the SiNx / Si substrate. The MX is at least one of SnS2, In2Se3 and SnSe2, and the MX is at least one of SnS2, In2Se3 and SnSe2; x in the SiN < x > ranges from 1.3 to 1.4. The invention also comprises preparation of the material and application of the material in preparation of a field effect transistor. The research shows that the material can realize synergy through the combination of each layer of material and hierarchical relationship, the performance of the material can be obviously enhanced based on a brand new matching modulation mechanism, and the research also shows that the special synergy between the materials is easy to damage by adjusting the substrate and the vertical heterojunction of the material, so that the material can be applied to the field of the field effect transistor. The performance of the material is not facilitated.

Description

Technical Field

[0001] The present invention belongs to the application field of two-dimensional material heterojunction, and specifically relates to the application field of field effect transistor of two-dimensional material heterojunction. Background Art

[0002] Two-dimensional transition metal dichalcogenides (TMDs) have a dangling bond-free surface, which ensures extraordinary electronic properties within the confinement of a single atom or a few atoms of thickness. Their atomically thin size also confers superior immunity to short-channel effects, which has attracted widespread attention.

[0003] Adjusting the carrier density (n 2D ) is very important for controlling its basic electronic properties and corresponding device performance (especially the on-state current I on For example, substitutional lattice doping is often used to control carrier density and minimize contact resistance (R) in conventional semiconductors. C ). However, for atomically thin 2D TMDs, there is not enough physical space to accommodate these lattice doping. In addition, the current state-of-the-art ion implantation doping methods usually have high-energy ion implantation processes, which will severely damage the 2D TMDs, and the atomically thin lattice will also degrade their electronic properties. Among other methods, charge transfer doping methods with surface adsorbents also involve aggressive chemical treatments, which are prone to introduce surface impurities or Coulomb scattering centers, impairing charge transport. Moreover, the stability of such surface adsorbate doping is usually limited and is often incompatible with the high-resolution lithography process required to fabricate ultra-short channel transistors. Therefore, the difficulties encountered in regulating the carrier density of 2D TMDs fundamentally limit the realization of low contact resistance, which in turn affects the ultimate performance of 2D transistors. At the same time, most metal-semiconductor contacts usually exhibit a non-negligible Schottky barrier (SB), which is caused by the inevitable generation of lattice defects at the metal-semiconductor interface during high-temperature thermal evaporation, thereby forming a Fermi level pinning effect (FLP). To address this challenge, considerable efforts have been made to reduce R by using mechanical transfer-assisted metal-semiconductor van der Waals contacts, low-temperature deposited metal contacts, semi-metallic contacts, and electronically doped contact regions. C Some of these strategies have been shown to be able to significantly reduce the R C However, due to the lack of low-melting-point high-work-function metals and the difficulty in achieving deep-level P-type doping, P-type 2D TMD semiconductor contacts are generally not very successful. C The development of P-type two-dimensional TMD semiconductor field-effect transistors remains a challenge. Summary of the invention

[0004] In view of the problems existing in the prior art, the first object of the present invention is to provide a MX / WSe2 / SiN x / Si composite materials are designed to significantly optimize material performance based on the combined synergy of materials and layers.

[0005] The second object of the present invention is to provide the MX / WSe 2 / SiN x / Si composite material preparation method.

[0006] The third object of the present invention is to provide a method for utilizing the MX / WSe 2 / SiN x Application of / Si composite materials in the preparation of field effect transistors.

[0007] The fourth object of the present invention is to provide a method for utilizing the MX / WSe 2 / SiN x Field effect transistor prepared by / Si composite material.

[0008] MX / WSe 2 / SiN x / Si composite materials, including SiN x / Si substrate and composite on SiN x MX / WSe on Si substrate 2 Two-dimensional vertical heterojunction, wherein the MX / WSe 2 Two-dimensional vertical heterojunction WSe 2 Composite on SiN x SiN / Si substrate x surface;

[0009] The MX is SnS 2 、In 2 Se 3 SnSe 2 At least one of;

[0010] The SiN x Where x is 1.3 to 1.4.

[0011] The present invention provides a new material and innovatively finds that the material can unexpectedly achieve synergy based on the combination of the layer composition and the hierarchical structure relationship, and can generate a large amount of additional carrier concentration beyond the gate capacitance modulatable based on the new gate modulation band structure super doping mechanism, greatly optimizing the contact resistance R of the composite material C and the on-state current I on .

[0012] The present invention also provides a MX / WSe 2 / SiN xPreparation method of SiN / Si composite material, in advance x SiN / Si substrate x Surface deposition of WSe 2 2D material layer; then on WSe 2 MX two-dimensional material is deposited on the two-dimensional material layer to make the SiN x MX / WSe formed on Si substrate 2 Two-dimensional vertical heterojunction to obtain the MX / WSe 2 / SiN x / Si composite materials;

[0013] Alternatively, by transfer method, in SiN x / Si layer-by-layer transfer of WSe 2 layer and MX layer; or directly transfer MX / WSe 2 Composite layer (WSe 2 Layer composited on the substrate SiN x surface), to obtain the MX / WSe 2 / SiN x / Si composite materials.

[0014] The present invention innovatively adopts SiN x / Si as the substrate, and construct the special layer of MX / WSe on its surface 2 Heterojunction can significantly enhance the performance of the prepared material based on the special synergistic mechanism between the substrate and the heterojunction components and structure.

[0015] In the present invention, the SiN x SiN / Si substrate x The thickness may be 50 to 100 nm, further may be 60 to 85 nm, further may be 70 to 75 nm.

[0016] In the present invention, the WSe 2 The two-dimensional material layer can be prepared based on known methods. For example, an optional solution of the present invention is to use WSe 2 Powder source, based on PVD method, in SiN x SiN / Si substrate x Surface deposition of WSe 2 Two-dimensional material layers.

[0017] In the present invention, the deposition temperature of PVD is 1130-1200° C.; the carrier gas in the PVD process is a protective atmosphere, and the flow rate of the carrier gas is 50-150 sccm; and the deposition time of PVD is 3-10 minutes.

[0018] In the present invention, the MX layer can be formed based on known processes. For example, the MX can be formed by CVD method. An alternative step is: using X powder and M oxide powder as source materials, depositing MX two-dimensional material on the WSe 2 two-dimensional material layer by CVD method to obtain the MX / WSe 2 / SiN x / Si composite material; the X powder is at least one of sulfur powder and selenium powder. The M oxide powder is an oxide of at least one of Sn and In.

[0019] In the present invention, the weight ratio of X powder and M oxide powder can be adjusted as needed, for example, it can be 5-20:1.

[0020] Preferably, when the X powder is sulfur powder, its volatilization temperature can be 130-170 °C; when the X powder is selenium powder, its volatilization temperature can be 300-330 °C.

[0021] Preferably, when the M oxide powder is SnO 2 powder, its volatilization temperature is 570-650 °C; when the M oxide powder is In 2 O 3 its volatilization temperature is 600-640 °C.

[0022] Preferably, when the MX is SnS 2 the carrier gas in the CVD deposition stage is pure argon, and the flow rate of the carrier gas is 60-100 sccm; when the MX is In 2 Se 3 the carrier gas in the CVD deposition stage is a mixture of argon and hydrogen, where the flow rate of argon is 60-100 sccm and the flow rate of hydrogen is 3-7 sccm; when the MX is SnSe 2 the carrier gas in the CVD deposition stage is a mixture of argon and hydrogen, where the flow rate of argon is 60-100 sccm and the flow rate of hydrogen is 3-7 sccm.

[0023] Preferably, when the MX is SnS 2 the CVD deposition temperature is 590-620 °C; when the MX is In 2 Se 3 the CVD deposition temperature is 600-640 °C; when the MX is SnSe 2 the CVD deposition temperature is 590-620 °C.

[0024] Preferably, the time in the CVD deposition stage is not less than 5 min; more preferably 8-10 min.

[0025] The present invention also includes MX / WSe prepared by the preparation method 2 / SiN x / Si composite materials.

[0026] The present invention also provides the MX / WSe 2 / SiN x Application of / Si composite materials to prepare field effect transistors.

[0027] In the present invention, the MX / WSe 2 / SiN x / Si composite material is used as the substrate material, and the required field effect transistor is prepared based on conventional principles and means.

[0028] The application of the present invention, in addition to using the MX / WSe 2 / SiN x In addition to using the Si / Si composite material as the substrate, other preparation methods and the structure and principle of the manufactured transistor may be well known.

[0029] The present invention also provides a field effect transistor, which comprises the MX / WSe 2 / SiN x / Si composite materials, or through the MX / WSe 2 / SiN x / Si composite materials were prepared.

[0030] The field effect transistor of the present invention utilizes the MX / WSe 2 / SiN x / Si composite materials, other structures and structures may be well known.

[0031] In the present invention, the field effect transistor includes at least one of a Hallbar pattern field effect transistor, a TLM pattern field effect transistor, an ultra-short channel field effect transistor, and a large-area film effect transistor array.

[0032] Beneficial Effects

[0033] The present invention provides a new MX / WSe 2 / SiN x / Si composite materials, which can achieve synergy based on the combination of each layer of materials and hierarchical relationships, can significantly enhance the performance of the material.

[0034] The new material described in the present invention has a unique type III gap energy band arrangement, and with the help of this strong modulation ability, it can obviously realize an unprecedented gate modulation energy band structure super doping mechanism. For example, the MX / WSe 2 / SiN x SnS / Si composite materials 2 / WSe 2 / SiN x / Si as an example, in SnS 2 / WSe 2 / SiN x In the / Si structure, the mechanism is that as the gate voltage increases in a negative direction, WSe 2 and SnS 2 The energy band of WSe moves upward, however, 2 Closer to the gate dielectric, a large number of holes are in the WSe 2 The accumulation of SnS 2 The layer produces a charge shielding effect, making WSe 2 The energy band moves upward faster, SnS 2 The band moves up more slowly and the type III gap band arrangement becomes more obvious, allowing electrons to move from WSe 2 The valence band of SnS is directly transferred into 2 conduction band, thus further realizing WSe 2 The large amount of holes in the layer, and SnS 2 The amount of electron doping in the layer is much higher than that of SiN x The carrier concentration range that can be modulated by the substrate itself.

[0035] In addition, the present invention also conducted a comparative study on the materials and structures of the substrate of the material and the vertical heterojunction of the material, which can prove that the combination of the materials described in the present invention and their hierarchical relationships can unexpectedly achieve synergy and can significantly synergistically enhance the performance of the material based on a new modulation mechanism.

[0036] For example, the MX / WSe 2 / SiN x SnS / Si composite materials 2 / WSe 2 / SiN x Taking Si as an example, thanks to the III-type alignment of the energy band position, it is possible to achieve ultra-high carrier (n) beyond the gate dielectric limit for the first time. 2D =1.49×10 14 cm -2 ) overmodulation, thus achieving unprecedented ultra-low contact resistance (R c =0.041kΩμm) and ultra-high hole on-state current (I on=2.30mA / μm) of P-type metal-oxide-semiconductor field-effect transistor, two performances of which are superior to all existing two-dimensional semiconductor MOSFET devices and the three-dimensional Si-based device standards required by IRDS. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 To prepare SnS 2 / WSe 2 / SiN x Atmospheric pressure chemical vapor deposition device for / Si composite materials;

[0038] Figure 2 For Example 1-1, SiN x SnS grown on substrate 2 / WSe 2 / SiN x The scale of the optical microscope images of / Si composite materials is 20 μm;

[0039] Figure 3 SnS prepared in Example 1-1 2 / WSe 2 / SiN x Atomic force microscopy characterization of / Si composite materials;

[0040] Figure 4 SnS prepared in Example 1-1 2 / WSe 2 / SiN x Raman spectrum of WSe / Si composite materials, in which WSe 2 The group refers to the WSe prepared in step 1 2 / SiN x / Si, SnS 2 / WSe 2 Group refers to the SnS prepared in step 2 2 / WSe 2 / SiN x / Si;

[0041] Figure 5 SnS prepared in Example 1-1 2 / WSe 2 / SiN x Transmission electron microscopy characterization of WSe / Si composite materials. 2 The group refers to the WSe prepared in step 1 2 / SiN x / Si, SnS 2 / WSe 2 Group refers to the SnS prepared in step 2 2 / WSe 2 / SiNx / Si;

[0042] Figure 6 SnS prepared in Example 1-1 2 / WSe 2 / SiN x / Si composite materials and WSe prepared in Comparative Examples 1-2 2 / SnS 2 / SiN x UV and X-ray emission spectra of WSe / Si 2 The group refers to the WSe prepared in step 1 2 / SiN x / Si, SnS 2 / WSe 2 Group refers to the SnS prepared in step 2 2 / WSe 2 / SiN x / Si; SnS 2 Group refers to the SnS prepared in step 1 2 / SiN x / Si,WSe 2 / SnS 2 Group refers to WSe 2 / SnS 2 / SiN x / Si;

[0043] Figure 7 SnS in Example 2-1 2 / WSe 2 / SiN x Schematic diagram of the structure of the Holbar pattern field effect transistor of / Si composite material ( Figure 7 a) and electrical output characteristic curve ( Figure 7 b), where WSe 2 Group refers to WSe 2 / SiN x / Si, SnS 2 / WSe 2 Group refers to SnS 2 / WSe 2 / SiN x / Si;

[0044] Figure 8 SnS prepared in Example 2-1 2 / WSe 2 / SiN x / Si structure at different gate bias voltages (V g ) under the band alignment ( Figure 8 a), V g = Hall resistance at -40V (Rxy ) Curve of the change of magnetic field ( Figure 8 b), carrier concentration V g Dependence curve ( Figure 8 c);

[0045] Fig. 9 Preparation of WSe by non-destructive flipping of the sample in Comparative Example 2-1 2 / SnS 2 / SiN x Schematic diagram of / Si composite material;

[0046] Fig.10 For WSe in Comparative Example 2-1 2 / SnS 2 / SiN x / Si structure different gate bias voltage (V g ) under the band alignment ( Fig.10 a), V g = Hall resistance at -40V (R xy ) Curve of the change of magnetic field ( Fig.10 b), carrier concentration V g Dependence curve ( Fig.10 c);

[0047] Fig.11 The SnS with the same channel size in Comparative Example 2-2 2 / WSe 2 / SiO 2 / Si composite material (abbreviated as SiO 2 ) and SnS 2 / WSe 2 / SiN x / Si (abbreviated as SiN in the attached figure x ) Composite materials in V ds =Comparison of transfer characteristic curves under 1V;

[0048] Fig.12 SnS 2 / WSe 2 / SiO 2 / Si composite material structure and SnS 2 / WSe 2 / SiN x / Si composite structure at the same negative gate bias voltage (V g ) band alignment under;

[0049] Fig.13 SnS in Example 3-1 2 / WSe 2 and WSe 2Total resistance curves of TLM pattern field effect transistors with different channel lengths ( Fig.13 a) Using TLM and four-probe method at different V g Extracted R C curve( Fig.13 b);

[0050] Fig.14 The energy band diagram of the semiconductor and metal contact after the conventional thermal evaporation process in Example 3-1 ( Fig.14 a), SnS 2 / WSe 2 TLM patterned field effect transistors on low work function metals ( Fig.14 b) and high work function metals ( Fig.14 c) Energy band diagram under contact.

[0051] Fig.15 In in Example 3-2 2 Se 3 / WSe 2 / SiN x The band alignment (15a) and L ch =2μm when V g =Output curve at -40V.

[0052] Fig.16 SnSe in Example 3-3 2 / WSe 2 / SiN x The band alignment (15a) and L ch =2μm when V g =Output curve at -40V.

[0053] Fig.17 SnS in Example 4-1 2 / WSe 2 / SiN x Output characteristic curves of / Si composite field effect transistors under different channel lengths ( Fig.17 a,c) and transfer characteristic curve ( Fig.17 b,d).

[0054] Fig.18 SnS in Example 5-1 2 / WSe 2 / SiN x Optical morphology and electrical related test images of / Si large-area field-effect transistors. DETAILED DESCRIPTION

[0055] The present invention is further described below through implementation cases, but the content of the present invention is not limited to the following content.

[0056] The present invention provides a MX / WSe 2 / SiN x / Si composite material comprising SiN x / Si substrate and composite on SiN x MX / WSe on Si substrate 2 Two-dimensional vertical heterojunction, wherein the MX / WSe 2 Two-dimensional vertical heterojunction WSe 2 Composite on SiN x SiN / Si substrate x surface.

[0057] The research of the present invention shows that the material can achieve synergy through the combination of each layer of material and the hierarchical relationship, and can significantly enhance the performance of the material based on a new matching modulation mechanism. The research of the present invention also shows that adjusting the substrate and vertical heterojunction of the material can easily destroy the special synergy between the materials, which is not conducive to the performance of the material.

[0058] MX / WSe of the present invention 2 / SiN x / Si composite materials can be prepared by pre- x SiN / Si substrate x Surface deposition of WSe 2 2D material layer; then on WSe 2 It is prepared by depositing MX two-dimensional material on a two-dimensional material layer.

[0059] In the present invention, the deposition process can be implemented with existing equipment, and only needs to meet the temperature control method.

[0060] In the present invention, the material of the present invention can be prepared into different devices based on known methods.

[0061] PVD Deposition of WSe 2 The conditions are as follows: the PVD deposition temperature is 1130-1200°C; the carrier gas of the PVD process is a protective atmosphere, and the flow rate of the carrier gas is 50-150 sccm; and the PVD deposition time is 3-10 min.

[0062] For example, as an example, MX is SnS 2 For example, the SnS 2 / WSe 2 / SiN x The preparation process of the SiN / Si composite material is as follows: x WSe formed on Si 2layer, and then formed SnS based on the CVD method 2 layer, to obtain the SnS 2 / WSe 2 / SiN x / Si composite materials.

[0063] SnS formed by CVD 2 The steps are: SnO 2 The powder and S powder are placed in the high temperature zone and low temperature zone of the vapor deposition tube respectively, and each temperature zone is heated to make each raw material volatilize and chemically deposit on the substrate surface under the carrier gas; the grown WSe 2 The substrate of the nanosheets is covered with SnO 2 Above the powder, two temperature zones are heated to volatilize the raw materials and carry them in the WSe 2 Surface chemical deposition.

[0064] The temperature of the low temperature zone is controlled within a range of 130-170°C; the temperature of the high temperature zone is 550-650°C, and the carrier gas is pure argon atmosphere;

[0065] Preferably: SnO 2 The purity of powder and S powder raw materials is greater than 99%;

[0066] Preferably, SnO 2 The mass of powder is 0.06g; the mass of S powder is 0.1g;

[0067] In the present invention, the substrate is a substrate on which high-quality WSe is grown. 2 70nm SiN x / Si.

[0068] In the present invention, the temperature of the high temperature zone refers to SnO 2 and the temperature region where the substrate is located, which can be understood as SnO 2 Preferably, the temperature of the high temperature zone is 570-650°C, more preferably 580-620°C.

[0069] In the present invention, the temperature of the low temperature zone is the temperature of sulfur powder, which can be understood as the volatilization temperature of S. The temperature of the low temperature zone is 130-170°C.

[0070] In the present invention, the carrier gas atmosphere is 99.99% pure argon atmosphere.

[0071] In the present invention, during the chemical deposition stage, the flow rate of the carrier gas is 60-100 sccm.

[0072] In the present invention, the chemical deposition time is not less than 5 minutes, and may be preferably 8 to 10 minutes.

[0073] The present invention also provides a MX / WSe 2 / SiN x A method for characterizing the carrier concentration of a Si / Si composite material is characterized in that it is prepared as an electronic device to characterize the electrical transport properties under a magnetic field.

[0074] Preferably, a Hallbar pattern field effect transistor is prepared therefrom;

[0075] Preferably, the preparation steps of the Hall Bar pattern field effect transistor are:

[0076] In MX / WSe 2 / SiN x Spin-coat photoresist on the / Si composite material and use exposure technology to expose and develop the sample to mark it, then use exposure and development technology again to make Hall Bar electrode patterns in the contact electrode, connecting electrode and large electrode area, then use metal thermal evaporation technology to deposit metal on the sample, use solvent to dissolve and peel off the metal in the non-patterned area, and complete the production of Hall Bar pattern field effect transistor;

[0077] Preferably, the photoresist used is PMMA, more preferably 495KPMMAA8;

[0078] Preferably, the photoresist spin coating speed is 3000 rpm and the spin coating time is 60 s;

[0079] Preferably, the exposure technique uses electron beam exposure, and the electron beam current used is preferably 250pA;

[0080] Preferably, in the developing technology, a water / isopropyl alcohol mixed solution is used as a developer and isopropyl alcohol is used as a fixer, and the volume ratio of the water / isopropyl alcohol developer is further preferably 1:3;

[0081] Preferably, the developing time is 40 to 60 seconds;

[0082] Preferably, the metal deposited by electron beam evaporation is Au, and the metal thickness is preferably 50 nm;

[0083] Preferably, acetone is used as solvent;

[0084] Preferably, the characterization instrument uses a comprehensive physical property measurement system.

[0085] The present invention also provides a Hallbar pattern field effect transistor, which comprises the MX / WSe 2 / SiN x / Si composite materials.

[0086] The present invention also provides a MX / WSe 2 / SiN xA method for characterizing the electrical transport properties and contact resistance of Si / Si composite materials, characterized in that the composite materials are prepared into electronic devices to characterize the electrical output properties;

[0087] Preferably, MX / WSe 2 / SiN x / Si composite materials to prepare TLM pattern field effect transistors;

[0088] Preferably, the steps of preparing the TLM pattern field effect transistor are:

[0089] In MX / WSe 2 / SiN x Spin-coat photoresist on the / Si composite material and use exposure technology to expose and develop the sample to mark it, then use exposure and development technology again to make TLM electrode patterns in the contact electrode, connecting electrode and large electrode area, then use metal thermal evaporation technology to deposit metal on the sample, use solvent to dissolve and peel off the metal in the non-patterned area, and complete the production of TLM pattern field effect transistors;

[0090] Preferably, the photoresist used is PMMA, more preferably 495KPMMAA8;

[0091] Preferably, the photoresist spin coating speed is 3000 rpm and the spin coating time is 60 s;

[0092] Preferably, the exposure technique uses electron beam exposure, and the electron beam current used is preferably 250pA;

[0093] Preferably, in the developing technology, a water / isopropyl alcohol mixed solution is used as a developer and isopropyl alcohol is used as a fixer, and the volume ratio of the water / isopropyl alcohol developer is further preferably 1:3;

[0094] Preferably, the developing time is 40 to 60 seconds;

[0095] Preferably, the metal deposited by electron beam evaporation is Au, and the metal thickness is preferably Au (50 nm);

[0096] Preferably, acetone is used as solvent;

[0097] Preferably, the characterization instrument uses a semiconductor parameter analyzer.

[0098] The present invention also provides a TLM pattern field effect transistor, which comprises the MX / WSe 2 / SiN x / Si composite materials.

[0099] The present invention also provides a MX / WSe 2 / SiN xApplication of the / Si composite material, characterized in that it is used for the preparation of electronic devices;

[0100] Preferably, MX / WSe 2 / SiN x / Si composite material to prepare an ultra-short channel field effect transistor, and more preferably an ultra-short channel field effect transistor with a channel length in the range of 20 to 100 nm;

[0101] Preferably, the preparation steps of the ultrashort channel field effect transistor are:

[0102] In MX / WSe 2 / SiN x Spin-coat photoresist on the Si / Si composite material and use exposure technology to expose and develop the marked sample, then use exposure and development technology again to make a short channel electrode pattern in the contact electrode area, then use metal thermal evaporation technology to deposit metal in the contact electrode area on the sample, use solvent to dissolve and peel off the metal in the non-patterned area, and complete the production of the contact electrode. This method of separately making short channel contact electrodes can obtain short channel electrodes of extreme sizes with a high success rate; then spin-coat photoresist again, use exposure and development technology to make electrode patterns in the connection electrode area and the large electrode area, then use metal thermal evaporation technology to deposit metal in the connection electrode area and the large electrode area on the sample, use solvent to dissolve and peel off the metal in the non-patterned area, complete the production of the connection electrode and the large electrode, and prepare a field effect transistor;

[0103] Preferably, the photoresist used is PMMA, the photoresist used in the process of making the contact electrode is preferably 950K PMMAA3, and the photoresist used in the process of making the connecting electrode and the large electrode is preferably 495K PMMA A8;

[0104] Preferably, the photoresist spin coating speed is 3000 rpm and the spin coating time is 60 s;

[0105] Preferably, the exposure technique uses electron beam exposure, and the electron beam current in the process of making the contact electrode pattern is preferably 7pA, and the electron beam current in the process of making the connection electrode and the large electrode pattern is preferably 250pA;

[0106] Preferably, the metal deposited by electron beam evaporation is Au, the metal thickness of the contact electrode is preferably 20 nm, and the metal thickness of the connecting electrode and the large electrode is preferably 50 nm;

[0107] Preferably, acetone is used as solvent;

[0108] Preferably, the performance of the ultra-short channel field effect transistor is characterized using a semiconductor parameter analyzer.

[0109] The present invention also provides an ultrashort channel field effect transistor, which comprises the MX / WSe 2 / SiN x / Si composite materials.

[0110] In the present invention, the SiN x The Si substrate can be a commercial substrate or a substrate prepared by conventional means. As an example, in the following case, the SiN x / Si substrate refers to 70nm SiN x / Si substrate. The SiN x The x in can be 1.3 to 1.4.

[0111] 1. Material preparation and characterization

[0112] Example 1-1

[0113] Step 1: WSe 2 Deposition:

[0114] Weigh 100 mg WSe 2 The powder is placed in a quartz boat and placed in the center of the temperature zone of the tube furnace. x / Si substrate was placed in the downstream transition temperature zone. The reaction chamber was purged with 1200sccm of high-purity argon for 15 minutes to remove residual oxygen and moisture in the chamber. Then, in an 85sccm argon atmosphere, the reverse gas flow (gas flows from the substrate to the raw material) was kept constant until the central temperature zone of the tube furnace was raised to 1150°C, and then the gas flow was immediately switched to a constant temperature of 5 minutes with a forward gas flow. After cooling naturally to room temperature, the double-layer WSe was obtained. 2 Substrate (WSe 2 / SiN x / Si, also referred to as WSe in the drawings 2 ).

[0115] Step 2: SnS 2 Deposition

[0116] Preparation of SnS 2 / WSe 2 / SiN x The experimental setup of the / Si composite material is as follows Figure 1 As shown in a, the raw material mass is SnO 2 The powder is 0.06g and the S powder is 0.1g. The S powder is placed in a porcelain boat in the upstream low temperature zone of the tube furnace, and the temperature of the low temperature zone is set at 140-150℃ for volatilization; SnO 2 The powder is placed in a porcelain boat in the downstream high temperature zone of the tube furnace, and the double-layer WSe 2 Substrate (SiNx / Si) facing SnO 2 The powder is placed obliquely on the porcelain boat, and the temperature of the high temperature zone is set at 600-610℃ to carry out SnO 2 The volatilization of SnS 2 The reaction and deposition of SnS was carried out under the transport of 80sccm pure argon gas for 8 to 10 minutes. 2 Grown on double-layer WSe 2 Surface. Prepared SnS 2 / WSe 2 / SiN x / Si composite material (also referred to as SnS in the accompanying drawings) 2 / WSe 2 ).

[0117] Grown SnS 2 Full coverage of double-layer WSe 2 The upper surface of SiN x SnS prepared on Si substrate 2 / WSe 2 Optical images of 2D material heterojunctions Figure 2 As shown; since a double-layer WSe with a lateral size of 80 μm is used 2 The substrate is used to grow SnS with a lateral size of up to 80 μm. 2 / WSe 2 / SiN x / Si composite materials.

[0118] Figure 3 SnS prepared in Example 1-1 2 / WSe 2 / SiN x Atomic force microscopy characterization of the WSe / Si composite material. It can be observed that the bottom layer thickness is 1.26nm corresponding to the double-layer WSe 2 Nanosheets with a total thickness of 1.95 nm corresponding to a single layer of SnS 2 / Double-layer WSe 2 Two-dimensional heterojunction, consistent with expected parameters.

[0119] Figure 4 SnS prepared in Example 1-1 2 / WSe 2 / SiN x Raman spectrum of / Si composite material; at 247cm -1 The peak at corresponds to 2H-WSe 2 of Model; and at 308.5cm -1 The additional peak at 2 Layer A1g mold.

[0120] Figure 5 SnS prepared in Example 1-1 2 / WSe 2 / SiN x Transmission electron microscopy characterization of the Si / Si composite material. As shown in Figure a, the energy dispersive spectroscopy element mapping image shows that the atoms of W, Se, Sn and S are uniformly distributed. Figure 5 As shown in b, SnS 2 / WSe 2 / SiN x The selected area electron diffraction pattern of the WSe / Si composite material area shows two groups of diffraction points, which are consistent with the WSe 2 and SnS 2 The lattice constants match well.

[0121] Figure 6 SnS prepared in Example 1-1 2 / WSe 2 / SiN x UV and X-ray emission spectra characterization of / Si composite materials. Figure 6 In a, the red shift of the UV emission spectrum corresponds to the double-layer WSe 2 Hole doping occurs in the Figure 6 bd, X-ray emission spectroscopy shows that in the formation of SnS 2 / WSe 2 / SiN x / Si composite materials, WSe 2 The core level binding energy of WSe is red-shifted, which can be judged 2 The layer is hole doped; while SnS 2 The core-level binding energy has a blue shift, which can be judged as SnS 2 The layer is electronically doped.

[0122] Example 1-2

[0123] Compared with Example 1, the only difference is that in step 2, the following materials are used to replace the SnS 2 As MX materials, the distinguishing steps are:

[0124] Group A: Using In 2 Se 3 As MX, its preparation conditions are: the raw material mass is In 2 O 3 0.1g of powder and 0.2g of Se powder were prepared. The Se powder was placed in a porcelain boat in the upstream low-temperature zone of the tube furnace, and the temperature of the low-temperature zone was set at 300-330°C for volatilization. 2 O3 The powder is placed in a porcelain boat in the downstream high temperature zone of the tube furnace, and the double-layer WSe 2 Substrate (SiN x / Si) facing In 2 O 3 The powder is placed obliquely on the porcelain boat, and the temperature of the high temperature zone is set at 600-640℃ for In 2 O 3 Volatilization and In 2 Se 3 The reaction and deposition of SnS was carried out for 8 to 10 minutes under the transport of 80 sccm argon and 5 sccm hydrogen mixed carrier gas. 2 Grown on double-layer WSe 2 Surface. 2 Se 3 / WSe 2 / SiN x / Si composite material (also directly referred to as In in the drawings 2 Se 3 / WSe 2 )

[0125] Group B: Using SnSe 2 As MX, its preparation conditions are as follows: the raw material mass is based on SnO 2 The powder is 0.1g and the Se powder is 0.2g. The Se powder is placed in a porcelain boat in the upstream low temperature zone of the tube furnace, and the temperature of the low temperature zone is set at 300-330°C for volatilization; SnO 2 The powder is placed in a porcelain boat in the downstream high temperature zone of the tube furnace, and the double-layer WSe 2 Substrate (SiN x / Si) facing SnO 2 The powder is placed obliquely on the porcelain boat, and the temperature of the high temperature zone is set at 590-620℃ to carry out SnO 2 The volatilization of SnSe 2 The reaction and deposition of SnSe was carried out for 8 to 10 minutes under the transport of 80 sccm argon and 5 sccm hydrogen mixed carrier gas. 2 Grown on double-layer WSe 2 Surface. Prepared SnSe 2 / WSe 2 / SiN x / Si composite material (also referred to as SnSe in the figures) 2 / WSe 2 )

[0126] Other operations and parameters are the same as in Example 1.

[0127] Comparative Example 1-1

[0128] Compared with Example 1, the only difference is that in step 1, SiO 2 / Si substrate replaces the SiN x / Si substrate, other operations and parameters are the same as those in Example 1, and the prepared material is marked as SnS 2 / WSe 2 / SiO 2 / Si.

[0129] Comparative Example 1-2

[0130] Compared with Example 1, the only difference is that SiN x The SnS / Si substrate was prepared in advance using the method of Example 1. 2 / WSe 2 / SiN x / Si, and then an organic polymer-assisted mechanical transfer method was used to transfer SnS 2 / WSe 2 After the layer is flipped, it is placed back on SiN x / Si substrate and remove the polymer, the obtained material is marked as WSe 2 / SnS 2 / SiN x / Si.

[0131] 2. Preparation of Hallbar pattern field effect transistor

[0132] Example 2-1

[0133] S N 2 / WSe 2 / SiN x Preparation method of Hallbar pattern field effect transistor of 70nm SiN / Si composite material. x SnS / Si 2 / WSe 2 / SiN x / Si composite material (Example 1-1) sample, 495K PMMAA860 s was spin-coated on the sample at 3000rpm, and the sample was exposed and developed using an electron beam exposure with a beam current of 250pA; then the contact electrode area, connecting electrode, and large electrode area of ​​the Hall Bar pattern were exposed again with an electron beam with a beam current of 250pA. After development, 50nm Au was deposited on the sample using metal thermal evaporation technology, and acetone was used to dissolve and peel off to complete the production of the Hall Bar pattern field effect transistor.

[0134] Figure 7 a is a structural diagram of a Hallbar pattern field effect transistor; Figure 7 b is SnS 2 / WSe2 and WSe 2 Comparison of the output characteristic curves of the Hall effect transistor. SnS 2 / WSe 2 The linear output property indicates the ohmic contact between metal and semiconductor, which is the basis for Hall test and also proves that SnS 2 / WSe 2 / SiN x The construction of Si / Si composite materials is beneficial to the improvement of contact properties.

[0135] Figure 8 a is SnS 2 / WSe 2 / SiN x / Si structure different gate bias voltage (V g ) band alignment under; Figure 8 b is SnS 2 / WSe 2 / SiN x / Si Hall Field Effect Transistor at V g = Hall resistance at -40V (R xy ) curve with magnetic field, the hole carrier concentration can be calculated based on the slope, which is as high as 1.47×10 14 cm -2 . Figure 8 c is SnS 2 / WSe 2 / SiN x V / Si Hall Field Effect Transistor Carrier Concentration g Dependence curve, the apparent capacitance C is calculated based on the slope Hall =5.20×10 -7 F -1 , about 70nm SiN x 5 times the gate dielectric capacitance (C g =1.06×10 -7 F cm -1 ). This indicates that in addition to electrostatic capacitance gating, there is also SnS 2 / WSe 2 / SiN x The gate modulation band shift of the / Si structure and the top SnS 2 The dielectric shielding effect of the SiN layer improves x / Si dielectric to WSe 2 The gate modulation capability induces a super-doping effect beyond the gate capacitance.

[0136] Comparative Example 2-1

[0137] Compared with Example 2-1, the only difference is that SnS 2 / WSe 2 / SiN x / Si structure is losslessly flipped to WSe 2 / SnS 2 / SiN x / Si structure and fabrication of Hallbar pattern electrodes.

[0138] Fig. 9 SnS 2 / WSe 2 / SiN x Non-destructive flipping process of / Si composite materials on substrates to characterize and extract WSe after flipping 2 / SnS 2 / SiN x / Si structure carrier concentration. The specific flipping process is: at a speed of 3000rpm in SnS 2 / WSe 2 / SiN x Spin polypropylene carbonate (PPC) on the SnS / Si structure for 1 min and then bake on a hot plate at 80°C for 2 min. Then use a transparent tape with a small circular hole to cover the PPC film with SnS 2 / WSe 2 With SiN x / Si is easily separated, and then the circular part is released onto a square polydimethylsiloxane (PDMS) substrate and the excess part outside the PDMS is cut off, finally forming PPC / SnS 2 / WSe 2 Then, the PPC / sample / PDMS structure was flipped 180° and pressed onto the SiN x / Si substrate, heated and released at 80℃ to form a flipped WSe 2 / SnS 2 / PPC / SiN x / Si structure. Finally, the sample was annealed at 250°C on a hot plate in a nitrogen atmosphere in a glove box for 30 minutes to completely decompose the PPC layer and obtain WSe 2 / SnS 2 / SiN x / Si structure.

[0139] Fig.10 a is WSe 2 / SnS 2 / SiN x / Si structure different gate bias voltage (V g ) band alignment under; Fig.10 b is WSe 2 / SnS 2 / SiN x / Si Hall Field Effect Transistor at V g = Hall resistance at -40V (R xy ) curve with magnetic field, the hole carrier concentration can be calculated based on the slope, which is as high as 1.67×10 13 cm -2 . Fig.10 c is WSe 2 / SnS 2 / SiN x V / Si Hall Field Effect Transistor Carrier Concentration g Dependence curve, the apparent capacitance C is calculated based on the slope Hall =2.71×10 -8 F cm -1 , about 70nm SiN x 1 / 4 of the gate dielectric capacitance (C g =1.06×10 -7 F cm -1 ). This indicates that in addition to electrostatic capacitance gating, there is also WSe 2 / SnS 2 / SiN x The gate modulation band offset of the / Si structure and the bottom SnS 2 The dielectric shielding effect of the layer suppresses the SiN x / Si dielectric to WSe 2 This further proves the modulation mechanism.

[0140] Comparative Example 2-2

[0141] Compared with Example 2-1, the only difference is that 280nm SiO 2 Form SnS as gate dielectric 2 / WSe 2 / SiO 2 / Si composite material structure and fabrication of Holba pattern electrodes.

[0142] Fig.11 For SnS with the same channel size 2 / WSe 2 / SiO 2 / Si composite materials and SnS 2 / WSe 2 / SiN x / Si composite materials in V ds =1V transfer characteristic curve comparison. Since the SiO2 thickness is larger, SnS 2 / WSe 2 / SiO 2V / Si composites g Applied up to ±60V; while SiN x Small thickness, SnS 2 / WSe 2 / SiN x V / Si composites g Applied up to ±40V. It is clearly observed that compared with SnS 2 / WSe 2 / SiN x / Si composite materials, SnS 2 / WSe 2 / SiO 2 The on-state current of the SnS / Si composite material is one order of magnitude smaller, the off-state current is five orders of magnitude larger, and the current switching ratio is six orders of magnitude smaller. 2 / WSe 2 / SiO 2 The performance of the / Si composite material is far inferior to that of SnS 2 / WSe 2 / SiN x / Si composite materials.

[0143] Fig.12 SnS 2 / WSe 2 / SiO 2 / Si composite material structure and SnS 2 / WSe 2 / SiN x / Si composite material structure at the same negative V g The bands are aligned under 280nm SiO 2 The weak gate modulation capability makes SnS 2 / WSe 2 The band shift of the heterojunction is very small and the resulting super-doping effect is very weak, so the carrier concentration of the heterojunction is modulated over a large range, resulting in a small on-state current, a large off-state current, and a very low current switching ratio.

[0144] 3. Preparation of TLM pattern field effect transistor

[0145] Example 3-1

[0146] S N 2 / WSe 2 / SiN x Preparation method of TLM pattern field effect transistor of / Si composite material. x SnS / Si 2 / WSe 2 / SiN x / Si composite material (Example 1-1) sample, 495K PMMAA860 s was spin-coated on the sample at 3000rpm, and the sample was exposed and developed using an electron beam exposure with a beam current of 250pA; then the contact electrode area, connecting electrode, and large electrode area of ​​the TLM pattern were exposed again with an electron beam with a beam current of 250pA. After development, 50nm Au was deposited on the sample using metal thermal evaporation technology, and acetone was used to dissolve and peel off to complete the production of the TLM pattern field effect transistor. The prepared SnS 2 / WSe 2 / SiN x Scanning electron microscope (SEM) images of TLM patterned field effect transistors of / Si composite materials are shown in Fig.11 aInset, scale bar is 8 μm.

[0147] Fig.13 a is SnS 2 / WSe 2 / SiN x / Si and WSe 2 / SiN x Total resistance curves of SiTLM patterned field effect transistors with different channel lengths. The contact electrodes used are all Au with a work function of 5.3 eV. The V g All are -40V; the contact resistance (R C ) is 0.045kΩμm. Fig.13 b is SnS 2 / WSe 2 TLM pattern FET at V g = R extracted at -30, -35, -40V C , its R C It can be modulated from 0.063kΩμm to 0.045kΩμm, which is consistent with the SnS 2 / WSe 2 R extracted by four-probe method for Hall-Bar pattern field effect transistor C The values ​​of the contact resistance of the electrodes are close to each other (from 0.049 kΩμm to 0.041 kΩμm), which mutually confirm the reliable realization of ultra-low contact resistance.

[0148] Fig.14 For metal-semiconductor Schottky contacts with thermal evaporation technology ( Fig.14 a) In contrast, SnS 2 / WSe 2 / SiN x / Si FETs in low ( Fig.14b) Energy band diagram of high (14c) work function metal contact, intended to compare the Schottky barrier heights of metals with different work functions. Typical semiconductor devices are prone to severe Fermi pinning and high Schottky barriers due to defect-induced gap states generated during thermal evaporation; and are dominated by thermal ion emission at low carrier density, usually showing significant dependence on the metal work function, while SnS 2 / WSe 2 / SiN x / Si field effect transistors are mainly based on tunneling injection at high carrier density, so low Schottky barrier height and ultra-low R can be achieved under the contact of metals with different work functions. C .

[0149] Example 3-2

[0150] Compared with Example 3-1, the only difference is that MX / WSe 2 / SiN x In / Si structure 2 Se 3 As MX, get In 2 Se 3 / WSe 2 / SiN x / Si composite material. Its energy band alignment is as follows Fig.15 As shown in a, it exhibits a quasi-III-type II energy band arrangement. g =The output curve at -40V is as follows Fig.15 As shown in b, in L ch =2μm, the current is also greater than 1.0mA / μm, with quite good electrical properties, proving that this quasi-type III energy band arrangement composite material can also produce similar super-doping effects.

[0151] Example 3-3

[0152] Compared with Example 3-1, the only difference is that MX / WSe 2 / SiN x SnSe is used in / Si structure 2 As MX, SnSe 2 / WSe 2 / SiN x / Si composite material. Its energy band alignment is as follows Fig.16 As shown in a, it shows a type III energy band arrangement. g =The output curve at -40V is as follows Fig.16 As shown in b, in L ch =2μm, the current is also greater than 1.0mA / μm, with very good electrical properties, proving that this type III energy band arrangement composite material can produce a super-doping effect.

[0153] 4. Preparation of ultra-short channel field effect transistors

[0154] Example 4-1

[0155] Preparation of SnS 2 / WSe 2 / SiN x / Si composite material ultra-short channel field effect transistors are used to characterize and verify the electronic performance of ultra-small transistors obtained by cutting-edge technology, and to explore the possibility of future application in advanced chips. x SnS / Si 2 / WSe 2 / SiN x The SnS / Si composite material (Example 1-1) was spin-coated with 950K PMMAA at 3000 rpm for 360 s, and the sample was exposed and developed using an electron beam with a beam current of 250 pA; then, the SnS / Si composite material (Example 1-1) was spin-coated with 950K PMMAA at 3000 rpm for 360 s, and the sample was exposed and developed using an electron beam with a beam current of 250 pA; 2 / WSe 2 / SiN x The ultra-short channel contact electrode pattern was exposed and developed on the / Si composite material, 20nmAu was deposited on the sample, and acetone was used to dissolve and peel off the metal in the non-patterned area to complete the production of the ultra-short channel contact electrode; then 495KPMMAA8 was spin-coated again, and the electrode pattern was made by exposing and developing the connecting electrode area and the large electrode area with an electron beam with a beam current of 250pA, 50nmAu was deposited on the sample, and acetone was used to dissolve and peel off the metal in the non-patterned area to complete the production of the connecting electrode and the large electrode, and the SnS 2 / WSe 2 / SiN x / Si composite ultra-short channel field effect transistor, typical SEM images are as follows Fig.16 As shown in illustrations of b and c.

[0156] Fig.17 a, b are 85nm channel length SnS 2 / WSe 2 / SiN x Output characteristic curve of / Si composite field effect transistor ( Fig.17 a) and transfer characteristic curve ( Fig.17 b). Fig.17 c, d are 20nm channel length SnS 2 / WSe 2 / SiN x Output characteristic curve of / Si composite field effect transistor ( Fig.17 c) and transfer characteristic curve ( Fig.17 d). It can be seen that SnS2 / WSe 2 / SiN x The ultra-short channel field effect transistor of the / Si composite material can be operated at a bias voltage of 0.88V (V ds ) exhibits a hole current density of up to 2.30mA / μm, which exceeds all MOSFETs and is superior to all existing two-dimensional semiconductor MOSFET devices and the three-dimensional Si device standards required by IRDS.

[0157] 5. Preparation of large-area film field-effect transistor arrays

[0158] S N 2 / WSe 2 / SiN x Preparation method of large-area film field effect transistor array of Si / Si composite material. x / Si was replaced with sapphire substrate to obtain 1.5×1.5cm 2 S N 2 / WSe 2 Continuous film, subsequently transferred to SiN x SnS / Si 2 / WSe 2 / SiN x / Si composite material large area film. The device preparation method of Example 2-1 is used to prepare SnS 2 / WSe 2 / SiN x / Si composite material large area film field effect transistor device array, its optical picture is as follows Fig.18 As shown in ac, Fig.18 b scale is 1mm, Fig.18 c scale bar is 100 μm. Each SnS 2 / WSe 2 / SiN x The output curve of the / Si composite field effect tube shows excellent ohmic behavior ( Fig.18 d), the transfer characteristic curve shows a high maximum current and 10 10 High current switching ratio ( Fig.18 e) 130 L ch = 0.8 μm FET array statistical maximum current density (I on ) data show that the average I on Greater than 1.0mA / μm( Fig.18 f). This provides a promising opportunity for the future preparation of wafer-scale, high-quality, and scalable SnS 2 / WSe 2 / SiN x / Si composites provide a reliable way to form large-area films for SnS 2 / WSe 2 / SiN x This lays a solid foundation for the future integration and industrial application of / Si composite materials devices.

Claims

1. MX / WSe2 / SiN x / Si composite material, characterized in that Including SiN x / Si substrate and composite on SiN x / Si substrate surface MX / WSe2 two-dimensional vertical heterojunction, wherein the WSe2 of the MX / WSe2 two-dimensional vertical heterojunction is composited on the SiN x SiN / Si substrate x surface; The MX is at least one of SnS2, In2Se3, and SnSe2; The SiN x Where x is 1.3 to 1.

4.

2. A MX / WSe2 / SiN as claimed in claim 1 x A method for preparing a / Si composite material, characterized in that: Pre-SiN x SiN / Si substrate x Depositing a WSe2 two-dimensional material layer on the surface; Then, MX 2D material is deposited on the WSe2 2D material layer to make the SiN x / Si substrate to form a MX / WSe2 two-dimensional vertical heterojunction to obtain the MX / WSe2 / SiN x / Si composite materials; Alternatively, by transfer method, in SiN x / Si layer by layer transfer WSe2 layer and MX layer; or directly transfer MX / WSe2 composite layer to obtain the MX / WSe2 / SiN x / Si composite materials.

3. MX / WSe2 / SiN as claimed in claim 2 x A method for preparing a / Si composite material, characterized in that: The SiN x SiN / Si substrate x The thickness is 50 to 100 nm.

4. MX / WSe2 / SiN as claimed in claim 2 x A method for preparing a / Si composite material, characterized in that: Using WSe2 powder as the source, based on the PVD method, on SiN x SiN / Si substrate x A WSe2 two-dimensional material layer is deposited on the surface.

5. MX / WSe2 / SiN as claimed in claim 4 x A method for preparing a / Si composite material, characterized in that: The deposition temperature of PVD is 1130-1200°C; the carrier gas of the PVD process is a protective atmosphere, and the flow rate of the carrier gas is 60-120 sccm; the time of PVD deposition is 3-10 minutes.

6. MX / WSe2 / SiN as claimed in claim 2 x A method for preparing a / Si composite material, characterized in that: Using X powder and M oxide powder as source materials, a MX two-dimensional material is deposited on the WSe2 two-dimensional material layer based on a CVD method to obtain the MX / WSe2 / SiN x / Si composite material; the X powder is at least one of sulfur powder or selenium powder; the M oxide powder is at least one of Sn and In oxide.

7. MX / WSe2 / SiN as claimed in claim 6 x A method for preparing a / Si composite material, characterized in that: The weight ratio of X powder to M oxide powder is 2 to 20:1; preferably, the X powder is S powder, and the weight ratio of X powder to M oxide powder is 10 to 20:1; the X powder is Se powder, and the weight ratio of X powder to M oxide powder is 2 to 4:1; Preferably, when the X powder is sulfur powder, its volatilization temperature may be 130-170° C.; when the X powder is selenium powder, its volatilization temperature may be 300-330° C.; Preferably, when the M oxide powder is SnO2 powder, its volatilization temperature is 590-620°C; when the M oxide powder is indium oxide, its volatilization temperature is 600-640°C; Preferably, when the MX is SnS2, the carrier gas in the CVD deposition stage is pure argon, wherein the flow rate of the carrier gas is 60-100 sccm; when the MX is In2Se3, the carrier gas in the CVD deposition stage is a mixture of argon and hydrogen, wherein the flow rate of argon is 60-100 sccm, and the flow rate of hydrogen is 3-7 sccm; when the MX is SnSe2, the carrier gas in the CVD deposition stage is a mixture of argon and hydrogen, wherein the flow rate of argon is 60-100 sccm, and the flow rate of hydrogen is 3-7 sccm; When the MX is SnS2, the CVD deposition temperature is 590-620°C; when the MX is In2Se3, the CVD deposition temperature is 600-640°C; when the MX is SnSe2, the CVD deposition temperature is 590-620°C Preferably, the duration of the CVD deposition stage is not less than 5 minutes; more preferably, it is 8 to 10 minutes.

8. A MX / WSe2 / SiN as claimed in claim 1 x / Si composite material or MX / WSe2 / SiN prepared by the preparation method according to any one of claims 2 to 7 x Application of / Si composite materials, characterized in that, A field effect transistor was prepared.

9. A field effect transistor, characterized in that: Containing the MX / WSe2 / SiN according to claim 1 x / Si composite material or MX / WSe2 / SiN prepared by the preparation method according to any one of claims 2 to 7 x / Si composite materials, or through the MX / WSe2 / SiN x / Si composite materials were prepared.

10. The field effect transistor according to claim 9, characterized in that The field effect transistor includes at least one of a Hallbar pattern field effect transistor, a TLM pattern field effect transistor, an ultra-short channel field effect transistor, and a large-area film effect transistor array.

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