Display panel and display device

Abstract

The invention relates to a display panel and a display device, the display panel comprises a display area, a winding area and a hole area, and the display area is arranged around at least part of the winding area; the display panel further comprises a plurality of first scanning signal lines used for providing first scanning signals for the pixel circuits; the plurality of data signal lines are used for providing data signals for the pixel circuits; in the winding area, the data signal line and the first scanning signal line are arranged around the hole area; wherein the overlapping area of the orthographic projection of the target scanning signal line on the target plane and the orthographic projection of the target data signal line on the target plane is smaller than a preset threshold value; the target scanning signal line is the first scanning signal line closest to the hole region in the multiple first scanning signal lines, and the target data signal line is the data signal line closest to the hole region in the multiple data signal lines. The display panel provided by the invention has relatively good display performance.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As an important part of the information industry, display technology has played an important role in the development of information technology. With the development of display technology, organic light emitting diode display panels and other types of display panels have been widely used.

[0003] However, the display performance of the display panel in the related art is insufficient. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a display device, aiming to improve the display performance of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, the display panel comprising a display area, a winding area and a hole area, the display area is arranged around at least a portion of the winding area; the display panel further comprises:

[0006] A plurality of first scanning signal lines, used for providing a first scanning signal to the pixel circuit;

[0007] A plurality of data signal lines, used for providing data signals to the pixel circuit;

[0008] In the winding area, the data signal line and the first scanning signal line are arranged around the hole area;

[0009] Among them, the overlapping area of ​​the orthographic projection of the target scan signal line on the target plane and the orthographic projection of the target data signal line on the target plane is less than a preset threshold; the target scan signal line is the first scan signal line closest to the hole area among multiple first scan signal lines, and the target data signal line is the data signal line closest to the hole area among multiple data signal lines.

[0010] In a second aspect, an embodiment of the present application further provides a display device, which includes the display panel provided in the first aspect.

[0011] The display panel and the display device provided by the embodiments of the present application include a display area, a winding area and a hole area, wherein the display area is arranged around at least a part of the winding area; the display panel also includes: a plurality of first scanning signal lines and a plurality of data signal lines, wherein the first scanning signal lines are used to provide a first scanning signal for a pixel circuit, and the data signal lines are used to provide a data signal for the pixel circuit; in the winding area, the data signal lines and the first scanning signal lines are arranged around the hole area; in the present application, by controlling the orthographic projection of the first scanning signal line closest to the hole area among the plurality of first scanning signal lines on the target plane, the overlapping area with the orthographic projection of the data signal line closest to the hole area among the plurality of data signal lines on the target plane is smaller than a preset threshold value, so that the overlapping area of ​​the first scanning signal line closest to the hole area and the data signal line closest to the hole area relative to the first scanning signal line and the data signal line at other positions in the winding area can be reduced, thereby reducing the influence of the delay of the first scanning signal transmitted by the first scanning signal line closest to the hole area on the pixel circuit, thereby improving the display uniformity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the planar structure of the area surrounding the hole area of ​​the display panel in the related art;

[0013] Figure 2 A schematic diagram of a circuit structure of a pixel circuit provided in an embodiment of the present application;

[0014] Figure 3 A schematic diagram of a planar structure of an area surrounding a hole area of ​​a display panel provided in an embodiment of the present application;

[0015] Figure 4 A schematic diagram of a planar structure of an area surrounding a hole area of ​​another display panel provided in an embodiment of the present application;

[0016] Figure 5 A schematic diagram of a planar structure of an area surrounding a hole area of ​​another display panel provided in an embodiment of the present application;

[0017] Figure 6 A schematic cross-sectional view of a display panel provided in an embodiment of the present application;

[0018] Figure 7 A schematic diagram of a layout structure of a display panel provided in an embodiment of the present application;

[0019] Figure 8 A schematic diagram of a circuit structure of a pixel circuit provided in an embodiment of the present application;

[0020] Fig. 9 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0021] Description of reference numerals:

[0022] 11-first scanning signal line, 11`-target scanning signal line, 111-first A scanning signal line, 112-first scanning signal winding part, 113-first B scanning signal line, 12-data signal line, 12`-target data signal line, 121-A data signal line, 122-data signal winding part, 123-B data signal line, 13-gate part of driving transistor, 14-light emitting control signal line, 15-second scanning signal line, 16-third scanning signal line, 21-substrate, 22-first metal layer, 23-target active layer, 24-second metal layer, 25-third metal layer, 26-fourth metal layer, 27-fifth metal layer. DETAILED DESCRIPTION

[0023] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0025] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly under or there may be one or more intervening elements. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there may be one or more intervening elements.

[0026] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be construed as being one in number.

[0027] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0028] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.

[0029] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0030] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0031] As described in the background technology section, the display panel in the related art has insufficient display performance: the brightness of the light-emitting element corresponding to the first scanning signal line in the middle of the hole area of ​​the display panel is higher than the brightness of the light-emitting elements corresponding to the first scanning signal lines on both sides of the hole area of ​​the display panel. Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a planar structure of the area surrounding the hole area H of a display panel in the related art, Figure 2 is a schematic diagram of a pixel circuit structure in the related art, Figure 1 Only part of the first scan signal lines (SC_P1, SC_P2 and SC_P3) and part of the data signal lines (Data1 and Data2) are shown. Figure 1It can be seen that the first scan signal line used to control the data writing process of the pixel circuit in the winding area R in the related art overlaps with the data signal line that provides the data signal to the pixel circuit, and the overlapping area of ​​the first scan signal line SC_P1 closest to the hole area and the data signal line Data1 closest to the hole area is larger than the overlapping area of ​​the first scan signal line and the data signal line at other positions, such as the overlapping area of ​​the first scan signal line SC_P3 and the data signal line Data2. The inventor has found through research that the different overlapping areas of the first scan signal line and the data signal line will lead to different delays of the first scan signal. Since there is a parasitic capacitor C1 between the gate of the data writing transistor M1 and the gate of the driving transistor M0 in the pixel circuit, the jump of the first scan signal will couple the potential of the gate of the driving transistor M0. The delays of each first scan signal are different, which will lead to different coupling amounts of the gate potential of the driving transistor M0 in each row of pixel circuits. Moreover, the larger the overlapping area of ​​the first scanning signal line and the data signal line, the greater the delay of the first scanning signal, which will lead to a lower coupling amount of the gate potential of the driving transistor M0 in each row of pixel circuits, and the lower the gate potential of the driving transistor M0, the higher the brightness of the light-emitting element. Therefore, in the related art, the gate potential of the driving transistor of the pixel circuit corresponding to the first scanning signal line closest to the hole area is lower than the gate potential of the driving transistor of the pixel circuit corresponding to the first scanning signal line at other positions, and there is a phenomenon of uneven brightness around the hole area.

[0032] Based on the above technical problems, the inventors have found that the phenomenon of uneven brightness around the hole area can be improved by reducing the overlapping area of ​​the first scanning signal line closest to the hole area and the data signal line closest to the hole area. Based on this, the inventors have further studied the technical solution of the embodiment of the present application. Specifically, the display panel provided in the embodiment of the present application includes a display area, a winding area and a hole area, and the display area is arranged around at least part of the winding area; the display panel also includes: a plurality of first scanning signal lines, which are used to provide a first scanning signal for the pixel circuit; a plurality of data signal lines, which are used to provide a data signal for the pixel circuit; in the winding area, the data signal line and the first scanning signal line are arranged around the hole area; wherein the overlapping area of ​​the orthographic projection of the target scanning signal line on the target plane and the orthographic projection of the target data signal line on the target plane is less than a preset threshold; the target scanning signal line is the first scanning signal line closest to the hole area among the plurality of first scanning signal lines, and the target data signal line is the data signal line closest to the hole area among the plurality of data signal lines. By adopting the above technical solution, by making the overlapping area of ​​the orthographic projection of the target scanning signal line on the target plane and the orthographic projection of the target data signal line on the target plane smaller than a preset threshold, the coupling amount of the gate potential of the driving transistor in the pixel circuit corresponding to the target scanning signal line is increased, the gate potential of the driving transistor in the pixel circuit corresponding to the target scanning signal line is increased, the brightness of the light-emitting element corresponding to the target scanning signal line is reduced, and the brightness uniformity around the hole area of ​​the display panel is improved.

[0033] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be described clearly and completely below in conjunction with the drawings in the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] In an exemplary embodiment, the present application provides a display panel, see Figure 3 , Figure 3 This is a schematic diagram of the planar structure of the area around the hole area of ​​the display panel in an example of the present application. The display panel includes a display area AA, a winding area S1 and a hole area S2. The display area AA is arranged around at least a portion of the winding area S2, and the winding area S1 is arranged around at least a portion of the hole area S2; the display panel also includes a plurality of first scanning signal lines 11 for providing a first scanning signal to the pixel circuit and a plurality of data signal lines 12 for providing a data signal to the pixel circuit.

[0035] See also Figure 3 , it can be seen that in the display area AA, the first scan signal line 11 is extended along the first direction, and the data signal line 12 is extended along the second direction, the first direction is the X-axis direction shown in the figure, and the second direction is the Y-axis direction shown in the figure, and the first direction and the second direction intersect. In the winding area S1, the data signal line 12 and the first scan signal line 11 are arranged around the hole area. The target scan signal line 11' is the first scan signal line 11 closest to the hole area S2 among the multiple first scan signal lines 11, and the target data signal line 12' is the data signal line 12 closest to the hole area S2 among the multiple data signal lines 12. The overlapping area of ​​the orthographic projection of the target scan signal line 11' on the target plane and the orthographic projection of the target data signal line 12' on the target plane is less than the preset threshold.

[0036] by Figure 3 Take this as an example to illustrate. Figure 3 In the embodiment, the target scanning signal line 11' is the first scanning signal line 11 closest to the hole area S2 among the multiple first scanning signal lines 11, the target data signal line 12'-1 and the target data signal line 12'-2 are the data signal lines 12 closest to the hole area S2 among the multiple data signal lines 12, and the target data signal line 12'-1 and the target data signal line 12'-2 are symmetrically arranged along the axis of the hole area S2 in the second direction. It can be seen that the overlapping area of ​​the target scanning signal line 11' and the target data signal line 12' in the present application is much smaller than Figure 1The overlapping area of ​​the first scanning signal line SC_P1 closest to the hole area and the data signal line Data1 closest to the hole area in the related technology. And the overlapping area of ​​the first scanning signal line SC_P1 closest to the hole area and the data signal line Data1 closest to the hole area in the related technology is larger than the overlapping area of ​​the remaining first scanning signal lines and data signal lines, while in the present application, the overlapping area of ​​the target scanning signal line 11' and the target data signal line 12' can be smaller than the overlapping area of ​​the remaining first scanning signal lines and data signal lines, thereby increasing the coupling amount of the gate potential of the driving transistor in the pixel circuit corresponding to the target scanning signal line, raising the gate potential of the driving transistor in the pixel circuit corresponding to the target scanning signal line, and reducing the brightness of the light-emitting element corresponding to the target scanning signal line, thereby making the brightness of the light-emitting element corresponding to the first scanning signal line in the middle of the hole area of ​​the display panel approximately consistent with the brightness of the light-emitting element corresponding to the first scanning signal line on both sides of the hole area of ​​the display panel, alleviating the problem of uneven brightness around the hole area of ​​the display panel.

[0037] It should be understood that this application Figure 3 The schematic diagram of the planar structure of the area around the hole area is only an example. In applications, the number of the target scanning signal lines 11' can also be two, and the two target scanning signal lines are symmetrically arranged along the axis of the hole area S2 in the first direction.

[0038] The display panel provided by the embodiment of the present application includes a display area, a winding area and a hole area, and the display area is arranged around at least a part of the winding area; the display panel also includes: a plurality of first scanning signal lines and a plurality of data signal lines, the first scanning signal lines are used to provide a first scanning signal for a pixel circuit, and the data signal lines are used to provide a data signal for the pixel circuit; in the winding area, the data signal lines and the first scanning signal lines are arranged around the hole area; in the present application, by controlling the orthographic projection of the first scanning signal line closest to the hole area among the plurality of first scanning signal lines on the target plane, the overlapping area with the orthographic projection of the data signal line closest to the hole area among the plurality of data signal lines on the target plane is less than a preset threshold, so that the overlapping area of ​​the first scanning signal line closest to the hole area and the data signal line closest to the hole area relative to the first scanning signal line and the data signal line at other positions in the winding area can be reduced, thereby reducing the influence of the delay of the first scanning signal transmitted by the first scanning signal line closest to the hole area on the pixel circuit, and improving the display uniformity of the display panel.

[0039] In an exemplary embodiment, see Figure 4 The winding area S1 is divided into a first sub-area S11 and a second sub-area S12 by the target data signal line 12'. The first scanning signal line 11 is arranged around the hole area in the first sub-area and the second sub-area, and the data signal line 12 is arranged around the hole area in the second sub-area S12.

[0040] For ease of reference, Figure 4 Only the target data signal line 12'-1 and the target data signal line 12'-2 are shown to indicate that the winding area S1 is divided into the first sub-area S11 and the second sub-area S12 by the target data signal line 12', and the first scanning signal line 11 and the remaining data signal lines 12 are not shown. However, relevant technicians should understand that the winding area also has multiple first scanning signal lines 11 and multiple data signal lines 12 arranged in the manner described in the above embodiment.

[0041] In this embodiment, the winding area S1 is divided into a first sub-area S11 and a second sub-area S12 by the target data signal line 12`, and the first scanning signal line 11 is arranged around the hole area S2 in the first sub-area S11 and the second sub-area S12, and the data signal line 12 is only arranged around the hole area in the second sub-area S12, so that there is no overlap between the first scanning signal line 11 and the data signal line 12 in the first sub-area S11, and thus the overlapping area between the first scanning signal line 11 and the data signal line 12 relatively close to the hole area Q2 can be made smaller than the overlapping area between the first scanning signal line 11 and the data signal line 12 relatively far from the hole area Q2. Since the size of the overlapping area between the first scanning signal line 11 and the data signal line 12 will affect the size of the gate potential of the driving transistor in the pixel circuit corresponding to the first scanning signal line 11, and thus affect the brightness of the light-emitting element, the present application controls the data signal line 12 to be wound only in the second sub-area S12. Compared with the related art, the overlapping area between the first scanning signal line 11 and the data signal line 12 relatively close to the hole area Q2 can be reduced, thereby increasing the gate potential of the driving transistor in the pixel circuit corresponding to each row, reducing the brightness of the light-emitting elements corresponding to each row, reducing the difference in brightness between the light-emitting elements corresponding to the first scanning signal line in the middle of the hole area of ​​the display panel and the light-emitting elements corresponding to the first scanning signal line on both sides of the hole area of ​​the display panel, and improving the brightness uniformity of the display panel.

[0042] In an exemplary embodiment, see Figure 5 , at least part of the first scan signal line 11 includes a first A scan signal line 111, a first scan signal winding portion 112 and a first B scan signal line 113 connected in sequence; wherein the first A scan signal line 111 and the first B scan signal line 113 are located in the display area AA and extend along the first direction, and the first scan signal winding portion 112 is located in the winding area S1. At least part of the data signal line 12 includes a A data signal line 121, a data signal winding portion 122 and a B data signal line 123 connected in sequence, wherein the A data signal line 121 and the B data signal line 123 are located in the display area AA and extend along the second direction, and the data signal winding portion 122 is located in the winding area S1.

[0043] from Figure 5It can be seen that the first A scanning signal line 111 and the first B scanning signal line 113 are at least partially located in the display area AA and extend along the first direction, the first scanning signal winding portion 112 is arranged around the hole area S2 in the winding area S1, the A data signal line 121 and the B data signal line 123 are at least partially located in the display area AA and extend along the second direction, and the data signal winding portion 122 is arranged around the hole area S2 in the winding area S1.

[0044] from Figure 5 It can also be seen that the spacing between two adjacent first scanning signal lines 11 in the display area AA in the second direction is greater than the spacing between two adjacent first scanning signal lines 11 in the winding area S1; the spacing between two adjacent data signal lines 12 in the display area AA in the first direction is greater than the spacing between two adjacent data signal lines 12 in the winding area S1 in the first direction.

[0045] It can be understood that the first scan signal winding portion 112 is disposed around the hole area S2 in the first sub-region S11 and the second sub-region S12, and the data signal winding portion 122 is disposed around the hole area only in the second sub-region S12.

[0046] In the present application, by arranging the first scanning signal winding portion 112 around the hole area S2 in the first sub-area S11 and the second sub-area S12, and the data signal winding portion 122 is only arranged around the hole area in the second sub-area S12, the overlapping area between the first scanning signal winding portion 112 and the data signal winding portion 122 of the target scanning signal line 11` can be reduced, and the first scanning signal winding portion 112 and the data signal winding portion 122 of the target scanning signal line 11` are arranged to have no overlap, thereby reducing the signal delay of the target scanning signal line 11`, reducing the influence of the delay of the first scanning signal transmitted by the target scanning signal line 11` on the pixel circuit, and improving the display uniformity of the display panel.

[0047] In an exemplary embodiment, see Figure 6 and Figure 7 , the display panel includes a substrate 21 , a first metal layer 22 and a target active layer 23 .

[0048] The first metal layer 22 is located on one side of the substrate 21, and the target active layer 23 is located on the side of the first metal layer 22 away from the substrate 21. The first metal layer 21 includes the first scanning signal line 11 and the gate portion of the driving transistor in the pixel circuit; the orthographic projection of the first scanning signal line 11 on the target plane overlaps with the orthographic projection of the target active layer 23 on the target plane, and the target active layer 23 is connected to the gate portion of the driving transistor in the pixel circuit, and the target plane includes the plane where the substrate 21 is located.

[0049] It can be understood that in the display area AA, the gate portion 13 of the driving transistor and each first scanning signal line 11 in each pixel circuit are located on the first metal layer 22, and the gate portion 13 of the driving transistor is spaced apart from the first scanning signal line, the target active layer 23 is connected to the gate portion 13 of the driving transistor, and the orthographic projection of the first scanning signal line 11 on the plane where the substrate 21 is located overlaps with the orthographic projection of the target active layer 23 on the plane where the substrate 21 is located, thereby causing a parasitic capacitance to exist between the first scanning signal line 11 and the gate portion 13 of the driving transistor. When the first scanning signal transmitted on the first scanning signal line 21 undergoes a level jump, since the potential at both ends of the capacitor remains relatively stable, the gate potential of the driving transistor will jump following the level jump of the first scanning signal. In the present application, by reducing or even eliminating the overlapping area between the first scanning signal line and the data signal line relatively close to the hole area, the signal delay of the first scanning signal line relatively close to the hole area can be reduced, thereby increasing the coupling amount of the gate potential of the driving transistor in the pixel circuit corresponding to these first scanning signal lines, raising the gate potential of the driving transistor in the corresponding pixel circuit, reducing the brightness of the corresponding light-emitting element, and improving the brightness uniformity around the hole area of ​​the display panel.

[0050] In an exemplary embodiment, please refer to Figure 6 The display panel also includes a second metal layer 24 and a third metal layer 25 .

[0051] The second metal layer 24 is located between the first metal layer 22 and the target active layer 23, and the third metal layer 25 is located on the side of the target active layer 23 away from the substrate 21. In the winding area S1, the first scanning signal line 11 includes a first winding portion and a second winding portion that are electrically connected, wherein the first winding portion is located in the first metal layer and the second winding portion is located in the second metal layer, or the first winding portion is located in the second metal layer and the second winding portion is located in the third metal layer.

[0052] In applications, the first scanning signal line 11 can be wound in a double-layer winding manner in the winding area. For example, when the first scanning signal line 11 enters the winding area, the first scanning signal line 11 can be divided into an electrically connected first winding portion and a second winding portion, and the first winding portion is located in the first metal layer 22 and the second winding portion is located in the second metal layer 24 by punching, or the first winding portion is located in the second metal layer 24 and the second winding portion is located in the third metal layer 25 by punching.

[0053] In one example, assuming that the display panel includes N levels of first scan signal lines in the winding area, the first winding portion of the i-th level first scan signal line 11 can be wound on the first metal layer 22, and the second winding portion of the i-th level first scan signal line 11 can be wound on the second metal layer 24; the first winding portion of the i+1-th level first scan signal line 11 can be wound on the second metal layer 24, and the second winding portion of the i+1-th level first scan signal line 11 can be wound on the third metal layer 25; the first winding portion of the i+2-th level first scan signal line 11 can be wound on the first metal layer 22, and the second winding portion of the i+2-th level first scan signal line 11 can be wound on the second metal layer 24, and so on, alternating double-layer winding.

[0054] In an exemplary embodiment, see Figure 6 and Figure 7 , the display panel also includes a plurality of light-emitting control signal lines 14, which are used to provide light-emitting control signals for the pixel circuit. In the display area, the light-emitting control signal line is located in the first metal layer 22, and is located on the side of the gate portion 13 of the driving transistor away from the first scanning signal line 11. Assuming that the display panel includes N levels of light-emitting control signal lines in the winding area, the i-th level light-emitting control signal line is connected to the i+1-th level light-emitting control signal line, and the i-th level light-emitting control signal line is connected to the i+1-th level light-emitting control signal line and is located in the first metal layer; the i+2-th level light-emitting control signal line is connected to the i+3-th level light-emitting control signal line, and the i+2-th level light-emitting control signal line is connected to the i+3-th level light-emitting control signal line and is located in the second metal layer, 1≤i≤N-3.

[0055] When the light-emitting control signal line is located in the display area AA, the light-emitting control signal line 14 is located in the first metal layer 22. When the light-emitting control signal line 14 enters the winding area, two adjacent levels of light-emitting control signal lines 14 are connected together by punching to realize combined winding. In addition, the i-th level light-emitting control signal line and the i+1-th level light-emitting control signal line are combined and wound in the first metal layer 22, the i+2-th level light-emitting control signal line and the i+3-th level light-emitting control signal line are combined and wound in the second metal layer 24, and so on. The combined windings are alternately carried out in this way.

[0056] In an exemplary embodiment, the display panel further includes a plurality of second scanning signal lines 15 and a plurality of third scanning signal lines 16 .

[0057] The second scanning signal line 15 is used to provide the pixel circuit with a second scanning signal, which is used to control the threshold compensation process of the pixel circuit. The third scanning signal line 16 is used to provide the pixel circuit with a third scanning signal, which is used to control the first initialization process of the pixel circuit.

[0058] Among them, in the display area AA, the second scanning signal line 15 is located at the second metal layer and the third metal layer at the same time, and the third scanning signal line 16 is located at the second metal layer and the third metal layer at the same time; in the winding area, two adjacent rows of second scanning signal lines 15 are located at the first metal layer and the second metal layer respectively, and two adjacent rows of third scanning signal lines 16 are located at the first metal layer and the second metal layer respectively.

[0059] In applications, the second metal layer 24 and the third metal layer 25 can be used as the top-bottom double gate of the threshold compensation transistor and the first initialization transistor in the pixel circuit. When the second scan signal line 15 and the third scan signal line 16 are located in the display area AA, the second scan signal line 15 and the third scan signal line 16 can be located in the second metal layer 24 and the third metal layer 25 at the same time and arranged at intervals. When the second scan signal line 15 and the third scan signal line 16 enter the winding area, assuming that the winding area has N levels of second scan signal lines 15 and N levels of third scan signal lines 16, then the i-th level second scan signal line 15 and the i-th level third scan signal line 16 can be wound on the first metal layer 22 by punching, and the i+1-th level second scan signal line 15 and the i+1-th level third scan signal line 16 can be wound on the second metal layer 24 by punching.

[0060] In an exemplary embodiment, see Figure 6 The display panel further includes a fourth metal layer 25 and a fifth metal layer 27. The fourth metal layer 25 is located on a side of the third metal layer 25 away from the substrate, and the fifth metal layer 27 is located on a side of the fourth metal layer 25 away from the substrate.

[0061] The first scanning signal line 11 can be double-layered by punching holes in the fourth metal layer 25, the first scanning signal line 11 of the light emitting control signal line can be combined and wound by punching holes in the fourth metal layer 25, and the second scanning signal line 15 and the third scanning signal line 16 can be wound by punching holes in the fourth metal layer 25. The data signal line can be located in the fifth metal layer 27.

[0062] In an exemplary embodiment, see Figure 8 The pixel circuit of the display panel of the present application includes: a data writing transistor T2, a threshold compensation transistor T3, a first initialization transistor T4, a second initialization transistor T5, a first light emission control transistor T6, a second light emission control transistor T7 and a storage capacitor Cst.

[0063] The first electrode of the data writing transistor T2 is connected to the data signal line for receiving the data signal Vdata, the second end of the data writing transistor T2 is connected to the first electrode of the driving transistor T1, the gate of the data writing transistor T2 is connected to the first scanning signal line for receiving the first scanning signal SP, wherein a parasitic capacitor C1 is provided between the gate of the data writing transistor T2 and the gate of the driving transistor T1.

[0064] The first electrode of the threshold compensation transistor T3 is connected to the second electrode of the driving transistor T1 , the second electrode of the threshold compensation transistor T3 is connected to the gate of the driving transistor T1 , and the gate of the threshold compensation transistor T3 is connected to the second scanning signal line for receiving the second scanning signal SN1 .

[0065] The first electrode of the first initialization transistor T4 is used to receive the first initialization signal Vref1 , the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 , and the gate of the first initialization transistor T4 is connected to the third scan signal line for receiving the third scan signal SN2 .

[0066] The first electrode of the second initialization transistor T5 is used to receive the second initialization signal Vref2, the second electrode of the second initialization transistor T5 is connected to the first electrode of the light emitting element D, and the gate of the second initialization transistor T5 is connected to the first scanning signal line for receiving the first scanning signal SP.

[0067] The first electrode of the first light emitting control transistor T6 is used to receive the first power supply signal PVDD, the second electrode of the first light emitting control transistor T6 is connected to the first electrode of the driving transistor T1, and the gate of the first light emitting control transistor T6 is connected to the light emitting control signal line for receiving the light emitting control signal EM.

[0068] The first electrode of the second light emitting control transistor T7 is connected to the second electrode of the driving transistor T1, the second electrode of the second light emitting control transistor T7 is connected to the first electrode of the light emitting element D, and the gate of the second light emitting control transistor T7 is connected to the light emitting control signal line for receiving the light emitting control signal EM.

[0069] The first plate of the storage capacitor Cst is used to receive the first power signal PVDD, and the second plate of the storage capacitor Cst is connected to the gate of the driving transistor T1.

[0070] Based on the same application concept, an embodiment of the present application also provides a display device. Fig. 9 A schematic diagram of the structure of a display device 200 provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the display device 200 includes the display panel 100 in any of the above embodiments. Fig. 9As shown, the display device 200 includes a display panel 100. Therefore, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiment, and the similarities can be understood by referring to the above explanation of the display panel 100, which will not be repeated below.

[0071] The display device 200 provided in the embodiment of the present application can be Fig. 9 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present application do not specifically limit this.

[0072] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel comprises a display area, a winding area and a hole area, wherein the display area is arranged around at least a portion of the winding area; the display panel further comprises: A plurality of first scanning signal lines, used for providing a first scanning signal to the pixel circuit; A plurality of data signal lines, used for providing data signals to the pixel circuit; In the winding area, the data signal line and the first scanning signal line are arranged around the hole area; Among them, the overlapping area of ​​the orthographic projection of the target scan signal line on the target plane and the orthographic projection of the target data signal line on the target plane is less than a preset threshold; the target scan signal line is the first scan signal line closest to the hole area among multiple first scan signal lines, and the target data signal line is the data signal line closest to the hole area among multiple data signal lines.

2. The display panel according to claim 1, characterized in that: The winding area is divided into a first sub-area and a second sub-area by the target data signal line; The first scanning signal line is arranged around the hole area in the first sub-area and the second sub-area, and the data signal line is arranged around the hole area in the second sub-area.

3. The display panel according to claim 1, characterized in that: At least part of the first scan signal line includes a first A scan signal line, a first scan signal winding portion and a first B scan signal line connected in sequence; wherein the first A scan signal line and the first B scan signal line are located in the display area and extend along a first direction, and the first scan signal winding portion is located in the winding area.

4. The display panel according to claim 1, characterized in that: At least part of the data signal lines include a data signal line A, a data signal winding portion and a data signal line B connected in sequence, the data signal line A and the data signal line B are located in the display area and extend along the second direction, and the data signal winding portion is located in the winding area.

5. The display panel according to claim 1, characterized in that: In the display area, a distance between two adjacent first scanning signal lines in the second direction is greater than a distance between two adjacent first scanning signal lines in the winding area in the second direction; In the display area, a distance between two adjacent data signal lines in the first direction is greater than a distance between two adjacent data signal lines in the winding area in the first direction, wherein the first direction intersects with the second direction.

6. The display panel according to claim 1, characterized in that: The display panel comprises: substrate; A first metal layer, located on one side of the substrate; a target active layer, located on a side of the first metal layer away from the substrate; Among them, the first metal layer includes a first scanning signal line and a gate portion of a driving transistor in the pixel circuit; the orthographic projection of the first scanning signal line on the target plane overlaps with the orthographic projection of the target active layer on the target plane, and the target active layer is connected to the gate portion of the driving transistor in the pixel circuit, and the target plane includes the plane where the substrate is located.

7. The display panel according to claim 6, characterized in that: The display panel further includes: a second metal layer, located between the first metal layer and the target active layer; a third metal layer, located on a side of the target active layer away from the substrate; In the winding area, the first scanning signal line includes a first winding portion and a second winding portion that are electrically connected, wherein the first winding portion is located in the first metal layer and the second winding portion is located in the second metal layer, or the first winding portion is located in the second metal layer and the second winding portion is located in the third metal layer.

8. The display panel according to claim 7, characterized in that: The display panel further includes: A plurality of light-emitting control signal lines, wherein the light-emitting control signal lines are used to provide light-emitting control signals for the pixel circuit; Among them, in the display area, the light-emitting control signal line is located in the first metal layer, and is located on the side of the gate portion of the driving transistor away from the first scanning signal line; in the winding area, there are N light-emitting control signal lines, the i-th level light-emitting control signal line is connected to the i+1-th level light-emitting control signal line, and the i-th level light-emitting control signal line is connected to the i+1-th level light-emitting control signal line and is located in the first metal layer; the i+2-th level light-emitting control signal line is connected to the i+3-th level light-emitting control signal line, and the i+2-th level light-emitting control signal line is connected to the i+3-th level light-emitting control signal line and is located in the second metal layer, 1≤i≤N-3.

9. The display panel according to claim 7, characterized in that: The display panel further includes: a plurality of second scanning signal lines, wherein the second scanning signal lines are used to provide a second scanning signal to the pixel circuit, and the second scanning signal is used to control a threshold compensation process of the pixel circuit; Wherein, in the display area, the second scanning signal lines are located in the second metal layer and the third metal layer at the same time; in the winding area, two adjacent rows of the second scanning signal lines are located in the first metal layer and the second metal layer respectively.

10. The display panel according to claim 7, characterized in that: The display panel further includes: A plurality of third scanning signal lines, used for providing a third scanning signal to the pixel circuit, wherein the third scanning signal is used for controlling a first initialization process of the pixel circuit; In the display area, the third scanning signal lines are located in both the second metal layer and the third metal layer; in the winding area, two adjacent rows of the third scanning signal lines are located in the first metal layer and the second metal layer, respectively.

11. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 10.

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