Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a display area and a non-display area located on one side of the display area. The display area comprises a plurality of pixel circuits and a plurality of data lines, and the data lines are used for providing data signals for the pixel circuits; the pixel circuit comprises a storage capacitor and a plurality of transistors; the non-display area comprises a first fan-out area, the first fan-out area comprises a plurality of first fan-out signal lines, and the first fan-out signal lines are electrically connected with the data lines; the display panel further comprises a substrate; the first metal layer is located on one side of the substrate, and the grid electrode of the at least one transistor is located on the first metal layer; the second metal layer is located on the side, away from the substrate, of the first metal layer, and one polar plate of the storage capacitor is located on the second metal layer; the third metal layer is located on the side, away from the substrate, of the second metal layer, and at least part of the first fan-out signal lines are located on the third metal layer; the resistivity of the first metal layer and the resistivity of the second metal layer are both larger than the resistivity of the third metal layer.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, display panels have been widely used in people's production and life. Existing display panels have the problem of heavy data line loading, which affects the display effect. Summary of the invention

[0003] The main purpose of the present application is to provide a display panel and a display device, so as to at least solve the problem of heavy load on data lines of the display panel in the prior art.

[0004] To achieve the above-mentioned purpose, according to one aspect of the present application, a display panel is provided, comprising a display area and a non-display area located on one side of the display area; the display area comprises a plurality of pixel circuits and a plurality of data lines, the data lines being used to provide data signals for the pixel circuits; the pixel circuits comprise storage capacitors and a plurality of transistors; the non-display area comprises a first fan-out area, the first fan-out area comprises a plurality of first fan-out signal lines, the first fan-out signal lines are electrically connected to the data lines; the display panel further comprises: a substrate; a first metal layer located on one side of the substrate, a gate of at least one of the transistors being located on the first metal layer; a second metal layer located on a side of the first metal layer away from the substrate, a plate of the storage capacitor being located on the second metal layer; a third metal layer located on a side of the second metal layer away from the substrate, at least part of the first fan-out signal lines being located on the third metal layer; wherein the resistivities of the first metal layer and the second metal layer are both greater than the resistivity of the third metal layer.

[0005] According to another aspect of the present application, based on the same inventive concept, a display device is also provided, comprising: any one of the display panels described above.

[0006] By applying the technical solution of the present application, among the first metal layer, the second metal layer and the third metal layer sequentially arranged in the direction away from the substrate, the resistivity of the third metal layer is the smallest, and at least a portion of the first fan-out signal line electrically connected to the data line is arranged in the third metal layer with small resistivity, thereby ensuring that the resistance of the first fan-out signal line is small, making the load of the first fan-out signal line small, and alleviating the problem of poor display effect of the display panel due to the large load of the data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0008] Figure 1 A schematic top view of a display panel provided in an embodiment of the present application is shown;

[0009] Figure 2 Shown along Figure 1 A schematic cross-sectional view obtained by the dashed line AA' in FIG.

[0010] Figure 3 A schematic structural diagram of a pixel circuit provided in an embodiment of the present application is shown;

[0011] Figure 4 A schematic top view of a display panel provided according to an embodiment of the present application is shown;

[0012] Figure 5 A schematic top view of another display panel provided in an embodiment of the present application is shown;

[0013] Figure 6 A schematic structural diagram of a display device provided according to an embodiment of the present application is shown.

[0014] The above drawings include the following reference numerals:

[0015] 10. display area; 11. non-display area; 12. data line; 13. storage capacitor; 131. first plate; 132. second plate; 14. transistor; 141. gate; 142. active layer; 143. drain; 144. source; 15. first fan-out area; 16. first fan-out signal line; 17. substrate; 18. pixel circuit; 19. light-emitting unit; 21. first signal routing; 22. short-circuit bar circuit; 23. first control transistor; 24. test signal line; 25. second signal routing; 26. driver chip; 27. second fan-out area; 28. bending area; 29. ​​second fan-out signal line; 30. power signal bus; 301. first part; 302. second part; 31. demultiplexing circuit; 32. data connection line; 34. multiplexer; 35. second control transistor; 100. display panel; 200. display device. DETAILED DESCRIPTION

[0016] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0017] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0018] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0019] As introduced in the background technology, in the prior art, the data line load of the display panel is relatively large. To solve this technical problem, the embodiments of the present application provide a display panel and a display device.

[0020] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0021] In this embodiment, a display panel is provided. Figure 1 is a schematic top view of a display panel according to an embodiment of the present application, Figure 2 is along Figure 1 The cross-sectional view is obtained by the dashed line AA' in FIG. Figure 1 and Figure 2 As shown, the display panel 100 includes a display area 10 and a non-display area 11 located on one side of the display area 10; the display area 10 includes a plurality of pixel circuits 18 and a plurality of data lines 12, and the data lines 12 are used to provide data signals for the pixel circuits 18; the pixel circuits 18 include storage capacitors 13 and a plurality of transistors 14; the non-display area 11 includes a first fan-out area 15, and the first fan-out area 15 includes a plurality of first fan-out signal lines 16, and the first fan-out signal lines 16 are electrically connected to the data lines 12;

[0022] The display panel 100 further includes:

[0023] Substrate 17;

[0024] Specifically, the substrate 17 is located in the display area 10 and the non-display area 11 .

[0025] A first metal layer, located on one side of the substrate 17, wherein a gate 141 of at least one transistor 14 is located on the first metal layer;

[0026] Specifically, there are other film layers between the substrate 17 and the first metal layer. The gate 141 of the transistor 14 may be a top gate structure or a bottom gate structure. Those skilled in the art may set the gates of some of the transistors 14 in the plurality of transistors 14 in the first metal layer, or may set the gates 141 of all the transistors 14 in the first metal layer.

[0027] A second metal layer is located on a side of the first metal layer away from the substrate 17, and one electrode plate (the first electrode plate 131) of the storage capacitor 13 is located on the second metal layer;

[0028] Specifically, there are other film layers between the first metal layer and the second metal layer.

[0029] A third metal layer is located on a side of the second metal layer away from the substrate 17, and at least a portion of the first fan-out signal line 16 is located on the third metal layer;

[0030] Specifically, there are other film layers between the second metal layer and the third metal layer. Those skilled in the art may only set some of the first fan-out signal lines 16 in the third metal layer, or may set all of the first fan-out signal lines 16 in the third metal layer. The first metal layer, the second metal layer, and the third metal layer are respectively located in the display area 10 and the non-display area 11.

[0031] Wherein, the resistivity of the first metal layer and the second metal layer are both greater than the resistivity of the third metal layer.

[0032] Through the above embodiments, among the first metal layer, the second metal layer and the third metal layer sequentially arranged in the direction away from the substrate, the resistivity of the third metal layer is the smallest, and at least a portion of the first fan-out signal line electrically connected to the data line is arranged in the third metal layer with small resistivity, thereby ensuring that the resistance of the first fan-out signal line is small, making the load of the first fan-out signal line small, and alleviating the problem of poor display effect of the display panel due to the large load of the data line.

[0033] like Figure 2As shown, the transistor 14 further includes an active layer 142, a drain 143 and a source 144. The other electrode plate (second electrode plate 132) of the storage capacitor 13 may be located at the first metal layer. The pixel circuit 18 further includes a light emitting unit 19.

[0034] Figure 3 A schematic diagram of a 7T1C pixel circuit of an embodiment of the present application is exemplarily shown, as shown in FIG. Figure 3 As shown, the above pixel circuit includes 7 transistors T1~T7 and 1 storage capacitor 13, wherein transistor T2 is the driving transistor of the pixel circuit, the initialization signal terminal VREF is used to provide the initialization signal, and the driving terminals Emit, S1 and S2 are all used to provide the driving signal. The working principle of the pixel circuit is: in the initialization stage, transistor T5 is turned on and transistor T7 is turned off; the voltage of the initialization signal terminal VREF is transmitted by transistor T5 to the first node N1 to initialize the driving transistor T2. In the data writing stage, transistors T5 and T7 are both turned off, transistors T3 and T6 are turned on, and the data signal terminal DATA receives the data signal transmitted by the data line to the second node N2; the signal of the second node N2 is transmitted to the third node N3 through the driving transistor T2, and the signal of the third node N3 is transmitted to the first node N1 through the transistor T3, so that the potential of the first node N1 is increased; in the light emitting stage, transistors T3 and T6 are turned off, transistors T1 and T4 are turned on, and the driving current generated by the driving transistor T2 is transmitted to the light emitting unit 19, so that the light emitting unit 19 emits light. It should be noted that Figure 3 Only a 7T1C mode circuit structure of the pixel circuit is exemplified, but the present application is not limited to this. The specific circuit structure of the pixel circuit can be adaptively adjusted according to the needs; furthermore, the pixel circuit can also be embodied as 8T1C, 9T2C, etc., which is not limited in the present application.

[0035] In one alternative, Figure 1 As shown, the display panel 100 further includes a first signal line 21 and a shorting bar circuit 22, wherein the shorting bar circuit 22 is located on a side of the first fan-out area 15 away from the display area 10; the first signal line 21 and the shorting bar circuit 22 are electrically connected, the first signal line 21 is electrically connected to the first fan-out signal line 16, and the first signal line 21 and the first fan-out signal line 16 are arranged in different layers, that is, the first signal line 21 is not located in the third metal layer. In this embodiment, the electrically connected first fan-out signal line and the first signal line are arranged in different layers, so that the static electricity accumulated on the signal line can be released, the influence of static electricity on the signal line can be avoided, and the stability of signal transmission can be ensured.

[0036] Specifically, the first signal wiring 21 and the first fan-out signal line 16 are connected in different layers through vias. There may be multiple first signal wirings 21, and the multiple first signal wirings 21 are electrically connected to the first fan-out signal lines 16 in a one-to-one correspondence.

[0037] For example, Figure 4 As shown, the shorting bar circuit 22 includes a plurality of first control transistors 23. Under the control of an enable signal EN, the first control transistors 23 electrically connect the first signal trace 21 and the test signal line 24. The first signal trace can be connected to the test signal line through the shorting bar circuit to test some functions of the display panel, thereby quickly and accurately locating the problem.

[0038] like Figure 4 As shown, there are multiple test signal lines 24, the control end of the first control transistor 23 is used to receive the enable signal EN, the input end IN of the first control transistor 23 is electrically connected to the test signal line 24 one by one, and the output ends OUT of the plurality of first control transistors 23 are electrically connected and then connected to the first signal wiring 21. In the display test phase, the first control transistor 23 is turned on by the enable signal, and a display test signal is applied to the test signal line 24, so that the display test signal is transmitted to the data line of the display area through the first control transistor 23 and the first signal wiring 21, so that the display panel displays images such as red, green, blue, gray or black, and realizes the display test of each sub-pixel. After the display test is completed, the short-circuit rod circuit can be cut and removed along the cutting line to realize the narrow frame design of the display panel, or the short-circuit rod circuit can be retained.

[0039] In some embodiments, Figure 1 As shown, the display panel further includes a plurality of second signal wires 25, the second signal wires 25 are located in the third metal layer, and the second signal wires 25 are electrically connected to the driver chip 26; one end of the first signal wire 21 is electrically connected to the first fan-out signal line 16, and the other end of the first signal wire 21 is electrically connected to the second signal wire 25. In this embodiment, the second signal wire connecting the driver chip and the first signal wire is arranged in the third metal layer, and since the resistivity of the third metal layer is relatively small, the load of the second signal wire is relatively small, thereby further ensuring a better display effect of the display panel.

[0040] like Figure 2As shown, the display panel further includes a fourth metal layer, the fourth metal layer is located between the third metal layer and the second metal layer, or the fourth metal layer is located on the side of the third metal layer away from the substrate 17; at least part of the first signal wiring 21 is located in the fourth metal layer; wherein the resistivity of the first metal layer and the second metal layer are both greater than the resistivity of the fourth metal layer. In this embodiment, the first signal wiring is arranged in the fourth metal layer with a smaller resistivity, which ensures that the resistance of the first signal wiring is smaller, so that the load of the first signal wiring is smaller, thereby further alleviating the problem of poor display effect caused by the large load of the data line, and further ensuring a better display effect of the display panel.

[0041] It should be noted that Figure 2 The embodiment in which the fourth metal layer is located on the side of the third metal layer away from the substrate 17 is merely exemplified, and does not constitute a limitation to the present application. The fourth metal layer may also be located between the third metal layer and the second metal layer.

[0042] Specifically, the resistivity of the fourth metal layer may be the same as the resistivity of the third metal layer, or the resistivity of the fourth metal layer may be different from the resistivity of the third metal layer.

[0043] In the present application, the display panel further includes: a plurality of third signal lines, one end of the third signal line is electrically connected to the first signal line, the other end of the third signal line is electrically connected to the second signal line, part of the third signal line is located in the first metal layer, and part of the third signal line is located in the second metal layer. In this embodiment, the third signal line is arranged in the first metal layer and the second metal layer, and the third signal line is connected in parallel at both ends of the first signal line with a smaller resistivity, which can further reduce the resistance of the signal line after the parallel connection, thereby achieving the effect of further reducing the signal load.

[0044] Furthermore, the plurality of third signal lines are alternately distributed in the first metal layer and the second metal layer. In other words, along the arrangement direction of the plurality of third signal lines, the plurality of third signal lines are alternately located in the first metal layer and the second metal layer.

[0045] In another alternative, Figure 1As shown, the display panel also includes a second fan-out area 27 and a bending area 28, the second fan-out area 27 is located between the bending area 28 and the display area 10, and the first fan-out area 15 is located on the side of the bending area 28 away from the display area 10; the second fan-out area 27 includes a plurality of second fan-out signal lines 29, and the second fan-out signal lines 29 are electrically connected to the data lines 12 and the first fan-out signal lines 16, respectively; among the plurality of second fan-out signal lines 29, some of the second fan-out signal lines 29 are located in the first metal layer, and some of the second fan-out signal lines 29 are located in the second metal layer. In this embodiment, the second fan-out signal lines in the second fan-out area between the bending area and the display area are arranged in the first metal layer and the second metal layer. By arranging the second fan-out signal lines in layers, the required number of second fan-out signal lines can be arranged in a limited space, so that the spacing between adjacent second fan-out signal lines meets the signal line spacing requirements. This can not only effectively reduce the signal interference between adjacent second fan-out signal lines and improve the stability and reliability of signal transmission, but also is conducive to the narrow-frame design of the display panel.

[0046] Furthermore, the plurality of second fan-out signal lines are alternately distributed in the first metal layer and the second metal layer. In other words, along the arrangement direction of the plurality of second fan-out signal lines, the plurality of second fan-out signal lines are alternately located in the first metal layer and the second metal layer.

[0047] And, if Figure 1 As shown, the second fan-out signal line 29 is also located in the bending area 28 .

[0048] Specifically, Figure 1 As shown, the display panel further includes a power signal bus 30 located in the non-display area 10, and the power signal bus 30 includes a first portion 301 located in the second fan-out area 27, and the first portion 301 extends along a first direction, and the first direction intersects with the extension direction of the data line 12; in the thickness direction of the display panel, the first portion 301 overlaps with the second fan-out signal line 29, that is, the first portion 301 and the second fan-out signal line 29 overlap in their orthographic projections on the substrate; and the first portion 301 is located in the third metal layer. The first portion of the power signal bus extending along the first direction is set in the third metal layer with a smaller resistivity, which ensures that the load of the power signal bus is smaller.

[0049] In an optional solution, the first direction and the extending direction of the data line 12 are perpendicular to each other.

[0050] For example, Figure 1 and Figure 2As shown, the power signal bus 30 also includes a second portion 302 located in the first fan-out area 15; the display panel also includes a fourth metal layer, the fourth metal layer is located between the third metal layer and the second metal layer, or the fourth metal layer is located on the side of the third metal layer away from the substrate 17; the second portion 302 is located in the fourth metal layer; the resistivity of the first metal layer and the second metal layer are both greater than the resistivity of the fourth metal layer; wherein, in the thickness direction of the display panel, the second portion 302 and the first fan-out signal line 16 at least partially overlap, that is, the orthographic projections of the second portion 302 and the first fan-out signal line 16 on the substrate overlap. In this embodiment, the second portion of the power signal bus is set in the fourth metal layer with a smaller resistivity, which ensures that the resistance of the power signal bus is smaller, so that the load of the power signal bus is smaller.

[0051] In a specific application process, the first part 301 and the second part 302 are electrically connected together. Figure 2 Only the relative positional relationship between the first part 301 and the second part 302 is shown exemplarily, and the electrical connection relationship between the two is not shown.

[0052] like Figure 1 As shown, the second portion 302 extends along the first direction.

[0053] Specifically, the resistivity of the fourth metal layer may be the same as the resistivity of the third metal layer, or the resistivity of the fourth metal layer may be different from the resistivity of the third metal layer.

[0054] The power signal bus 30 includes at least one of a positive power signal bus PVDD and a negative power signal bus PVEE.

[0055] In this application, if Figure 1 As shown, the display panel further includes a demultiplexer (demux) circuit 31, and the demultiplexer circuit 31 is electrically connected to the data line 12 and the second fan-out signal line 29, respectively. That is, the data line 12 and the second fan-out signal line 29 are electrically connected through the demultiplexer circuit 31. Through the demultiplexer circuit, an input signal can be distributed to one of the multiple output ports to achieve signal selection and distribution, thereby effectively reducing the number of the second fan-out signal lines.

[0056] Demultiplexing circuits are widely used in display panels due to their low cost. However, as the display resolution increases, the pulse width reserved for the demultiplexing circuit gradually decreases, causing the charging process of the demultiplexing circuit to affect the uniformity of the screen. In addition, the demand for narrow bezels of display panels increases the load on the data lines, causing further deterioration of the screen uniformity during the charging process of the demultiplexing circuit.

[0057] By adopting the above-mentioned technical solution of the present application, at least a part of the first fan-out signal line electrically connected to the data line is set in the third metal layer with low resistivity, thereby ensuring that the resistance of the first fan-out signal line is small, thereby ensuring that the signal load of the first fan-out signal line is small, alleviating the problem of uneven display of the display panel during the charging process of the demultiplexing circuit caused by the heavy load of the data line, reducing the risk of charging of the demultiplexing circuit caused by the heavy load, and effectively solving the above-mentioned problems.

[0058] like Figure 4 As shown, the demultiplexing circuit 31 includes a plurality of 1:n multiplexers 34, that is, one multiplexer 34 includes n second control transistors 35, the input terminals IN of the n second control transistors 35 are electrically connected together as the input terminal of the multiplexer 34, the control terminals G of the n second control transistors 35 serve as the control terminal of the multiplexer 34, the output terminals OUT of the n second control transistors 35 serve as the output terminal of the multiplexer 34, the input terminal of the multiplexer 34 is electrically connected to the second fan-out signal line 29, the control terminals of the n second control transistors 35 are electrically connected to n clock control signal lines one by one, the output terminals of the n second control transistors 35 are electrically connected to the data lines 12 one by one, and the second control transistors 35 are controlled to turn on through the clock control signal lines, so that the data voltage is written to the data lines 12.

[0059] It should be noted that Figure 4 Only an embodiment where n=2 is shown exemplarily, that is, a 1:2 multiplexer is shown. Those skilled in the art may also select a multiplexer with other values ​​of n to form the above demultiplexing circuit, for example, a 1:4 multiplexer to form the above demultiplexing circuit.

[0060] In actual application, the materials of the first metal layer and the second metal layer include molybdenum; the materials of the third metal layer include titanium and aluminum. Since the resistivity of titanium and aluminum is lower than that of molybdenum, a third metal layer with lower resistivity can be obtained. Molybdenum has a high melting point, is not easy to deform, and has strong corrosion resistance, so that the performance and reliability of the obtained first metal layer and the second metal layer are better.

[0061] In addition, the material of the fourth metal layer includes titanium and aluminum, so that a fourth metal layer with low resistivity can be obtained.

[0062] In a specific application process, the material of the fourth metal layer and the third metal layer may be the same or different.

[0063] In some other embodiments, Figure 5 As shown, the display panel further includes a data connection line 32, the data connection line 32 is at least partially located in the display area 10, the data connection line 32 is electrically connected to the data line 12, and the data connection line 32 is electrically connected to the first fan-out signal line 16. This embodiment introduces FIAA (Fanout inactive area, fan-out line is arranged in the display area) design in the display panel, and transfers at least part of the data connection line from the original non-display area to the display area, thereby saving the layout space of the non-display area, reducing the border width, and improving the screen-to-body ratio, which is conducive to the narrow border design of the display panel.

[0064] Specifically, the data connection line includes a first connection line segment extending along a first direction and a second connection line segment extending along a second direction, the first end of the first connection line segment is electrically connected to the data line in the display area, the second end of the first connection line segment is electrically connected to the first end of the second connection line segment, the second end of the second connection line segment is electrically connected to the first fan-out signal line, the second direction is parallel to the extension direction of the data line, and the first direction intersects with the second direction.

[0065] In addition, the second connecting line segment at least partially overlaps with the data line in the display area.

[0066] In the present application, the first metal layer is also referred to as a gate metal layer, the second metal layer is also referred to as an electrode layer, and the third metal layer and the fourth metal layer are also referred to as data line layers.

[0067] The embodiment of the present application also provides a display device. Figure 6 A schematic diagram of the structure of a display device 200 of the present application is shown as an example. Figure 6 As shown, the display device 200 includes: any one of the display panels 100 described above.

[0068] In the above embodiments, the display device includes any one of the above display panels, which is provided with a first metal layer, a second metal layer and a third metal layer in sequence along a direction away from the substrate, and the third metal layer has the smallest resistivity among the three. At least a portion of the first fan-out signal line electrically connected to the data line is provided in the third metal layer with small resistivity, thereby ensuring that the resistance of the first fan-out signal line is small, so that the load of the first fan-out signal line is small, thereby ensuring that the load of the signal transmitted to the data line is small, alleviating the problem of poor display effect of the display panel due to the large load of the data line, and ensuring that the display effect of the display device is good.

[0069] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0070] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0071] 1) In the display panel of the present application, among the first metal layer, the second metal layer and the third metal layer arranged in sequence in the direction away from the substrate, the resistivity of the third metal layer is the smallest, and at least a portion of the first fan-out signal line electrically connected to the data line is arranged in the third metal layer with small resistivity, thereby ensuring that the resistance of the first fan-out signal line is small, making the load of the first fan-out signal line small, and alleviating the problem of poor display effect of the display panel due to the large load of the data line.

[0072] 2) The display device of the present application includes any one of the above-mentioned display panels, which are provided with a first metal layer, a second metal layer and a third metal layer in sequence along a direction away from the substrate. Among the three, the third metal layer has the smallest resistivity. At least a portion of the first fan-out signal line electrically connected to the data line is provided in the third metal layer with small resistivity, thereby ensuring that the resistance of the first fan-out signal line is small, making the load of the first fan-out signal line small, alleviating the problem of poor display effect of the display panel due to the large load of the data line, and ensuring that the display effect of the display device is good.

[0073] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display area includes a display area and a non-display area located on one side of the display area; the display area includes a plurality of pixel circuits and a plurality of data lines, the data lines are used to provide data signals for the pixel circuits; the pixel circuits include storage capacitors and a plurality of transistors; the non-display area includes a first fan-out area, the first fan-out area includes a plurality of first fan-out signal lines, and the first fan-out signal lines are electrically connected to the data lines; The display panel further includes: substrate; A first metal layer, located at one side of the substrate, wherein a gate of at least one of the transistors is located at the first metal layer; A second metal layer is located on a side of the first metal layer away from the substrate, and one plate of the storage capacitor is located on the second metal layer; A third metal layer is located on a side of the second metal layer away from the substrate, and at least part of the first fan-out signal line is located on the third metal layer; The resistivity of the first metal layer and the second metal layer are both greater than the resistivity of the third metal layer.

2. The display panel according to claim 1, characterized in that: The display panel also includes a first signal routing line and a short-circuit bar circuit, wherein the short-circuit bar circuit is located on a side of the first fan-out area away from the display area; the first signal routing line is electrically connected to the short-circuit bar circuit, the first signal routing line is electrically connected to the first fan-out signal line, and the first signal routing line and the first fan-out signal line are arranged on different layers.

3. The display panel according to claim 2, characterized in that: The shorting bar circuit includes a plurality of first control transistors. Under the control of an enable signal, the first control transistors electrically connect the first signal wiring and the test signal line.

4. The display panel according to claim 2, characterized in that: The display panel also includes a plurality of second signal lines, the second signal lines are located in the third metal layer, and the second signal lines are electrically connected to the driver chip; one end of the first signal line is electrically connected to the first fan-out signal line, and the other end of the first signal line is electrically connected to the second signal line.

5. The display panel according to claim 2, characterized in that: The display panel also includes a fourth metal layer, which is located between the third metal layer and the second metal layer, or the fourth metal layer is located on a side of the third metal layer away from the substrate; at least a portion of the first signal routing is located in the fourth metal layer; wherein the resistivity of the first metal layer and the second metal layer are both greater than the resistivity of the fourth metal layer.

6. The display panel according to claim 1, characterized in that: The display panel also includes a second fan-out area and a bending area, the second fan-out area is located between the bending area and the display area, and the first fan-out area is located on the side of the bending area away from the display area; the second fan-out area includes a plurality of second fan-out signal lines, and the second fan-out signal lines are electrically connected to the data lines and the first fan-out signal lines, respectively; among the plurality of second fan-out signal lines, some of the second fan-out signal lines are located in the first metal layer, and some of the second fan-out signal lines are located in the second metal layer.

7. The display panel according to claim 6, characterized in that: The display panel also includes a power signal bus located in the non-display area, and the power signal bus includes a first portion located in the second fan-out area, the first portion extends along a first direction, and the first direction intersects with the extension direction of the data line; in the thickness direction of the display panel, the first portion overlaps with the second fan-out signal line, and the first portion is located in the third metal layer.

8. The display panel according to claim 7, characterized in that: The power signal bus also includes a second part located in the first fan-out area; the display panel also includes a fourth metal layer, the fourth metal layer is located between the third metal layer and the second metal layer, or the fourth metal layer is located on the side of the third metal layer away from the substrate; the second part is located in the fourth metal layer; the resistivity of the first metal layer and the second metal layer are both greater than the resistivity of the fourth metal layer; wherein, in the thickness direction of the display panel, the second part and the first fan-out signal line at least partially overlap.

9. The display panel according to claim 7, characterized in that: The power signal bus includes at least one of a positive power signal bus and a negative power signal bus.

10. The display panel according to claim 6, characterized in that: The display panel further includes a demultiplexing circuit, and the demultiplexing circuit is electrically connected to the data line and the second fan-out signal line respectively.

11. The display panel according to claim 1, characterized in that: The materials of the first metal layer and the second metal layer include molybdenum; the material of the third metal layer includes titanium and aluminum.

12. The display panel according to claim 1, characterized in that: The display panel further includes a data connection line, wherein the data connection line is at least partially located in the display area, the data connection line is electrically connected to the data line, and the data connection line is electrically connected to the first fan-out signal line.

13. A display device, characterized in that: include: The display panel according to any one of claims 1 to 12.

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