Memory distortion cancellation in power amplifier circuits

Abstract

Memory distortion cancellation in a power amplifier circuit (58) is provided. The power amplifier circuit (58) includes one or more amplifier stages (40, 42) each configured to amplify a radio frequency (RF) signal based on a time-varying modulated voltage received at a respective collector node. Notably, each of the amplifier stages (40, 42) may inherently leak a derivative of a time-varying modulation voltage, also referred to as a modulation current, from a respective collector node into a respective input node, which may result in an undesired remodulation term, which may reduce the adjacent channel leakage ratio (ACLR) of the power amplifier circuit (58). Herein, a cancellation circuit (54, 60) is configured to inject a cancellation current to the respective input node to cancel at least a portion of the leaked modulation current.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 401,779 filed on August 29, 2022 and the benefit of U.S. Provisional Patent Application No. 63 / 478,752 filed on January 6, 2023, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The technology of the present disclosure generally relates to eliminating memory distortion in power amplifier circuits. Background Art

[0004] Mobile communication devices have become increasingly common in today's society for providing wireless communication services. The popularity of these mobile communication devices is driven in part by the many functions currently enabled on such devices. Increased processing power of such devices means that mobile communication devices have evolved from pure communication tools to sophisticated mobile multimedia centers capable of enhancing the user experience.

[0005] The redefined user experience relies on higher data rates provided by advanced fifth generation (5G) and 5G new radio (5G-NR) systems, where transmit circuits typically amplify radio frequency (RF) to higher power before transmission. In a typical transmit circuit, the transceiver circuit is configured to generate an RF signal, the power management circuit is configured to generate a modulation voltage, the power amplifier circuit is configured to amplify the RF signal based on the modulation voltage, and the antenna circuit is configured to transmit the RF signal at one or more RF frequencies.

[0006] The RF signals transmitted in 5G and 5G-NR systems are subject to strict adjacent channel leakage ratio (ACLR) requirements imposed by standards bodies and / or regulators. ACLR defines the ratio between the power of the RF signal transmitted on the intended radio channel and the power of the RF signal received in the unintended adjacent radio channel. Given that the ACLR of a wideband RF signal can be largely dominated by remodulation terms, such as third-order intermodulation products (IMD3), it is desirable to improve the IMD3 performance of the transmit circuitry, thereby improving the ACLR. Summary of the invention

[0007] Embodiments of the present disclosure relate to memory distortion cancellation in a power amplifier circuit. The power amplifier circuit includes one or more amplifier stages, each of which is configured to amplify a radio frequency (RF) signal based on a time-varying modulation voltage received at a corresponding collector node. Notably, each of the amplifier stages may inherently cause a derivative of the time-varying modulation voltage (also referred to as a modulation current) to leak from the corresponding collector node into the corresponding input node, which may produce an undesired remodulation term that may reduce the adjacent channel leakage ratio (ACLR) of the power amplifier circuit. In addition, as a derivative of the time-varying modulation voltage, the undesired remodulation term typically has a memory effect that is difficult to compensate for by, for example, digital predistortion. In an embodiment disclosed herein, a cancellation circuit is provided in the power amplifier circuit for injecting a cancellation current into the corresponding input node to offset at least a portion of the leaked modulation current. By eliminating the leaked modulation current, the undesired modulation term can be suppressed, thereby helping to improve the ACLR of the power amplifier circuit.

[0008] In one aspect, a power amplifier circuit is provided. The power amplifier circuit includes an input stage amplifier. The input stage amplifier is configured to receive an RF signal via an input stage input node and to receive a time-varying modulation voltage via an input stage collector node. The input stage amplifier is further configured to amplify the RF signal based on the time-varying modulation voltage received via the input stage collector node. The power amplifier circuit also includes an output stage amplifier. The output stage amplifier is coupled to the input stage amplifier and is configured to receive the RF signal amplified by the input stage amplifier via an output stage input node and to receive the time-varying modulation voltage via an output stage collector node. The output stage amplifier is further configured to further amplify the RF signal based on the time-varying modulation voltage received via the output stage collector node. The power amplifier circuit also includes an output stage cancellation circuit. The output stage cancellation circuit is coupled to the output stage collector node and the output stage input node. The output stage cancellation circuit is configured to generate an output stage cancellation current based on the time-varying modulation voltage received via the output stage collector node, thereby suppressing a modulated output stage current leaking from the output stage collector node into the output stage input node.

[0009] In another aspect, a method for canceling memory distortion in a power amplifier circuit is provided. The method includes amplifying an RF signal received via an input stage input node based on a time-varying modulation voltage received via an input stage collector node. The method also includes further amplifying the RF signal received via an output stage input node based on the time-varying modulation voltage received via an output stage collector node. The method also includes generating an output stage cancellation current based on the time-varying modulation voltage received via the output stage collector node, thereby suppressing a modulated output stage current leaking from the output stage collector node into the output stage input node.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and become aware of additional aspects thereof after reading the following detailed description of the preferred embodiments and the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] FIG. 1A is a schematic diagram of a conventional transmit circuit that may suffer from degraded adjacent channel leakage ratio (ACLR) performance due to memory distortion caused by a power amplifier circuit in a radio frequency (RF) signal;

[0013] FIG. 1B is a schematic diagram showing the internal structure of an amplifier stage (eg, output stage) of the power amplifier circuit in FIG. 1A ;

[0014] Figure 2 is a schematic diagram of an exemplary power amplifier circuit for eliminating memory distortion configured in accordance with an embodiment of the present disclosure;

[0015] Figure 3 is a schematic diagram of an exemplary power amplifier circuit for eliminating memory distortion configured in accordance with another embodiment of the present disclosure;

[0016] Figure 4A and 4B Provide information about Figure 2 and 3 A schematic diagram of an exemplary illustration of how the capacitive loading of the power amplifier circuit can be further reduced in addition to eliminating memory distortion;

[0017] Figure 5 It can be set Figure 2 and 3 A schematic diagram of an exemplary user element of a power amplifier circuit of; and

[0018] Figure 6 yes Figure 2 and 3Flowchart of an exemplary process by which a power amplifier circuit in may be used to eliminate memory distortion. DETAILED DESCRIPTION

[0019] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments and to illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will appreciate the applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0020] It will be appreciated that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish different elements. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items.

[0021] It should be understood that when an element such as a layer, a region or a substrate is referred to as being "on another element" or "extending onto another element", it may be directly on another element or directly extending onto another element, or there may also be an intermediate element. On the contrary, when an element is referred to as being "directly on another element" or "extending directly onto another element", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, a region or a substrate is referred to as being "above another element" or "extending above another element", it may be directly above another element or directly extending above another element, or there may also be an intermediate element. On the contrary, when an element is referred to as being "directly above another element" or "extending directly above another element", there is no intermediate element. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to another element, or there may be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0022] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0023] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. It should also be understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined herein, the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0025] Embodiments of the present disclosure relate to memory distortion cancellation in a power amplifier circuit. The power amplifier circuit includes one or more amplifier stages, each of which is configured to amplify a radio frequency (RF) signal based on a time-varying modulation voltage received at a corresponding collector node. Notably, each of the amplifier stages may inherently cause a derivative of the time-varying modulation voltage (also referred to as a modulation current) to leak from the corresponding collector node into the corresponding input node, which may produce an undesired remodulation term that may reduce the adjacent channel leakage ratio (ACLR) of the power amplifier circuit. In addition, as a derivative of the time-varying modulation voltage, the undesired remodulation term typically has a memory effect that is difficult to compensate for by, for example, digital predistortion. In an embodiment disclosed herein, a cancellation circuit is provided in the power amplifier circuit for injecting a cancellation current into the corresponding input node to offset at least a portion of the leaked modulation current. By eliminating the leaked modulation current, the undesired modulation term can be suppressed, thereby helping to improve the ACLR of the power amplifier circuit.

[0026] Before discussing the power amplifier circuit according to the present disclosure, Figure 2 To begin, a brief discussion of prior art power amplifier circuits is first provided with reference to FIGS. 1A and 1B to help understand how memory distortion may be formed at the collector node of a power amplifier circuit.

[0027] FIG. 1A is a schematic diagram of an exemplary prior art transmit circuit 10 that may suffer from degraded ACLR performance due to memory distortion caused by a power amplifier circuit 12 in an RF signal 14. The prior art transmit circuit 10 includes a transceiver circuit 16 and a power management integrated circuit (PMIC) 18. The transceiver circuit 16 is configured to generate and provide the RF signal 14 to the power amplifier circuit 12. The transceiver circuit 16 is also configured to generate and provide the RF signal 14 to the power amplifier circuit 12 according to the time-varying power envelope P of the RF signal 14. ENV (t) Generate time-varying target voltage V TGT (t), and the time-varying target voltage V TGT (t) is provided to the PMIC 18. The PMIC 18 is configured to be based on the time-varying target voltage V TGT (t) Generates a time-varying modulation voltage VCC (t), such as envelope tracking (ET) modulation voltage or average power tracking (APT) modulation voltage. It is worth noting that due to the time-varying modulation voltage V CC (t) is based on the time-varying target voltage V TGT (t) generated and time-varying target voltage V TGT (t) is the time-varying power envelope P of the RF signal 14 ENV (t) generates a time-varying modulation voltage V CC (t) and the time-varying power envelope P of the tracking RF signal 14 ENV (t) time-varying voltage envelope V ENV (t) is associated. The PMIC 18 is configured to communicate with the corresponding equivalent inductor impedance L TRACE-PMIC The associated external conductive trace 20 will modulate the time-varying voltage V CC (t) is supplied to the power amplifier circuit 12.

[0028] Herein, the power amplifier circuit 12 is a multi-stage power amplifier including an input stage 22 (denoted as “PA IN ”) and output stage 24 (denoted as “PA OUT ”). The input stage 22 is configured to receive a time-varying modulation voltage V at the input stage collector node 26. CC (t)(also expressed as “V CC-I (t)”), and the output stage 24 is configured to receive the time-varying modulation voltage V at the output stage collector node 28 CC (t)(also expressed as “V CC-O (t)”). The output stage collector node 28 is coupled to the input stage collector node 26 via the internal conductive trace 30. Similar to the external conductive trace 20, the internal conductive trace 30 is also connected to the corresponding equivalent inductive impedance L TRACE-PA Therefore, the time-varying modulation voltage V received at the input stage collector node 26 is CC(t) may be different in phase and / or amplitude from the time-varying modulation voltage V received at the output stage collector node 28 CC (t).

[0029] The input stage 22 is configured to receive the RF signal 14 via the input stage input node 32 and to modulate the RF signal 14 based on the time-varying modulation voltage V received at the input stage collector node 26. CC (t) amplifying the RF signal 14. The output stage 24 is configured to receive the RF signal 14 that has been amplified by the input stage 22 via the output stage input node 34. Therefore, the output stage 24 will be based on the time-varying modulation voltage V received at the output stage collector node 28. CC (t) The RF signal 14 is further amplified.

[0030] The input stage 22 has a corresponding linear parasitic capacitance between the input stage collector node 26 and the input stage input node 32, as represented by the corresponding equivalent capacitor C BC-I Likewise, the output stage 24 has a corresponding linear parasitic capacitance between the output stage collector node 28 and the output stage input node 34, as represented by the corresponding equivalent capacitor C BC-O In this article, the equivalent capacitor C BC-I and C BC-O As discussed in detail in FIG. 1B , the equivalent capacitor C BC-I and / or equivalent capacitor C BC-O is the main factor of memory distortion in the RF signal 14.

[0031] Fig. 1B is a schematic diagram showing the internal structure of the output stage 24 of the power amplifier circuit 12 in Fig. 1A. Common elements between Figs. 1A and 1B are shown with common element numbers and will not be re-described herein.

[0032] The output stage 24 may include a corresponding transistor 36, such as a bipolar junction transistor (BJT) or a complementary metal oxide semiconductor (CMOS) transistor. Taking BJT as an example, the transistor 36 may include a base electrode B, a collector electrode C, and an emitter electrode E. The collector electrode C is coupled to the output stage collector node 28 to receive the time-varying modulation voltage V CC-O (t).

[0033] For example, the time-varying modulation voltage V received at the output stage collector node 28 CC-O (t) may include both linear and nonlinear terms, as represented in the following equation (Equation 1).

[0034] V CC-O (t) = V DC +A×V ENV (t)+B×V ENV (t)2 +C×V ENV (t) 3 +…(Equation 1)

[0035] In the equation (Equation 1), V DC Indicates constant DC voltage, A×V ENV (t) represents a linear term, and B×V ENV (t) 2 +C×V ENV (t) 3 +… represents a nonlinear term. Studies have shown that the time-varying modulation voltage V CC-O (t) is given by the linear term A×V ENV (t) dominates. Therefore, the time-varying modulation voltage V CC-O (t) can be linearly approximated as equation (Equation 2).

[0036] V CC-O (t)≈V DC +A×V ENV (t)(Equation 2)

[0037] When the equivalent capacitor C across the output stage collector node 28 and the output stage input node 34 BC-O Apply a time-varying modulation voltage V CC-O (t), the modulated output current I BC-O (t) is injected from the output stage collector node 28 into the output stage input node 34. As shown in the following equation (Equation 3), the modulated output stage current I BC-O (t) is largely a linear modulated current.

[0038] I CB-O (t)≈C BC-O ×A×dV ENV (t) / dt (Equation 3)

[0039] Modulation output stage current I BC-O (t) The net output impedance R presented at the base electrode B of the output stage 24 bb-O Converted into voltage R bb-O ×I CB-O (t), which is then added to the RF signal 14 at the base electrode B of transistor 36 to produce a distorted base voltage V CB-O (t), as shown in the following equation (Equation 4).

[0040]

[0041] In the equation (Equation 4), K RF represents a dimensionless constant (e.g., gain). The time-varying voltage envelope V ENV(t) and the RF signal 14 is remodulated by even-order (primarily 2nd-order) distortion within the output stage 24 to generate an output stage distortion product, which can be expressed as:

[0042]

[0043] Referring back to FIG. 1A , the specific analysis and issues discussed with respect to output stage 24 in FIG. 1B are equally applicable to input stage 22 . When the equivalent capacitor C across input stage collector node 26 and input stage input node 32 BC-I Apply a time-varying modulation voltage V CC-I (t), the modulation input current I BC-I (t) is injected from the input stage collector node 26 into the input stage input node 32. The modulated input stage current I BC-O (t) The net input stage impedance R presented at the base electrode B of the input stage 22 bb-I Converted into voltage R bb-I ×I CB-I (t), which is then added to the RF signal 14 at the base electrode B of the transistor 36 to produce a distorted base voltage V at the input stage 22 CB-I (t). Time-varying voltage envelope V ENV (t) and the RF signal 14 are remodulated by the high-order distortion within the input stage 22 to generate the input stage distortion product, which can be expressed as:

[0044]

[0045] It is worth noting that as the time-varying voltage envelope V ENV (t), the input-stage and output-stage distortion products inherently have memory, which may be difficult to compensate for by techniques such as isoGain and linear digital pre-distortion (DPD). As a result, the power amplifier circuit 12 may suffer from degraded ACLR performance. Therefore, it is desirable to suppress the input-stage and output-stage distortion products to help improve the ACLR performance of the power amplifier circuit 12.

[0046] in this regard, Figure 2 1A is a schematic diagram of an exemplary power amplifier circuit 38 configured according to an embodiment of the present disclosure for canceling output stage and / or input stage distortion present in the power amplifier circuit 12 of the prior art transmitting circuit 10 of FIG. 1A. According to the embodiments described herein, one or more cancellation circuits may be provided in the power amplifier circuit 38 to effectively suppress output stage and / or input stage distortion within the power amplifier circuit 38. By suppressing the time-varying voltage envelope V at the input of the output stage and / or input stage distortion within the power amplifier circuit 38, ENV (t), can significantly reduce the time-varying voltage envelope V ENVThe memory distortion generated by the remodulation between the RF signal (t) and the transistors in the power amplifier circuit 38 is reduced, and the ACLR performance of the power amplifier circuit 38 is improved (e.g., an ACLR reduction of >6 dB) without the assistance from the associated circuits (e.g., the transceiver and the PMIC). Therefore, the power amplifier circuit 38 can interoperate with transceivers and / or PMICs from different vendors.

[0047] The power amplifier circuit 38 includes an input stage amplifier 40 and an output stage amplifier 42. The input stage amplifier 40 is configured to receive an RF signal 44 via an input stage input node 46. Similar to the RF signal 14 in FIG. 1A, the RF signal 44 also varies with a time-varying power envelope P ENV The input stage amplifier 40 also receives the time-varying modulation voltage V via the input stage collector node 48. CC (t). Compared with the time-varying modulation voltage V in Figure 1A CC (t) Similarly, the received time-varying modulation voltage V CC (t) is also related to the time-varying voltage envelope V ENV For the purpose of differentiation, the time-varying modulation voltage V CC (t) is hereinafter referred to as the time-varying input stage voltage V CC-I (t). Therefore, the input stage amplifier 40 is configured based on the time-varying input stage voltage V CC-I (t) Amplifying the RF signal 44.

[0048] The output stage amplifier 42 is configured to receive the RF signal 44 amplified by the input stage amplifier 40 via the output stage input node 50. The output stage amplifier 42 also receives the time-varying modulation voltage V CC (t). For the purpose of differentiation, the time-varying modulation voltage V CC (t) is hereinafter referred to as the time-varying output stage voltage V CC-O (t). Therefore, the output stage amplifier 42 is configured to be based on the time-varying output stage voltage V CC-O (t) is the RF signal 44 which has been further amplified by the input stage amplifier 40.

[0049] In a non-limiting example, each of the input stage amplifier 40 and the output stage amplifier 42 includes the transistor 36 of FIG. 1B. The input stage amplifier 40 is the same as or functionally equivalent to the input stage 22 of FIG. 1A. Similar to the input stage 22, the input stage amplifier 40 also has a corresponding parasitic capacitance between the input stage collector node 48 and the input stage input node 46, as represented by an equivalent capacitor C of a corresponding d BC-I Indicated by the equivalent capacitor C in Figure 1A BC-ISimilarly, the equivalent capacitor C here BC-I is also a linear capacitor. Therefore, when the equivalent capacitor C BC-I Apply a time-varying input stage voltage V CC-I (t), the modulation input current I BC-I (t) is injected from the input stage collector node 48 into the input stage input node 46. Therefore, the input stage amplifier 40 can produce the same input stage distortion product as the input stage 22 in FIG. 1A

[0050] On the other hand, the output stage amplifier 42 is the same as or functionally equivalent to the output stage 24 in FIG. 1A. Similar to the output stage 24, the output stage amplifier 42 also has a corresponding parasitic capacitance between the output stage collector node 52 and the output stage input node 50, as represented by the corresponding equivalent capacitor C BC-O Indicated by the equivalent capacitor C in Figure 1A BC-O Similarly, the equivalent capacitor C here BC-O is also a linear capacitor. Therefore, the time-varying output stage voltage V CC-O (t) Across the equivalent capacitor C BC-O Applied, modulated output stage current I BC-O (t) is injected from the output stage collector node 52 into the output stage input node 50. Therefore, the output stage amplifier 42 can produce the same output stage distortion product as the output stage 24 in FIG. 1A

[0051] As previously described, input stage distortion products and / or output stage distortion products may cause power amplifier circuit 38 to suffer from degraded ACLR performance. Therefore, in order to help improve the ACLR performance of power amplifier circuit 38, it is necessary to suppress the input stage distortion products and / or output stage distortion products by eliminating the derivative of the baseband signal appearing at the base of input stage amplifier 40 and / or output stage amplifier 42.

[0052] In one embodiment, the power amplifier circuit 38 is configured to suppress output stage distortion products To help improve the ACLR performance of the power amplifier circuit 38. In this regard, the power amplifier circuit 38 is configured to further include an output stage cancellation circuit 54, which is coupled to the output stage collector node 52 and the output stage input node 50. Although the output stage cancellation circuit 54 is shown here as being directly coupled to the output stage collector node 52, the output stage cancellation circuit 54 can also be coupled to the output stage collector node 52 via a low-frequency feeding circuit (e.g., an inductor), which is omitted herein for simplicity. Herein, the output stage cancellation circuit 54 is configured to be based on the time-varying output stage voltage V CC-O (t) to generate the output stage elimination current INEUT-O (t), thereby suppressing the modulated output stage current I from leaking from the output stage collector node 52 to the output stage input node 50 BC-O (t). By suppressing the modulation output current I BC-O (t), which can reduce the output stage distortion product The ACLR performance in the power amplifier circuit 38 is thereby improved.

[0053] In another embodiment, the output stage cancellation circuit 54 may also be coupled to the input stage collector node 48. In this regard, the output stage cancellation circuit 54 may also be configured to be based on the time-varying output stage voltage V CC-O (t) and the time-varying input stage voltage V CC-I (t) Both generate the output stage elimination current I NEUT-O (t). Based on the time-varying input stage voltage V CC-I (t) to further generate the output stage elimination current I NEUT-O (t), the corresponding equivalent inductive impedance L associated with the internal conductive trace 55 between the input stage amplifier 40 and the output stage amplifier 42 can be further solved. TRACE-PA The time-varying input stage voltage V CC-I (t) distortion.

[0054] More specifically, the output stage cancellation circuit 54 is configured to generate an output stage cancellation current I NEUT-O (t), this current is roughly equal to the modulated output stage current I BC-O (t), but in the modulation output current I BC-O (t) flows in the opposite direction. Figure 2 As shown, the modulated output current I BC-O (t) flows from the output stage collector node 52 to the output stage input node 50, and the output stage eliminates the current I NEUT-O (t) flows from the output stage input node 50 to the output stage cancellation circuit 54. Therefore, the output stage cancellation current I NEUT-O (t) The modulation output stage current I can be substantially eliminated at the output stage input node 50. BC-O (t).

[0055] In a non-limiting example, the output stage cancellation circuit 54 may be configured to generate the output stage cancellation current I according to the following equation (Equation 5): NEUT-O (t) as the modulated output stage current IBC-O (t) is a linear function of

[0056] I NEUT-O (t) = M0 × I BC-O (t) (M0≦1) (Equation 5)

[0057] By eliminating the current I NEUT-O (t) and the modulated output current I BC-O (t) added, the output stage distortion product becomes In this regard, when M0 is equal to one (1), the output stage distortion products can be completely canceled. Studies have shown that by suppressing even a portion of the output stage distortion, significant ACLR improvements can be achieved. For example, when M0 is equal to 3 / 4 (0.75), the power amplifier circuit 38 can achieve an ACLR improvement of approximately 12 dB. Therefore, in real-world implementations, it may be possible to meet the desired ACLR target by canceling only a portion of the output stage distortion products. Therefore, the output stage cancellation circuit 54 may not require calibration to generate an accurately matched modulated output stage current I BC-O (t) Output stage elimination current I NEUT-O (t).

[0058] Under certain conditions, such as when transistor 36 in output stage amplifier 42 operates in the linear region, when the time-varying modulation voltage V CC (t) is the average power tracking (APT) modulation voltage, or when the time-varying power envelope P ENV (t) or time-varying voltage envelope V ENV (t) is not present, the output stage cancellation circuit 54 may be subject to instability issues. In this regard, the power amplifier circuit 38 may further include a stabilization circuit 56 coupled between the output stage collector node 52 and the output stage input node 50. The stabilization circuit 56 may be configured to stabilize the current I STAB (t) and the output stage elimination current I NEUT-O (t) is added to help prevent low frequency (e.g., <200MHz) oscillations.

[0059] In a non-limiting example, the stabilization circuit 56 can also help suppress the time-varying power envelope P ENV The negative real impedance in the frequency between the modulation bandwidth and the carrier frequency (t) thus makes it possible to more actively generate the output stage cancellation current I NEUT-O (t) (eg, M0=1). For example, the stabilization circuit 56 may be as simple as a resistor-capacitor (RC) circuit coupled between the output stage collector node 52 and the output stage input node 50 .

[0060] In another embodiment, the power amplifier circuit 38 is configured to suppress input stage distortion products and the output stage distortion product To help improve the ACLR performance of the power amplifier circuit 38. In this regard, Figure 3 is a schematic diagram of an exemplary power amplifier circuit 58 configured in accordance with another embodiment of the present disclosure. Figure 2 and 3 Common elements between the present invention are shown with common element numbers and will not be described again in this article.

[0061] The power amplifier circuit 58 is further configured to include an input stage cancellation circuit 60 coupled between the input stage collector node 48 and the input stage input node 46. Similar to the output stage cancellation circuit 54, the input stage cancellation circuit 60 is configured to be based on the time-varying input stage voltage V CC-I (t) to generate the input stage elimination current I NEUT (I(t), thereby suppressing the modulated input stage current I leaking from the input stage collector node 48 into the input stage input node 46 BC-I (t).

[0062] In a non-limiting example, the input stage cancellation circuit 60 may be configured to generate the input stage cancellation current I according to the following equation (Equation 6): NEUT-I (t) as the modulation input current I BC-I (t) is a linear function of

[0063] I NEUT-I (t) = M1 × I BC-I (t)(M1≦1)(Equation 6)

[0064] By eliminating the current I NEUT-I (t) and the modulation input stage current I BC-I (t) added, the input stage distortion product becomes In this regard, when M1 is equal to one (1), the input stage distortion products can be completely canceled. In addition, by including the input stage cancellation circuit 60 to suppress the input stage distortion products, intermodulation between the input stage distortion products and the output stage distortion products at the output stage amplifier 42 can be prevented, which would cause cascaded high-order memory distortion. Such high-order memory distortion can become significant in ACLR2 (also known as "alternative ACLR") and cause problems.

[0065] Return to reference Figure 2 , with or without Figure 3 Adding output stage cancellation circuit 54 in the absence of input stage cancellation circuit 60 can also help reduce the time-varying voltage envelope V ENV (t) is presented to the time-varying modulation voltage V by the power amplifier circuit 38 at the modulation frequency CC (t) Capacitive load C PA Recall that the power amplifier circuit 12 in FIG. 1A is coupled to the PMIC 18 via the external conductive trace 20, and the external conductive trace 20 is connected to the equivalent inductive impedance L TRACE-PMICSimilarly, when the power amplifier circuit 38 is coupled to a PMIC (not shown), the conductive path between the PMIC and the power amplifier circuit 38 will also have a corresponding equivalent inductive impedance. Therefore, the capacitive load C PA and equivalent inductor impedance can form a time-varying modulation voltage V CC (t) distorted second-order filter. Therefore, when the RF signal 44 is generated with a higher modulation bandwidth (e.g., ≥100 MHz), it is highly desirable to set the capacitive load C PA Minimized to less than one hundred picofarads (<100 pF), the equalization filter (not shown) in the PMIC 18 can effectively compensate for the filtering effect of the second order filter.

[0066] Unfortunately, the capacitive load C of the power amplifier circuit 38 PA Typically between 150-170pF, of which about 90pF is the decoupling capacitor C PA1 or C PA2 The remaining 60-80pF is contributed by the equivalent capacitor C BC-O and / or equivalent capacitor C BC-I The so-called multiplication effect occurs. Therefore, in order to load the capacitive load C PA To reduce it to below 100pF, it will be necessary to minimize the equivalent capacitor C BC-O and / or equivalent capacitor C BC-I The multiplication effect caused by.

[0067] Figure 4A is a diagram showing the output stage amplifier 42 being coupled to the output stage cancellation circuit 54. Figure 2 The equivalent capacitor C of the output stage amplifier 42 including the transistor 36 in FIG. 1B BC-O Schematic diagram of the multiplication effect produced. In contrast, Figure 4B is to show how the output stage cancellation circuit 54 can reduce the Figure 2 The equivalent capacitor C in the output stage amplifier 42 BC-O Schematic diagram of the resulting multiplication effect d. Common elements between Figures 1B, 2, 4A and 4B are shown with common element numbers and will not be re-described herein.

[0068] like Figure 4A As shown, if the output stage elimination circuit 54 is not provided in the power amplifier circuit 38, then the equivalent capacitor C BC-O To the capacitive load C PA The contribution is approximately equal to 50.5*C BC-O In contrast, Figure 4B As shown, by adding the output stage elimination circuit 54 in the power amplifier circuit 38, the equivalent capacitor C BC-OInstead, the capacitive load C PA The contribution is approximately equal to 12.6*C BC-O In this regard, adding the output stage cancellation circuit 54 to the power amplifier circuit 38 can reduce the multiplication effect by a factor of four (4) or even greater (where M0 is high). PA Reduce to less than or equal to 100pF.

[0069] Can be set in user components Figure 2 The power amplifier circuit 38 and Figure 3 The power amplifier circuit 58 is used to achieve the memory distortion elimination according to the embodiment described above. In this regard, Figure 5 It can be set Figure 2 The power amplifier circuit 38 and Figure 3 Schematic diagram of an exemplary user element 100 of the power amplifier circuit 58.

[0070] Herein, user element 100 can be any type of user element, such as a mobile terminal, smart watch, tablet computer, computer, navigation device, access point and similar wireless communication device supporting wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth and near field communication. User element 100 will generally include control system 102, baseband processor 104, transmitting circuit system 106, receiving circuit system 108, antenna switch circuit system 110, multiple antennas 112 and user interface circuit system 114. In a non-limiting example, for example, control system 102 can be a field programmable gate array (FPGA). In this regard, control system 102 can include at least a microprocessor, an embedded memory circuit and a communication bus interface. Receive circuit system 108 receives radio frequency signals from one or more base stations via antenna 112 and through antenna switch circuit system 110. Low noise amplifier and filter cooperate to amplify and eliminate broadband interference from received signals for processing. Downconversion and digitization circuitry (not shown) then downconverts the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0071] The baseband processor 104 processes the digitized received signal to extract the information or data bits transmitted in the received signal. Such processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 104 is typically implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0072] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, and encodes the digitized data for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at a desired transmit frequency or frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to an antenna 112 via an antenna switch circuitry 110. Multiple antennas 112 and duplicate transmit circuitry 106 and receive circuitry 108 may provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0073] In an embodiment, Figure 2 The power amplifier circuit 38 and Figure 3 The power amplifier circuit 58 can be configured to eliminate memory distortion based on a process. In this regard, Figure 6 yes Figure 2 The power amplifier circuit 38 and Figure 3 Flowchart of an exemplary process 200 by which the power amplifier circuit 58 may be used to eliminate memory distortion.

[0074] Herein, the input stage amplifier 40 is configured to be based on a time-varying modulation voltage V received via the input stage collector node 48. CC (t) amplifies the RF signal 44 received via the input stage input node 46 (step 202). The output stage amplifier 42 is configured to receive the time-varying modulation voltage V via the output stage collector node 52 based on the time-varying modulation voltage V CC (t) to further amplify the RF signal 44 that has been amplified by the input stage amplifier 40 and received via the output stage input node 50 (step 204). The output stage cancellation circuit 54 is configured to receive the time-varying modulation voltage V via the output stage collector node 52 based on the time-varying modulation voltage V CC(t) To generate the output stage elimination current I NEUT-O (t), thereby suppressing the modulated output stage current I from leaking from the output stage collector node 52 to the output stage input node 50 BC-O (t)(Step 206).

[0075] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims

1. A power amplifier circuit (38, 58), comprising: An input stage amplifier (40) configured to: The input stage receives a radio frequency (RF) signal (44) via an input stage input node (46) and receives a time-varying modulation voltage (V CC (t)); and Based on the time-varying modulation voltage (V CC (t)), amplifying the RF signal (44); an output stage amplifier (42) coupled to the input stage amplifier (40) and configured to: The RF signal (44) amplified by the input stage amplifier (40) is received via an output stage input node (50), and the time-varying modulation voltage (V CC (t)); and Based on the time-varying modulation voltage (V CC (t)), further amplifying the RF signal (44); and An output stage cancellation circuit (54) is coupled to the output stage collector node (52) and the output stage input node (50), the output stage cancellation circuit (54) being configured to generate a time-varying modulation voltage (V CC (t)) to generate the output stage cancellation current (I NEUT-O (t)), thereby suppressing the modulated output stage current (I BC-O (t)).

2. The power amplifier circuit (38, 58) of claim 1, further comprising a stabilization circuit (56) coupled between the output stage collector node (52) and the output stage input node (50), the stabilization circuit (56) being configured to provide a stabilization current (I STAB (t)) and the output stage elimination current (I NEUT-O (t)) are added.

3. The power amplifier circuit of claim 1 , wherein the output stage cancellation circuit is also coupled to the input stage collector node and is configured to generate the output stage cancellation current based on the time-varying modulation voltage received via the output stage collector node and the time-varying modulation voltage received via the input stage collector node.

4. The power amplifier circuit of claim 3, further comprising a stabilization circuit coupled between the output stage collector node and the output stage input node, the stabilization circuit being configured to add a stabilization current to the output stage cancellation current.

5. The power amplifier circuit of claim 1, wherein the modulated output stage current is proportionally related to a linear parasitic capacitance between the output stage collector node and the output stage input node.

6. The power amplifier circuit according to claim 1, wherein: The time-varying modulation voltage received at the output stage collector node includes a linear term and a plurality of nonlinear terms; and The output stage cancellation circuit is further configured to generate the output stage cancellation current based on the linear term of the time-varying modulation voltage received at the output stage collector node.

7. The power amplifier circuit (58) of claim 1, further comprising an input stage cancellation circuit (60) coupled between the input stage collector node (48) and the input stage input node (46), the input stage cancellation circuit (60) being configured to provide a time-varying modulation voltage (V CC (t)) to generate the input stage cancellation current (I NEUT-I (t)), thereby suppressing the modulated input stage current (I BC-I (t)).

8. The power amplifier circuit of claim 7, further comprising a stabilization circuit coupled between the output stage collector node and the output stage input node, the stabilization circuit being configured to add a stabilization current to the output stage cancellation current.

9. The power amplifier circuit of claim 7, wherein the modulated input stage current is proportionally related to a linear parasitic capacitance between the input stage collector node and the input stage input node.

10. The power amplifier circuit according to claim 7, wherein: The time-varying modulation voltage received at the input stage collector node includes a linear term and a plurality of nonlinear terms; and The input stage cancellation circuit is further configured to generate the input stage cancellation current based on the linear term of the time-varying modulation voltage received at the input stage collector node.

11. A method for eliminating memory distortion in a power amplifier circuit (38, 58), comprising: Based on a time-varying modulation voltage (V CC (t)), amplifying a radio frequency RF signal (44) received via an input stage input node (46); Based on the time-varying modulation voltage (V CC (t)), further amplifying the RF signal (44) received via the output stage input node (50); and Based on the time-varying modulation voltage (V CC (t)), generating the output stage elimination current (I NEUT-O (t)), thereby suppressing the modulated output stage current (I BC-O (t)).

12. The method according to claim 11 further comprises: STAB (t)) and the output stage elimination current (I NEUT-O (t)) are added.

13. The method of claim 11, further comprising generating the output stage cancellation current based on the time-varying modulation voltage received via the output stage collector node and the time-varying modulation voltage received via the input stage collector node.

14. The method of claim 13, further comprising adding a stabilization current to the output stage cancellation current.

15. The method of claim 11, further comprising generating the modulated output stage current to be proportionally related to a linear parasitic capacitance between the output stage collector node and the output stage input node.

16. The method according to claim 11, further comprising: receiving the time-varying modulation voltage including a linear term and a plurality of nonlinear terms at the output stage collector node; as well as The output stage cancellation current is generated based on the linear term of the time varying modulation voltage received at the output stage collector node.

17. The method of claim 11 further comprising providing a time-varying modulation voltage (V CC (t)) to generate an input stage cancellation current (60) to suppress the modulated input stage current (I) leaking from the input stage collector node (48) to the input stage input node (46) BC-I (t)).

18. The method of claim 17, further comprising adding a stabilization current to the output stage cancellation current.

19. The method of claim 17, further comprising generating the modulated input stage current to be proportionally related to a linear parasitic capacitance between the input stage collector node and the input stage input node.

20. The method of claim 17, further comprising: receiving the time-varying modulation voltage including a linear term and a plurality of nonlinear terms at the input stage collector node; as well as The input stage cancellation current is generated based on the linear term of the time varying modulation voltage received at the input stage collector node.

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