Lanthanum nitride as DRAM molybdenum liner

Abstract

A method for a DRAM device with buried word lines is described. The method includes forming a metal nitride layer including lanthanum nitride (LaN) and a molybdenum conductor layer in a feature on a substrate. The method includes depositing a molybdenum conductor layer on a metal nitride layer by atomic layer deposition (ALD).

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor devices and semiconductor device fabrication. More specifically, embodiments of the present disclosure relate to methods of utilizing lanthanum nitride as a liner for DRAM molybdenum applications. Background Art

[0002] Electronic devices such as personal computers, workstations, computer servers, mainframes, and other computer-related equipment (such as printers, scanners, and hard drives) use memory devices that provide large amounts of data storage capabilities while incurring low power consumption. There are two main types of random access memory cells, dynamic and static, that are well suited for use in electronic devices. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than a very short period of time. Static random access memory (SRAM) is so named because it does not require periodic refreshing.

[0003] DRAM memory circuits are manufactured by replicating millions of identical circuit elements (known as DRAM cells) on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary number) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

[0004] The manufacture of a DRAM cell includes the manufacture of a transistor, a capacitor, and three contacts, one each to a bit line, a word line, and a reference voltage. DRAM manufacturing is a highly competitive industry. There is a constant pressure to reduce the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 megabits. Limitations to reducing cell size include the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with non-array devices. The formation of a low resistance contact between the active area and the bottom electrode of a 3D DRAM is essential to the performance of the device.

[0005] In DRAM devices, one of the main goals is to increase the storage per unit space, which results in an increase in the vertical size or stack height of the DRAM device. Compared with conventional cell DRAM, vertical cell DRAM has the advantage of reducing the chip area by about one-third. Therefore, there is a need for a 3D DRAM device and a manufacturing method that does not cause a floating body access transistor and does not increase the area of ​​the cell. Summary of the invention

[0006] One or more embodiments of the present disclosure relate to a method for forming a buried word line. In one or more embodiments, the method includes: depositing a metal nitride layer on a substrate, the metal nitride layer including lanthanum nitride; and depositing a molybdenum conductor layer on the metal nitride layer by an atomic layer deposition (ALD) process.

[0007] In one or more embodiments, a method of forming a buried word line includes depositing a metal nitride layer on a substrate, the metal nitride layer including lanthanum nitride; and depositing a molybdenum conductor layer on the metal nitride layer by an atomic layer deposition (ALD) process. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more particular description of the present disclosure, briefly summarized above, may be obtained by reference to the embodiments shown in the accompanying drawings, some of which are embodiments thereof, in which manner the above-mentioned features of the present disclosure may be understood in detail. It will be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of the scope of the present disclosure, as the present disclosure may admit to other equally effective embodiments.

[0009] Figure 1 A process flow chart showing a method according to one or more embodiments of the present disclosure;

[0010] Figures 2A-2D shows a cross-sectional view of an apparatus according to one or more embodiments;

[0011] Figures 3A-3C shows a cross-sectional view of an apparatus according to one or more embodiments;

[0012] Figures 4A-4D showing a cross-sectional view of an apparatus according to one or more embodiments; and

[0013] Figures 5A-5C A cross-sectional view of a device according to one or more embodiments is shown.

[0014] For ease of understanding, the same reference numerals have been used as much as possible to refer to the same elements that are common to the drawings. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further clarification. DETAILED DESCRIPTION

[0015] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the architecture or processing steps described in the following description. The present disclosure is capable of other embodiments and can be practiced or implemented in various ways.

[0016] As used in this specification and the appended claims, the term "substrate" refers to a surface, or a portion of a surface, on which a process is performed. It will also be understood by those skilled in the art that reference to a substrate may also refer to only a portion of such substrate, unless the context clearly indicates otherwise. In addition, reference to a deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0017] When "substrate" is used herein, it refers to any substrate or material surface formed on a substrate on which film processing is performed during the manufacturing process. For example, depending on the application, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material, such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to film processing directly on the substrate surface itself, in the present disclosure, any film processing step disclosed may also be performed on an underlying layer formed on the substrate, as described in more detail later, and the term "substrate surface" is intended to include such underlying layers as indicated by the context.

[0018] According to one or more embodiments, the term "on" with respect to a film or film layer includes a film or layer directly on a surface (e.g., a substrate surface) and one or more underlying layers between the film or layer and the surface (e.g., a substrate surface). Therefore, in one or more embodiments, the phrase "on a substrate surface" is intended to include one or more underlying layers. In other embodiments, the phrase "directly on..." refers to a film or layer in contact with a surface (e.g., a substrate surface) without an intervening layer. Therefore, the phrase "a layer directly on a substrate surface" refers to a layer in direct contact with the substrate surface without a layer in between.

[0019] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactant gas," and the like may be used interchangeably to refer to any gaseous species that may react with a substrate surface.

[0020] As used herein, "atomic layer deposition" or "cyclic deposition" refers to sequential exposure to two or more reactive compounds to deposit a layer of material on a substrate surface. A substrate or a portion of a substrate surface is separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be exposed to the substrate sequentially. In a spatial ALD process, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to two or more reactive compounds, so that any given point on the substrate is not substantially simultaneously exposed to more than one reactive compound. As used in this specification and the appended claims, as will be understood by those skilled in the art, the term "substantially" used in this regard means that there is a possibility that a small portion of the substrate will be exposed to multiple reactive gases simultaneously due to diffusion, and the simultaneous exposure is not intentional.

[0021] In one aspect of a time-domain ALD process, a first reactant gas (i.e., a first precursor or compound A, e.g., an aluminum precursor) is pulsed into a reaction zone followed by a first time delay. Next, a second precursor or compound B (e.g., an oxidant) is pulsed into the reaction zone followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the process chamber to purge the reaction zone or otherwise remove any residual reactant compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously during the entire deposition process such that only the purge gas flows during the time delay between pulses of the reactant compounds. The reactant compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either scenario, the pulsed compound A, purge gas, compound B, and purge gas of the ALD process is a cycle. The cycle may start with either compound A or compound B and continue in the corresponding order of the cycle until a film having a desired thickness is obtained.

[0022] In an embodiment of a spatial ALD process, a first reactant gas and a second reactant gas (e.g., nitrogen) are delivered to the reaction zone simultaneously, but are separated by an inert gas curtain and / or a vacuum curtain. The substrate moves relative to the gas delivery device so that any given point on the substrate is exposed to the first reactant gas and the second reactant gas.

[0023] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reactants simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to co-flow of precursors or overlap for most exposures of the precursors.

[0024] As used herein throughout the specification, "substantially simultaneously" means that the period during which the first reactant compound is exposed substantially overlaps with the period during which the second reactant compound is exposed.

[0025] As used herein, the term "cleaning" includes any suitable cleaning process that removes unreacted precursors, reaction products, and byproducts from a processing area. Suitable cleaning processes include moving the substrate through a gas curtain to a portion or section of a processing area that is free of reactants or substantially free of reactants. In one or more embodiments, cleaning the processing chamber includes applying a vacuum. In some embodiments, cleaning the processing area includes flowing a cleaning gas over the substrate. In some embodiments, the cleaning process includes flowing an inert gas. In one or more embodiments, the cleaning gas is selected from one or more of nitrogen (N2), helium (He), and argon (Ar). In some embodiments, purging the substrate surface or reaction chamber may occur for a duration ranging from 0.2 seconds to 30 seconds, from 0.2 seconds to 10 seconds, from 0.2 seconds to 5 seconds, from 0.5 seconds to 30 seconds, from 0.5 seconds to 10 seconds, from 0.5 seconds to 5 seconds, from 1 second to 30 seconds, from 1 second to 10 seconds, from 1 second to 5 seconds, from 5 seconds to 30 seconds, from 5 seconds to 10 seconds, or from 10 seconds to 30 seconds.

[0026] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores a data bit by storing a charge packet (i.e., binary 1) or no charge (i.e., binary 0) on a capacitor. Charge is gated onto the capacitor via an access transistor and sensed by turning on the same transistor and examining the voltage perturbation produced by the charge packet on the interconnect line dumped on the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor. A DRAM device is formed of an array of DRAM cells. The rows on the access transistors are linked by word lines, and the transistor inputs / outputs are linked by bit lines. Historically, DRAM capacitors have evolved from planar polysilicon-oxide-substrate plate capacitors to 3D structures, which have differentiated into "stacked" capacitors with both plates on the substrate, and "trench" capacitors that use etched cavities in the substrate as common plates.

[0027] Traditionally, DRAM cells have a recessed high work function metal structure in a buried word line structure. In a DRAM device, the bit line is formed in a metal layer located above the substrate, while the word line is formed at a polysilicon gate layer at the surface of the substrate. In a buried word line (bWL) device, the word line is buried below the surface of a semiconductor substrate that uses metal as a gate electrode. Current DRAM buried word line (bWL) processing involves a titanium nitride (TiN) and tungsten (W) stack or a molybdenum (Mo) stack as a liner. The stack may have high resistivity, high effective work function (eWF), and poor equivalent oxide thickness (EOT) / interface trap density (DiT). Therefore, embodiments of the present disclosure advantageously provide an alternative liner material, lanthanum nitride (LaN), for a molybdenum (Mo) stack in a DRAM buried word line (bWL) on a substrate, which reduces resistance in a DRAM device.

[0028] In one or more embodiments, the resistance (µΩ-cm) for a buried word line having a total thickness of 100 Å is measured. In one or more embodiments, the buried word line has a resistance less than or equal to 40 µΩ-cm, less than or equal to 30 µΩ-cm, less than or equal to 25 µΩ-cm, or less than or equal to 20 µΩ-cm, or less than or equal to 15 µΩ-cm at a total thickness of 100 Å. In some embodiments, the buried word line has a resistance less than or equal to 20 µΩ-cm at a total thickness of 100 Å. In one or more embodiments, the buried word line formed by method 100 has a resistance in a range from 50 µΩ-cm to 5 µΩ-cm, from 40 µΩ-cm to 10 µΩ-cm, from 30 µΩ-cm to 10 µΩ-cm, from 25 µΩ-cm to 10 µΩ-cm, from 20 µΩ-cm to 10 µΩ-cm at a total thickness of 100 Å.

[0029] Embodiments of the present disclosure are illustrated by way of drawings showing devices (e.g., transistors, memory devices, and the like) and processes for forming the devices according to one or more embodiments of the present disclosure. The processes shown are merely illustrative of possible uses for the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0030] One or more embodiments of the present disclosure are described with reference to the accompanying drawings. Figure 1 A process flow diagram showing a method according to one or more embodiments of the present disclosure. Figure 2A 3D are cross-sectional diagrams illustrating memory device 100 at various stages of processing to form a buried word line (bWL) according to one or more embodiments.

[0031] Reference Figure 1, one or more embodiments of the present disclosure relate to a method 10 of forming a memory device (e.g., a buried word line (bWL)). At operation 12, a substrate is provided. At operation 14, a metal nitride layer including lanthanum nitride is formed on the substrate. At operation 16, a second metal nitride layer is optionally formed on the metal nitride layer. At operation 18, a molybdenum conductor layer is formed on the metal nitride layer.

[0032] Reference Figures 2A to 3C , the substrate 102 is provided for processing. As used herein, the term "providing" means placing a substrate into a location or environment for further processing.

[0033] In one or more embodiments, the substrate 102 may be any suitable substrate material. In one or more embodiments, the substrate 102 includes one or more of silicon oxynitride (SiON), silicon oxide (SiOx), or a high-k dielectric material. Although the term "silicon oxide" may be used to describe the substrate 102, those skilled in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" may be used to describe a material having silicon and oxygen atoms in any suitable stoichiometric ratio. The same is true for other materials listed in this specification, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, and the like. Although a few examples of materials that may form the substrate 102 are described herein, any material that may serve as the basis for passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be built on it falls within the spirit and scope of the present disclosure.

[0034] In one or more embodiments, the substrate 102 may have any suitable thickness known to those skilled in the art. In some embodiments, the substrate 102 has a thickness in the range of from 20 Å to 100 Å, including in the range of from 30 Å to 75 Å, including in the range of from 40 Å to 60 Å.

[0035] In one or more embodiments, Figure 2B and Figure 3B As shown in FIG. 1 , a metal nitride layer 104 is formed on a surface of a substrate 102. The metal nitride layer 104 may include any suitable material known to those skilled in the art. In one or more embodiments, the metal nitride layer 104 includes lanthanum nitride (LaN).

[0036] The metal nitride layer 104 may have any suitable thickness. In one or more embodiments, the metal nitride layer 104 has a thickness of less than 20 Å. In one or more embodiments, the metal nitride layer 104 has a thickness in a range from about 1 Å to less than about 20 Å, including in a range from 5 Å to 20 Å, including in a range from 5 Å to 15 Å, including in a range from 10 Å to 20 Å, and including in a range from 10 Å to 15 Å. In one or more embodiments, the metal nitride layer 104 is formed to include lanthanum nitride (LaN) and has a thickness in a range from about 10 Å to about 15 Å.

[0037] In one or more embodiments, referring to Figure 2C , the second metal nitride layer 106 is optionally formed on the surface of the metal nitride layer 104. The second metal nitride layer 106 may include any suitable material known to those skilled in the art. In one or more embodiments, the second metal nitride layer 106 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), yttrium nitride (YN), zirconium nitride (ZrN), hafnium nitride (HfN), and barium nitride (BaN). In one or more specific embodiments, the second metal nitride layer 106 includes titanium nitride (TiN). It should be noted that FIG. 3A to FIG. 3C An alternative embodiment is shown in which the second metal nitride layer 106 is not present and only the first metal nitride layer 104 is present on the substrate 102 surface.

[0038] The second metal nitride layer 106 may have any suitable thickness. In one or more embodiments, the second metal nitride layer 106 has a thickness in the range of about 0.1 nm to about 10 nm, including in the range of from 5 nm to 8 nm, including in the range of from 1 nm to 3 nm, including in the range of from 1 nm to 2 nm. In one or more embodiments, the second metal nitride layer 106 is formed to include titanium nitride (TiN) and has a thickness in the range of about 1 nm to about 2 nm.

[0039] In one or more embodiments, the first metal nitride layer 104 and the second metal nitride layer 106 have a combined thickness of about 30 Å, including a combined thickness in a range from 15 Å to about 30 Å.

[0040] In one or more embodiments, the molybdenum conductor 108 is formed by atomic layer deposition. The atomic layer deposition may be a thermal process. Figure 2D , the device 100 is exposed to a molybdenum precursor to deposit a molybdenum conductor layer 108 on the second metal nitride layer 106. Figure 3C, the device 100 is exposed to a molybdenum precursor to deposit a molybdenum conductor layer 108 on the metal nitride layer 104. The molybdenum precursor can be any suitable molybdenum-containing compound that can react with (i.e., adsorb or chemisorb onto) the metal nitride layers 104, 106 to leave a molybdenum-containing species on the surface.

[0041] In one or more embodiments, the platinum precursor includes any suitable precursor known to those skilled in the art. The platinum precursor of one or more embodiments is volatile and thermally stable, and is therefore suitable for vapor deposition. In some embodiments, the platinum precursor includes a platinum halide. As used herein, the term "halide" refers to a binary phase, a portion of which is a halogen atom and the other portion is an element or free radical with a lower electronegativity than this halogen to form a fluoride, chloride, bromide, iodide, or astatide compound. Halide ions are halogen atoms with a negative charge. As known to those skilled in the art, halide anions include fluoride (F-), chloride (Cl-), bromide (Br-), iodide (I-), and astatide (At-). Therefore, as used herein, the term "platinum halide" refers to any coordination complex of platinum with one or more halogens or halide ligands. The term platinum halide includes a platinum mixed halide having at least two different halide atoms.

[0042] In one or more embodiments, the molybdenum halide is selected from one or more of molybdenum chloride, molybdenum pentachloride, molybdenum bromide, molybdenum iodide, molybdenum bromochloride, molybdenum bromoiodide, molybdenum chlorobromide, molybdenum chloroiodide, molybdenum iodobromide, and molybdenum iodine chloride.

[0043] In some embodiments, the molybdenum precursor includes a molybdenum oxyhalide species. In some embodiments, the molybdenum oxyhalide species includes one or more of molybdenum oxytetrachloride (MoCl4O), molybdenum oxytetrabromide (MoBr4O), molybdenum oxytetraiodide (MoI4O), molybdenum dioxide dibromide (MoO2Br2), molybdenum dioxide dichloride (MoCl2O2), and / or molybdenum dioxide diiodide (MoI2O2).

[0044] In one or more specific embodiments, the molybdenum precursor includes one or more of molybdenum chloride (MoCl5), molybdenum fluoride (MoF6), molybdenum iodide (MoI6), molybdenum bromide (MoBr3), molybdenum hexacarbonyl (Mo(CO)6), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxychloride (MoOCl4), tetrakis(dimethylamino)molybdenum(IV), and bis(tert-butylimino)-bis(dimethylamino)molybdenum.

[0045] In some embodiments, the metal nitride layers 104, 106 are exposed to a molybdenum precursor at a temperature ranging from 350 ºC to 550 ºC, from 400 ºC to 550 ºC, from 450 ºC to 550 ºC, 500 ºC to 550 ºC, from 350 ºC to 500 ºC, from 400 ºC to 500 ºC, from 450 ºC to 500 ºC, from 350 ºC to 450 ºC, from 400 ºC to 450 ºC, or from 350 ºC to 400 ºC.

[0046] In some embodiments, the metal nitride layers 104, 106 are exposed to the molybdenum precursor for a time period ranging from 0.25 seconds to 20 minutes, from 10 seconds to 20 minutes, from 1 minute to 20 minutes, from 5 minutes to 20 minutes, from 10 minutes to 20 minutes, from 0.25 seconds to 10 minutes, from 10 seconds to 10 minutes, from 1 minute to 10 minutes, from 5 minutes to 10 minutes, from 0.25 seconds to 5 minutes, from 10 seconds to 5 minutes, from 1 minute to 5 minutes, from 0.25 seconds to 1 minute, or from 10 seconds to 1 minute.

[0047] In some embodiments, the metal nitride layers 104, 106 are exposed to the molybdenum precursor at a dose ranging from 50 sccm to 700 sccm, from 100 sccm to 700 sccm, from 300 sccm to 700 sccm, from 500 sccm to 700 sccm, from 50 sccm to 500 sccm, from 100 sccm to 500 sccm, from 300 sccm to 500 sccm, from 50 sccm to 300 sccm, from 100 sccm to 300 sccm, or from 50 sccm to 100 sccm.

[0048] In some embodiments, the metal nitride layers 104 , 106 are exposed to a molybdenum precursor at a pressure ranging from 5 Torr to 50 Torr, from 10 Torr to 50 Torr, from 25 Torr to 50 Torr, from 5 Torr to 25 Torr, from 10 Torr to 25 Torr, or from 5 Torr to 10 Torr.

[0049] In some embodiments, the formed platinum conductor layer 108 includes elemental molybdenum. In some embodiments, the platinum conductor layer 108 consists essentially of platinum. As used in this manner, the term "consisting essentially of platinum" means that the content of platinum in the film is greater than or equal to about 80%, 85%, 90%, 95%, 98%, 99%, or 99.5% molybdenum in atomic percentage. The composition of the platinum conductor layer 108 is measured with reference to the bulk portion of the platinum conductor layer 108, excluding the interface region where diffusion of elements from adjacent films can occur.

[0050] Reference Figure 2D Figure 3C In some embodiments, the thickness of the platinum conductor layer 108 can be any suitable thickness. In some embodiments, the platinum conductor layer 108 has a thickness in a range from 1 nm to 50 nm, from 5 nm to 50 nm, from 10 nm to 50 nm, from 25 nm to 50 nm, from 1 nm to 25 nm, from 5 nm to 25 nm, from 10 nm to 25 nm, from 1 nm to 10 nm, from 5 nm to 10 nm, or from 1 nm to 5 nm.

[0051] Reference Figure 1 and FIG. 4A to FIG. 5C , one or more embodiments of the present disclosure relate to a method 10 of forming a memory device 200 (eg, a buried word line (bWL)).

[0052] Reference FIG. 3A to FIG. 5C In one or more embodiments, a substrate 202 is provided with a plurality of grooves 210 therein. The grooves 210 form a recessed channel. The grooves have a bottom 203 and at least one sidewall 207. The plurality of grooves 210 may be formed to have a width in the range of about 10 to about 100 nm, including but not limited to about 10 nm to about 80 nm, about 10 nm to about 70 nm, about 10 nm to about 60 nm, about 10 nm to about 50 nm, or about 10 nm to about 40 nm. As will be appreciated by those skilled in the art, the width of the plurality of grooves 210 is defined by a distance W1 from one sidewall 207 to another sidewall 207. The plurality of grooves 210 may be formed to have a depth in the range of about 120 nm to about 250 nm, including but not limited to about 120 nm to about 150 nm, about 150 nm to about 200 nm, about 200 nm to about 250 nm, about 120 nm to about 200 nm, or about 150 nm to about 250 nm. As will be appreciated by those skilled in the art, the depth of the plurality of trenches 210 is defined by a distance D1 from the substrate surface 205 to the bottom 203 of the plurality of trenches 210 .

[0053] One or more embodiments of the present disclosure relate to methods of depositing films in high aspect ratio features. High aspect ratio features are trenches, vias, or pillars having a height:width ratio greater than or equal to about 10, 20, or 50, or greater. In some embodiments, the film is conformally deposited on / in the high aspect ratio feature. As used in this manner, the thickness of the conformal film near the top of the feature is in the range of about 80-120% of the thickness at the bottom of the feature.

[0054] In order to form the plurality of trenches 210, a buffer insulating layer (e.g., a silicon oxide layer, not shown) may be formed on the substrate surface 205, and / or a hard mask layer (e.g., a nitride layer, not shown) may be formed. These techniques are well known to those skilled in the art and are therefore not described.

[0055] Reference Figure 4B and Figure 5B In some embodiments, a metal nitride layer 204 is formed on the substrate 202. In one or more embodiments, the metal nitride layer 204 includes any suitable metal nitride. In one or more embodiments, the metal nitride layer 204 includes lanthanum nitride (LaN).

[0056] The metal nitride layer 204 may have any suitable thickness. In one or more embodiments, the metal nitride layer 204 has a thickness of less than 20 Å. In one or more embodiments, the metal nitride layer 204 has a thickness in a range from about 1 Å to less than about 20 Å, including in a range from 5 Å to 20 Å, including in a range from 5 Å to 15 Å, including in a range from 10 Å to 20 Å, and including in a range from 10 Å to 15 Å. In one or more embodiments, the metal nitride layer 204 is formed to include lanthanum nitride (LaN) and has a thickness in a range from about 10 Å to about 15 Å.

[0057] In one or more embodiments, referring to Figure 4C , a second metal nitride liner 206 is optionally formed on the surface of the metal nitride layer 204. The second metal nitride layer 206 may include any suitable material known to those skilled in the art. In one or more embodiments, the second metal nitride layer 206 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), yttrium nitride (YN), zirconium nitride (ZrN), hafnium nitride (HfN), and barium nitride (BaN). In one or more specific embodiments, the second metal nitride layer 206 includes titanium nitride (TiN). It should be noted that FIG. 5A to FIG. 5C An alternative embodiment is shown in which the second metal nitride layer 206 is not present and only the first metal nitride layer 204 is present on the substrate 202 surface.

[0058] The second metal nitride layer 206 may have any suitable thickness. In one or more embodiments, the second metal nitride layer 206 has a thickness in the range of about 0.1 nm to about 5 nm, including in the range of from 1 nm to 3 nm, including in the range of from 1 nm to 2 nm. In one or more embodiments, the second metal nitride layer 206 is formed to include titanium nitride (TiN) and has a thickness in the range of about 1 nm to about 2 nm.

[0059] In one or more embodiments, the molybdenum conductor 208 is formed by atomic layer deposition. The atomic layer deposition may be a thermal process. Figure 4D , a process is performed to deposit a molybdenum conductor layer 204 on the substrate 202 (substrate surface). The deposition process may include one or more operations to form the molybdenum conductor layer 204 on the substrate 202. In some embodiments, the deposition process is selective for deposition on the metal nitride layer 204. Figure 5C , a process is performed to deposit a molybdenum conductor layer 204 on the substrate 202 (substrate surface). The deposition process may include one or more operations to form the molybdenum conductor layer 204 on the substrate 202. In some embodiments, the deposition process is selective for deposition on the second metal nitride layer 206.

[0060] The molybdenum precursor can be any suitable molybdenum-containing compound that can react with (i.e., adsorb or chemisorb onto) the metal nitride layers 204, 206 to leave a molybdenum-containing species on the surface. The atomic layer deposition process of some embodiments includes sequential exposure to a precursor and a reactant. The substrate 202 (or substrate surface) is optionally exposed to the reactant. In some embodiments, the reactant includes a reducing agent. The reducing agent can be any suitable compound known to those skilled in the art. In some embodiments, the reducing agent includes hydrogen (H2).

[0061] In one or more embodiments, the platinum precursor includes any suitable precursor known to those skilled in the art. The platinum precursor of one or more embodiments is volatile and thermally stable, and is therefore suitable for vapor deposition. In some embodiments, the platinum precursor includes a platinum halide. As used herein, the term "halide" refers to a binary phase, a portion of which is a halogen atom and the other portion is an element or free radical with a lower electronegativity than this halogen to form a fluoride, chloride, bromide, iodide, or astatide compound. Halide ions are halogen atoms with a negative charge. As known to those skilled in the art, halide anions include fluoride (F-), chloride (Cl-), bromide (Br-), iodide (I-), and astatide (At-). Therefore, as used herein, the term "platinum halide" refers to any coordination complex of platinum with one or more halogens or halide ligands. The term platinum halide includes a platinum mixed halide having at least two different halide atoms.

[0062] In one or more embodiments, the molybdenum halide is selected from one or more of molybdenum chloride, molybdenum pentachloride, molybdenum bromide, molybdenum iodide, molybdenum bromochloride, molybdenum bromoiodide, molybdenum chlorobromide, molybdenum chloroiodide, molybdenum iodobromide, and molybdenum iodine chloride.

[0063] In some embodiments, the molybdenum precursor includes a molybdenum oxyhalide species. In some embodiments, the molybdenum oxyhalide species includes one or more of molybdenum oxytetrachloride (MoCl4O), molybdenum oxytetrabromide (MoBr4O), molybdenum oxytetraiodide (MoI4O), molybdenum dioxide dibromide (MoO2Br2), molybdenum dioxide dichloride (MoCl2O2), and / or molybdenum dioxide diiodide (MoI2O2).

[0064] In one or more specific embodiments, the molybdenum precursor includes one or more of molybdenum chloride (MoCl5), molybdenum fluoride (MoF6), molybdenum iodide (MoI6), molybdenum bromide (MoBr3), molybdenum hexacarbonyl (Mo(CO)6), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxychloride (MoOCl4), tetrakis(dimethylamino)molybdenum(IV), and bis(tert-butylimino)-bis(dimethylamino)molybdenum.

[0065] In some embodiments, the metal nitride layers 204, 206 are exposed to a molybdenum precursor at a temperature ranging from 350 ºC to 550 ºC, from 400 ºC to 550 ºC, from 450 ºC to 550 ºC, 500 ºC to 550 ºC, from 350 ºC to 500 ºC, from 400 ºC to 500 ºC, from 450 ºC to 500 ºC, from 350 ºC to 450 ºC, from 400 ºC to 450 ºC, or from 350 ºC to 400 ºC.

[0066] In some embodiments, the metal nitride layers 204, 206 are exposed to the molybdenum precursor for a time period ranging from 0.25 seconds to 20 minutes, from 10 seconds to 20 minutes, from 1 minute to 20 minutes, from 5 minutes to 20 minutes, from 10 minutes to 20 minutes, from 0.25 seconds to 10 minutes, from 10 seconds to 10 minutes, from 1 minute to 10 minutes, from 5 minutes to 10 minutes, from 0.25 seconds to 5 minutes, from 10 seconds to 5 minutes, from 1 minute to 5 minutes, from 0.25 seconds to 1 minute, or from 10 seconds to 1 minute.

[0067] In some embodiments, the metal nitride layers 204, 206 are exposed to the molybdenum precursor at a dose ranging from 50 sccm to 700 sccm, from 100 sccm to 700 sccm, from 300 sccm to 700 sccm, from 500 sccm to 700 sccm, from 50 sccm to 500 sccm, from 100 sccm to 500 sccm, from 300 sccm to 500 sccm, from 50 sccm to 300 sccm, from 100 sccm to 300 sccm, or from 50 sccm to 100 sccm.

[0068] In some embodiments, the metal nitride layers 204, 206 are exposed to the molybdenum precursor at a pressure ranging from 5 Torr to 50 Torr, from 10 Torr to 50 Torr, from 25 Torr to 50 Torr, from 5 Torr to 25 Torr, from 10 Torr to 25 Torr, or from 5 Torr to 10 Torr.

[0069] Reference Figure 4D and Figure 5C In one or more embodiments, the platinum conductor layer 208 may have any suitable thickness. For example, the platinum conductor layer 208 may have a thickness in a range from 10 Å to 200 Å, from 20 Å to 200 Å, from 50 Å to 200 Å, from 100 Å to 200 Å, from 150 Å to 200 Å, from 10 Å to 150 Å, from 50 Å to 150 Å, from 100 Å to 150 Å, from 10 Å to 100 Å, from 50 Å to 100 Å, from 10 Å to 50 Å, or from 10 Å to 30 Å.

[0070] Reference Figure 4D and Figure 5C In some embodiments, a molybdenum conductor layer 208 is formed within feature 210. The molybdenum conductor layer 208 of some embodiments fills the gap formed by the feature in a bottom-up manner. As used in this manner, "bottom-up" means that deposition occurs substantially on the bottom of the feature relative to the sidewalls.

[0071] In some embodiments, the platinum conductor layer 208 is formed to include elemental molybdenum. In some embodiments, the platinum conductor layer 108 consists essentially of platinum. As used in this manner, the term "consisting essentially of platinum" means that the content of platinum in the film is greater than or equal to about 80%, 85%, 90%, 95%, 98%, 99%, or 99.5% molybdenum in atomic percentage. The composition of the platinum conductor layer 108 is measured with reference to the bulk portion of the platinum conductor layer 208, excluding interface regions where diffusion of elements from adjacent films may occur.

[0072] Spatially relative terms such as "below", "below", "down", "above", "upper" and similar terms may be used herein to simplify the description, so as to describe the relationship of one element or feature relative to another element or feature as shown in the figure. It should be understood that spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation shown in the figure. For example, if the device in the figure is reversed, the components described as "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the exemplary term "below" can cover both the orientation of the upper and lower sides. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly.

[0073] The use of the terms "a" and "an" and "the" and similar indicators in the context of describing the materials and methods discussed herein (particularly in the context of the appended claims) is strictly interpreted to cover both the singular and the plural, unless otherwise specified herein or clearly contradicted by the context. The numerical ranges mentioned herein are intended only as a shorthand method of individually referring to each separate value falling within this range, and unless otherwise specified herein, each separate value is incorporated into this specification as if it were individually mentioned herein. All methods described herein can be performed in any suitable order, unless otherwise specified herein or clearly contradicted by the context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods, and does not impose limitations on the scope unless otherwise stated. Any language in this specification should not be interpreted as indicating that any non-declared element is necessary for the implementation of the disclosed materials and methods.

[0074] References throughout this specification to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described with respect to that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in an embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0075] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is intended that the present disclosure includes modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a buried word line, the method comprising: depositing a metal nitride layer on a substrate, the metal nitride layer comprising lanthanum nitride; as well as A molybdenum conductor layer is deposited on the metal nitride layer by an atomic layer deposition (ALD) process.

2. The method of claim 1, wherein the metal nitride layer has a thickness of less than 20 Å. The method of claim 1 , further comprising depositing a second metal nitride layer on the metal nitride layer. 4 . The method of claim 3 , wherein the second metal nitride layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), yttrium nitride (YN), zirconium nitride (ZrN), hafnium nitride (HfN), and barium nitride (BaN). The method of claim 4 , wherein the second metal nitride layer comprises titanium nitride. The method of claim 1 , wherein the ALD process is a thermal process.

7. The method of claim 1, wherein the molybdenum conductor layer is selectively deposited on the metal nitride layer.

8. The method of claim 1, wherein the ALD process comprises sequentially exposing the substrate to a reactant and a molybdenum precursor.

9. The method of claim 1, wherein the platinum conductor layer is deposited to a thickness in a range from 10 Å to 200 Å.

10. The method of claim 1, wherein the ALD process occurs at a temperature in the range of 350°C to 550°C.

11. The method of claim 1 , wherein the buried word line has a resistance less than or equal to 20 µΩ-cm at a total thickness of 100 Å.

12. The method of claim 1 wherein the substrate has at least one feature having a bottom and at least one sidewall.

13. The method of claim 12, wherein the at least one feature has a width in the range of 10 nm to 12 nm.

14. The method of claim 12, wherein the at least one feature is filled with the molybdenum conductor layer in a bottom-up manner.

15. A method for forming a buried word line, the method comprising: depositing a first metal nitride layer on a substrate, wherein the first metal nitride layer comprises lanthanum nitride; depositing a second metal nitride layer on the substrate; as well as A molybdenum conductor layer is deposited on the first metal nitride layer by an atomic layer deposition (ALD) process.

16. The method of claim 15, wherein the first metal nitride layer has a thickness less than 20 Å. 17 . The method of claim 15 , wherein the second metal nitride layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), yttrium nitride (YN), zirconium nitride (ZrN), hafnium nitride (HfN), and barium nitride (BaN).

18. The method of claim 15, wherein the first metal nitride layer and the second metal nitride layer have a combined thickness in a range from 15 Å to 30 Å. The method of claim 15 , wherein the ALD process is a thermal process.

20. The method of claim 15, wherein the molybdenum conductor layer is selectively deposited on the second metal nitride layer.

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