Dry electrode electroencephalogram signal acquisition system with high signal-to-noise ratio

Abstract

The embodiment of the invention relates to the field of electroencephalogram signal processing and brain-computer interfaces, and provides a high-signal-to-noise-ratio dry electrode electroencephalogram signal acquisition system which comprises a rigid-flex active electrode device and an electroencephalogram signal multi-stage conditioning and amplifying device. The rigid-flex active electrode device is inserted and interconnected through the electroencephalogram signal multi-stage conditioning and amplifying device by adopting a high-density and ultralow-height plate connector. And through active signal following and step-by-step conditioning and amplification, the signal quality and reliability of electroencephalogram signal acquisition are improved.

Description

Technical Field

[0001] The present application relates to the technical fields of electroencephalogram (EEG) signal processing and brain-computer interface, and in particular to a high signal-to-noise ratio dry electrode EEG signal acquisition system. Background Art

[0002] Obtaining stable and reliable EEG signals is the premise of scalp brain-computer interface technology. Electroencephalogram (EEG) is the spontaneous bioelectric activity at the scale of brain cell groups. EEG signals are usually very weak, with an amplitude generally between 1 and 100 μV, and are easily interfered by various physiological and environmental noises, which reduces the signal-to-noise ratio. Among them, electromagnetic interference is the most critical noise, such as the 1 / f noise of the components themselves, the thermal noise generated by the circuit, the 50Hz mains frequency noise, and the differential mode noise caused by the circuit asymmetry, DC bias error, etc. In order to reduce the impact of these noises and improve the signal-to-noise ratio, it is necessary to continuously improve the EEG signal conditioning and acquisition system, which is crucial to improving the accuracy and reliability of EEG signal research.

[0003] In the EEG signal acquisition system, due to the low connection reliability between devices, more noise interference is easily introduced, resulting in poor effect when processing the collected EEG signals. Summary of the invention

[0004] The embodiment of the present application provides a high signal-to-noise ratio dry electrode EEG signal acquisition system, which improves the signal quality and reliability of EEG signal acquisition through active signal following and step-by-step conditioning and amplification.

[0005] A first aspect of an embodiment of the present application provides a high signal-to-noise ratio dry electrode EEG signal acquisition system, characterized in that the system includes a rigid-flexible active electrode device and an EEG signal multi-stage conditioning and amplification device, wherein the rigid-flexible active electrode device is interconnected by a high-density and ultra-low-height board connector through the EEG signal multi-stage conditioning and amplification device, wherein:

[0006] The rigid-flexible active electrode device is used to send the collected EEG signal, reference signal and common-mode bias voltage signal to the EEG signal multi-stage conditioning and amplification device through the interface module;

[0007] The EEG signal multi-stage conditioning and amplification device is used to filter and perform differential amplification processing on the received EEG signal and the reference signal to obtain the final usable EEG signal.

[0008] In this example, the high signal-to-noise ratio dry electrode EEG signal acquisition system includes a rigid-flexible active electrode device and an EEG signal multi-stage conditioning and amplification device. The rigid-flexible active electrode device is interconnected with the EEG signal multi-stage conditioning and amplification device using a high-density and ultra-low-height board connector. Therefore, the signal quality and reliability of EEG signal acquisition are improved through active signal following and step-by-step conditioning and amplification.

[0009] In one possible implementation, the rigid-flex active electrode device includes a reference electrode, a bias drive electrode module and a first active electrode module, a second active electrode module, a third active electrode module, a fourth active electrode module, a fifth active electrode module, a sixth active electrode module, a seventh active electrode module, an eighth active electrode module and an interface module.

[0010] In a possible implementation, the first active electrode module includes a first active electrode and a first buffer driving circuit, wherein:

[0011] The first active electrode is used to collect the user's brain electrical signal.

[0012] In one possible implementation, the EEG signal multi-stage conditioning and amplification device includes a reference signal buffer distribution module, a first-stage filtering module, 8-channel first-stage differential amplification modules, a second-stage filtering module, 8-channel second-stage differential amplification modules, a bias drive signal generation module and a differential ADC module.

[0013] In a possible implementation, the reference signal buffer allocation module is used to generate 8 identical and independent reference signals according to the reference signal of the collected EEG signal;

[0014] The first-stage filtering module is used to filter out high-frequency noise and DC bias signals in the EEG signal;

[0015] The second-stage filtering module is used to filter out high-frequency noise in the EEG signal;

[0016] The first-stage differential amplifier module is used to perform a first-stage amplification process on the EEG signal;

[0017] The second-stage differential amplifier module is used to perform secondary amplification processing on the EEG signal.

[0018] The differential ADC module is used to convert the EEG signal into a digital signal;

[0019] The gain of the first-stage differential amplifier module is smaller than the gain of the second-stage differential amplifier module.

[0020] In a possible implementation, the bias drive signal generating module is used to generate a common mode reference voltage, and the common mode reference voltage is used to suppress common mode noise of the EEG signal.

[0021] In a possible implementation, an amplification gain value of the first-stage differential amplification module is an amplification gain value between 2 and 10.

[0022] The high signal-to-noise ratio dry electrode EEG signal acquisition system provided in the embodiment of the present application adopts a variety of technical methods to condition and correct the EEG signals, etc., to support the acquisition of more accurate EEG signals. The specific technical methods include: drive-amplification separation design, front active drive circuit design, step-by-step conditioning and amplification design, anti-interference design and four-level fitting structure design, as follows:

[0023] Driver-amplifier separation design:

[0024] In order to ensure the quality of EEG signals, first of all, the first part needs to design a high-impedance active buffer conditioning circuit (corresponding to the rigid-flexible active electrode device) near the scalp to reduce the influence of the high internal resistance of the EEG signal source itself, improve the EEG signal driving ability, and reduce the susceptibility to noise interference caused by high contact impedance; then, the second part consists of a multi-stage conditioning and amplification circuit (corresponding to the EEG signal multi-stage conditioning and amplification device) to perform multi-stage filtering and differential amplification processing on the EEG signal to effectively improve the signal-to-noise ratio. The multi-stage conditioning and amplification circuit is interconnected with the rigid-flexible active electrode device through a high-density connector. Because the active electrode device realizes the driving isolation of the EEG signal source, this part of the circuit does not need to consider the influence of the high internal resistance characteristics of the EEG signal source on the circuit, and can be designed and assembled independently of the active electrode device, with strong flexibility and scalability.

[0025] Front active drive circuit design:

[0026] EEG signal high-impedance buffer conditioning circuit, each dry electrode is equipped with such a circuit (bias drive electrode module), which can flexibly realize the dry electrode distribution design in the brain area and the EEG signal drive isolation transmission, and abandon the long wire to transmit the EEG signal, and adopt the rigid-flexible circuit board structure, which can provide a good reference plane for the EEG signal, effectively ensuring the signal integrity and anti-interference ability. The front active drive circuit realizes: ultra-high input impedance, reducing the signal attenuation and noise caused by high contact impedance and its changes; reducing the equivalent impedance of the circuit and reducing the noise introduced by line coupling.

[0027] Step-by-step adjustment and amplification design:

[0028] The two-stage passive filter circuit and the two-stage differential amplifier circuit are used, and the filter circuit and the differential amplifier circuit are designed alternately, which can effectively filter out the noise interference in the EEG signal, suppress the common mode interference, and greatly improve the signal-to-noise ratio. Among them, the two-stage differential amplifier circuit, the first stage is a high-impedance and low-gain differential amplifier, which reduces the influence of the high internal resistance of the front-stage filter circuit, suppresses noise, and improves the signal-to-noise ratio for the first time. The second stage is a high-impedance and high-gain differential amplifier, which achieves a secondary improvement in the signal-to-noise ratio. Thus, the two-stage differential amplifier circuit can effectively improve the signal-to-noise ratio.

[0029] Anti-interference design:

[0030] In the circuit design, a variety of anti-interference designs are used to reduce noise interference. In the PCB design of the rigid-flex active electrode device, a printed shielded circuit design is adopted, and an independent power layer and ground layer are used to provide a good reference plane for the EEG signal, and can also effectively shield noise interference. In the PCB design of the EEG signal multi-stage conditioning and amplification device, multiple layers of power layers and ground layers are also used to provide a good reference plane for the multi-stage conditioning and amplification of the EEG signal, ensuring signal integrity. Moreover, in the PCB design of the EEG signal multi-stage conditioning and amplification device, the analog circuit and the digital circuit are well laid out and divided, which can effectively avoid the interference of the digital circuit on the analog circuit. Both two-stage differential amplifier circuits use a low input noise differential amplifier with a common mode rejection ratio of up to 120dB, which can effectively suppress the common mode interference in the circuit and reduce the influence of the circuit's own noise.

[0031] Four-level fitting structure design:

[0032] In order to further ensure the good fit between the dry electrode and the scalp and reduce the contact impedance of the dry electrode scalp interface, a flexible comb electrode and a multi-level adaptive fit design are used. First, the use of a flexible comb dry electrode makes it easier for the electrode to pass through the hair and contact the scalp; second, the design of the middle detail of the dry electrode (active electrode) makes the dry electrode as a whole adaptable; third, the looser structural design of the electrode holder and the flexible active drive electrode design ensure that the electrode can move flexibly in the electrode holder, further improving the adaptability; fourth, the electrode is fixed in an elastic shell, which is designed based on anthropometric head circumference data and fixed with elastic bands to ensure overall fit with different head shapes. The four-level fit design ensures that the electrode can fit well with the scalp and have a stable contact effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of the structure of a high signal-to-noise ratio dry electrode EEG signal acquisition system is provided for an embodiment of the present application;

[0035] Figure 2 A schematic diagram of the structure of a multi-stage EEG signal conditioning and amplification device is provided for an embodiment of the present application;

[0036] Figure 3 A structural schematic diagram of a reference signal buffer allocation module is provided for an embodiment of the present application;

[0037] Figure 4 A structural schematic diagram of a first-stage differential amplifier module is provided for an embodiment of the present application;

[0038] Figure 5 A circuit structure diagram of a second-stage differential amplifier module and a differential ADC module is provided for an embodiment of the present application;

[0039] Figure 6 A circuit structure schematic diagram of a bias drive signal generating module is provided for an embodiment of the present application;

[0040] Figure 7 A PCB stacking structure diagram of a circuit board of a multi-stage EEG signal conditioning and amplification device is provided for an embodiment of the present application;

[0041] Figure 8 A structural schematic diagram of a rigid-flex active electrode device is provided for an embodiment of the present application;

[0042] Fig. 9 A structural schematic diagram of a first movable electrode module is provided for an embodiment of the present application;

[0043] Fig.10 A schematic structural diagram of a bias driving electrode module is provided for an embodiment of the present application;

[0044] Fig.11 A schematic diagram of the architecture of a FR4 hard board is provided for an embodiment of the present application;

[0045] Fig.12 A schematic diagram of the architecture of a flexible board is provided for an embodiment of the present application;

[0046] Fig.13 A schematic diagram of a collected EEG signal is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0049] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments.

[0050] In order to better understand the multi-stage EEG signal conditioning and amplification device provided in the embodiment of the present application, the EEG signal acquisition scheme in the existing scheme is first briefly introduced below.

[0051] The EEG acquisition and amplification circuit based on wet electrodes is relatively mature. However, wet electrodes have problems such as long preparation time and inconvenience in wearing, which seriously restrict the practical application of brain-computer interfaces. The EEG signal acquisition based on dry electrodes is prone to introduce more noise interference due to the high contact impedance between the dry electrodes and the skin, resulting in a low signal-to-noise ratio of the collected EEG signals, and the clarity and accuracy of the signal are affected to a certain extent. In addition, the contact state between the electrode and the skin may be affected by many factors, such as sweating, oil secretion, hair interference, etc., which leads to large signal fluctuations, and puts higher requirements on the filtering, amplification, and acquisition of EEG signals.

[0052] Specifically, when collecting EEG signals, the following technical difficulties are usually encountered: 1) the signal is weak, with an amplitude ranging from a few microvolts to hundreds of microvolts; 2) the contact impedance is high; 3) it is susceptible to interference. Tiny signals are susceptible to various noise interferences, and a high amplification factor easily leads to synchronous noise amplification; the high contact impedance of dry electrodes easily causes signal attenuation, and makes it easy for environmental noise to be introduced into the collection process.

[0053] In view of the above difficulties, the high signal-to-noise ratio dry electrode EEG signal acquisition system provided in the embodiment of the present application improves the signal quality and reliability of EEG signal acquisition through active signal following and step-by-step conditioning and amplification. The specific technical solutions include: drive-amplification separation design, pre-active drive circuit design, step-by-step conditioning and amplification design, anti-interference design and four-level fitting structure design, as follows:

[0054] Driver-amplifier separation design:

[0055] In order to ensure the quality of EEG signals, first of all, the first part needs to design a high-impedance active buffer conditioning circuit (corresponding to the rigid-flexible active electrode device) near the scalp to reduce the influence of the high internal resistance of the EEG signal source itself, improve the EEG signal driving ability, and reduce the susceptibility to noise interference caused by high contact impedance; then, the second part consists of a multi-stage conditioning and amplification circuit (corresponding to the EEG signal multi-stage conditioning and amplification device) to perform multi-stage filtering and differential amplification processing on the EEG signal to effectively improve the signal-to-noise ratio. The multi-stage conditioning and amplification circuit is interconnected with the rigid-flexible active electrode device through a high-density connector. Because the active electrode device realizes the driving isolation of the EEG signal source, this part of the circuit does not need to consider the influence of the high internal resistance characteristics of the EEG signal source on the circuit, and can be designed and assembled independently of the active electrode device, with strong flexibility and scalability.

[0056] Front active drive circuit design:

[0057] EEG signal high-impedance buffer conditioning circuit, each dry electrode is equipped with such a circuit (bias drive electrode module), which can flexibly realize the dry electrode distribution design in the brain area and the EEG signal drive isolation transmission, and abandon the long wire to transmit the EEG signal, and adopt the rigid-flexible circuit board structure, which can provide a good reference plane for the EEG signal, effectively ensuring the signal integrity and anti-interference ability. The front active drive circuit realizes: ultra-high input impedance, reducing the signal attenuation and noise caused by high contact impedance and its changes; reducing the equivalent impedance of the circuit and reducing the noise introduced by line coupling.

[0058] Step-by-step adjustment and amplification design:

[0059] The two-stage passive filter circuit and the two-stage differential amplifier circuit are used, and the filter circuit and the differential amplifier circuit are designed alternately, which can effectively filter out the noise interference in the EEG signal, suppress the common mode interference, and greatly improve the signal-to-noise ratio. Among them, the two-stage differential amplifier circuit, the first stage is a high-impedance and low-gain differential amplifier, which reduces the influence of the high internal resistance of the front-stage filter circuit, suppresses noise, and improves the signal-to-noise ratio for the first time. The second stage is a high-impedance and high-gain differential amplifier, which achieves a secondary improvement in the signal-to-noise ratio. Thus, the two-stage differential amplifier circuit can effectively improve the signal-to-noise ratio.

[0060] Anti-interference design:

[0061] In the circuit design, a variety of anti-interference designs are used to reduce noise interference. In the PCB design of the rigid-flex active electrode device, a printed shielded circuit design is adopted, and an independent power layer and ground layer are used to provide a good reference plane for the EEG signal, and can also effectively shield noise interference. In the PCB design of the EEG signal multi-stage conditioning and amplification device, multiple layers of power layers and ground layers are also used to provide a good reference plane for the multi-stage conditioning and amplification of the EEG signal, ensuring signal integrity. Moreover, in the PCB design of the EEG signal multi-stage conditioning and amplification device, the analog circuit and the digital circuit are well laid out and divided, which can effectively avoid the interference of the digital circuit on the analog circuit. Both two-stage differential amplifier circuits use a low input noise differential amplifier with a common mode rejection ratio of up to 120dB, which can effectively suppress the common mode interference in the circuit and reduce the influence of the circuit's own noise.

[0062] Four-level fitting structure design:

[0063] In order to further ensure the good fit between the dry electrode and the scalp and reduce the contact impedance of the dry electrode scalp interface, a flexible comb electrode and a multi-level adaptive fit design are used. First, the use of a flexible comb dry electrode makes it easier for the electrode to pass through the hair and contact the scalp; second, the design of the middle detail of the dry electrode (active electrode) makes the dry electrode as a whole adaptable; third, the looser structural design of the electrode holder and the flexible active drive electrode design ensure that the electrode can move flexibly in the electrode holder, further improving the adaptability; fourth, the electrode is fixed in an elastic shell, which is designed based on anthropometric head circumference data and fixed with elastic bands to ensure overall fit with different head shapes. The four-level fit design ensures that the electrode can fit well with the scalp and have a stable contact effect.

[0064] See also Figure 1 , Figure 1 The present invention provides a schematic diagram of the structure of a high signal-to-noise ratio dry electrode EEG signal acquisition system. Figure 1 As shown, the high signal-to-noise ratio dry electrode EEG signal acquisition system 100 includes an EEG signal multi-stage conditioning and amplifier device 200 and a rigid-flexible active electrode device 300, wherein the rigid-flexible active electrode device is connected to the EEG signal multi-stage conditioning and amplifier device, wherein the rigid-flexible active electrode device is used to send the collected EEG signal and reference signal to the EEG signal multi-stage conditioning and amplifier device, wherein the EEG signal multi-stage conditioning and amplifier device is used to amplify and condition the received EEG signal, and generate a common-mode bias voltage signal and send it to the EEG signal multi-stage conditioning and amplifier device.

[0065] Among them, after receiving the EEG signal and the reference signal, the EEG signal multi-stage conditioning and amplification device 200 performs filtering and differential amplification processing to obtain the final usable EEG signal, which greatly improves the signal quality and signal-to-noise ratio of the acquired EEG signal.

[0066] Specifically, the EEG signal multi-stage conditioning and amplification device 200 and the rigid-flexible active electrode device 300 use high-density and ultra-low-height board connectors AXT616124 and AXT516124 for plug-in interconnection. The terminals of the connectors are made of copper alloy and are electroplated with Ni on the bottom layer and Au on the surface, which improves the contact stability and durability.

[0067] See also Figure 2 , Figure 2 The present invention provides a schematic diagram of a multi-stage electroencephalogram signal conditioning and amplification device. Figure 2 As shown, the method is applied to a high signal-to-noise ratio dry electrode EEG signal acquisition system, the device includes a reference signal buffer distribution module 1, a first-stage filtering module 2, an 8-way first-stage differential amplifier module 3, a second-stage filtering module 4, an 8-way second-stage differential amplifier module 5, a bias drive signal generation module 6 and a differential ADC module 7, wherein,

[0068] The signal output port of the reference signal buffer distribution module 1 is connected to the first type input port of the first filtering module, and the second type input port of the first filtering module is a signal receiving port of 8-channel EEG signals;

[0069] The 8 first-class signal output ports of the first-stage filtering module are respectively connected to the first input ports of the 8 first-stage differential amplifier modules, and the 8 second-class signal output ports of the first-stage filtering module 2 are respectively connected to the second input ports of the 8 first-stage differential amplifier modules 3.

[0070] The output ports of the 8-way first-stage differential amplifier module 3 are connected to the 8-way input ports corresponding to the second-stage filter module, the 8-way output ports of the second-stage filter module 4 are respectively connected to the input ports of the 8-way second-stage differential amplifier module 5, the first-type output ports of the 8-way second-stage differential amplifier module 5 are connected to the corresponding signal input ports in the differential ADC module 7, the second-type output ports of the 8-way second-stage differential amplifier module 5 are connected to the input port of the bias drive signal generating module, and the corresponding signal output port in the differential ADC module 7 is connected to the microprocessor; the output port of the bias drive signal generating module 6 is connected to the bias drive electrode;

[0071] The reference signal buffer distribution module 1 is used to receive the reference signal of the collected EEG signal, and generate 8 identical and independent reference signals according to the reference signal;

[0072] The gain of the first-stage differential amplifier module 3 is smaller than the gain of the second-stage differential amplifier module 5 .

[0073] The first-stage filter module 2 includes 16 first-stage sub-filter modules, each of which includes a first-stage low-pass filter circuit and a first-stage high-pass filter circuit. Among the 16 first-stage sub-filter modules, 8 signal input ports are first-class input ports, and the other 8 signal input ports are second-class input ports. The 8 first-stage sub-filter modules of the second-class input ports receive corresponding EEG signals respectively, and there are 8 EEG signals in total. The 8 first-stage sub-filter modules of the first-class input ports receive corresponding reference signals of EEG signals respectively. The electrical parameters of the 16 first-stage sub-filter modules are the same. The first-stage low-pass filter circuit is a passive RC low-pass filter circuit; the first-stage high-pass filter circuit can be a passive RC high-pass filter circuit. The output end of the first-stage low-pass filter circuit is connected to the input end of the first-stage high-pass filter circuit.

[0074] The EEG signal passes through the first-stage low-pass filter circuit to attenuate high-frequency interference, and then passes through the first-stage high-pass filter circuit to filter out the DC bias component in the signal, thereby retaining the EEG signal in the effective frequency band. At the same time, the reference signal generates 8 identical and independent reference signals through the buffer distribution circuit, which are used as differential reference input signals of the 8-channel EEG signals respectively, and are also conditioned by low-pass and high-pass filter circuits consistent with the electrical parameters of the EEG signals. Then, the processed EEG signal of each channel and the corresponding reference signal are input as a differential pair into the first-stage differential amplifier module 3 of the corresponding channel for amplification to improve the signal-to-noise ratio. The output differential signal passes through the second-stage filter module 4 to further attenuate the high-frequency noise in the signal, and then enters the second-stage differential amplifier module 5 for further amplification. Finally, the 8-channel parallel differential ADC circuit realizes the analog-to-digital conversion of the 8-channel EEG signals, and finally the MCU controller realizes the collection, transmission and processing of the EEG signals.

[0075] The device also realizes the output of bias drive signal, that is, the DC bias of the output signal of the second-stage differential amplifier module 5 generates a common-mode voltage signal with opposite polarity through the bias drive circuit, which is connected to the human body through the bias drive electrode to provide a common-mode reference voltage for the human body and limit the common-mode interference noise to a very narrow range, which helps to reduce the common-mode interference of the EEG signal on the active electrode and the reference electrode. The signal is extremely weak and will not cause adverse effects on the human body.

[0076] In this example, the EEG signal is filtered by the first-stage filtering module 2 to retain the EEG signal of the effective frequency band. At the same time, the reference signal is passed through the buffer distribution circuit to generate 8 identical and independent reference signals, which are used as differential reference input signals of the 8 EEG signals respectively. After filtering and conditioning consistent with the electrical parameters of the EEG signal, the processed EEG signal of each channel and the corresponding reference signal are input as a differential pair into the first-stage differential amplifier circuit of the corresponding channel for amplification to improve the signal-to-noise ratio. The output differential signal passes through the second-stage low-pass filtering circuit to further attenuate the high-frequency noise in the signal, and then enters the second-stage differential amplifier circuit. The differential amplifier circuit amplifies the signal again, and finally an 8-way parallel differential ADC circuit realizes analog-to-digital conversion of the 8-way EEG signals. Finally, the MCU controller realizes the acquisition, transmission and processing of the EEG signals. At the same time, the bias drive signal generation and output is also realized, that is, the DC bias of the output signal of the second-stage differential amplifier circuit generates a common-mode voltage signal with opposite polarity through the bias drive signal generating module 6. The signal is connected to the human body through the bias drive electrode to provide a common-mode reference voltage for the human body, and the common-mode interference noise is limited to a very narrow range, thereby reducing the common-mode interference of the EEG signal and further improving the signal-to-noise ratio of the EEG signal.

[0077] In a specific implementation, Figure 3 As shown, the reference signal buffer distribution module 1 includes a first unit gain buffer 11, a second unit gain buffer 12, a sixtieth capacitor C60, a sixty-first capacitor C61, a sixty-second capacitor C62 and a sixty-third capacitor C63, wherein:

[0078] The first port, the fifth port, the sixth port and the tenth port of the first unit gain buffer 11 are used to receive a reference signal of an EEG signal, the third port of the first unit gain buffer 11 is connected to a positive power supply port and a first end of the sixtieth capacitor C60, the second end of the sixtieth capacitor C60 is grounded, the eighth port of the first unit gain buffer 11 is connected to a negative power supply port and a first end of the sixtieth capacitor C61, the second end of the sixtieth capacitor C61 is grounded, the second port, the fourth port, the seventh port and the ninth port of the first unit gain buffer 11 are respectively connected to corresponding first-class input ports in the first filtering module;

[0079] The first port, the fifth port, the sixth port and the tenth port of the second unit gain buffer are used to receive the reference signal of the EEG signal, the third port of the second unit gain buffer 12 is connected to the positive power supply port and the first end of the sixty-second capacitor C62, the second end of the sixty-second capacitor C62 is grounded, the eighth port of the second unit gain buffer 12 is connected to the negative power supply port and the first end of the sixty-third capacitor C63, the second end of the sixty-third capacitor C63 is grounded, the second port, the fourth port, the seventh port and the ninth port of the second unit gain buffer 12 are respectively connected to the corresponding first-class input ports in the first filtering module.

[0080] Among them, the input signal of the reference signal buffer distribution module 1 is the reference signal of the EEG signal. After receiving the reference signal, 8 identical and independent reference signals are generated through the first unit gain buffer 11, the second unit gain buffer 12 and its peripheral circuits. The 8 identical and independent reference signals are respectively input into the subsequent corresponding 8-way first-stage differential amplifier module 3. The first unit gain buffer 11 and the second unit gain buffer 12 are identical unit gain buffers, which can be specifically AD8244 unit gain buffers. Since 8 identical and independent reference signals can be generated, the reference signal driving capability is improved and the coupling interference between channels is reduced.

[0081] In a specific implementation, Figure 4 As shown, the first-stage differential amplifier module 3 includes a first amplifier chip 31, a one-hundred-sixty-eighth capacitor C168, a one-hundred-twelfth resistor R112, a one-hundred-sixty-ninth capacitor C169, a one-hundred-seventy capacitor C170, a one-hundred-seventy-first capacitor C171, a one-hundred-seventy-second capacitor C172, a one-hundred-seventy-third capacitor C173, and a one-hundred-thirteenth resistor R113, wherein:

[0082] A 168th capacitor C168 is connected in parallel between the first signal input port and the second signal input port of the first stage differential amplifier module 3, and then connected to the first port of the first amplifier chip 31 and the fourth port of the first amplifier chip 31 respectively, and a 112th resistor R112 is connected in series between the second port and the third port of the first amplifier chip 31;

[0083] The fifth port of the first amplifier chip 31 is connected to the first end of the first one hundred and sixty-ninth capacitor C169 and the positive power supply port, and the second end of the first one hundred and sixty-ninth capacitor C169 is grounded;

[0084] The sixth port of the first amplifier chip 31 is connected to the fourteenth port, and the fourteenth port of the first amplifier chip 31 is the second output port of the first-stage differential amplifier module 3;

[0085] The seventh port of the first amplifier chip 31 is grounded, the eighth port of the first amplifier chip 31 is connected to the negative power supply port, the zeroth port, and the first end of the 170th capacitor C170, the second end of the 170th capacitor C170 is grounded, and the ninth port of the first amplifier chip 31 is grounded;

[0086] The twelfth port of the first amplifier chip 31 is connected to the first end of the first-hundred-and-seventy-third capacitor C173 and the first end of the first-hundred-and-thirteenth resistor R113, the second end of the first-hundred-and-thirteenth capacitor C173 is grounded, the second end of the first-hundred-and-thirteenth resistor R113 is connected to the fifteenth port of the first amplifier chip 31, and the fifteenth port of the first amplifier chip 31 is the second output port of the first-stage differential amplifier module 3;

[0087] The thirteenth port of the first amplifier chip 31 is connected to the first end of the first-hundred-and-seventy-second capacitor C172 and the negative power supply port, and the second end of the first-hundred-and-seventy-second capacitor C172 is grounded. The sixteenth port of the first amplifier chip 31 is connected to the first end of the first-hundred-and-seventy-first capacitor C171 and the positive power supply port, and the second end of the first-hundred-and-seventy-first capacitor C171 is grounded.

[0088] The first amplifier chip 31 can be a dual-channel precision instrument amplifier. The electrical parameters of the 8-way first-stage differential amplifier module 3 are the same. In the single-channel fully differential amplifier circuit, an RC low-pass filter circuit composed of R113 and C173 is designed to ensure the stability of the negative feedback loop.

[0089] In a specific implementation, Figure 2 As shown, the second-stage filtering module 4 includes 8 second sub-filtering modules 41, the electrical parameters of the 8 second sub-filtering modules 41 are the same, the input ports of the 8 second sub-filtering modules 41 are respectively connected to the output ports of the corresponding first-stage differential amplifier modules 3, and the output ports of the 8 second sub-filtering modules 41 are respectively connected to the input ports of the corresponding second-stage differential amplifier modules 5.

[0090] like Figure 4 As shown, the second sub-filtering module 41 includes a 114th resistor R114, a 115th resistor R115, a 174th capacitor C174 and a 175th capacitor C175, the 114th resistor R114 is connected in series between the first output port of the first-stage differential amplifier module 3 and the first end of the 174th capacitor C174, the first end of the 174th capacitor C174 and the 114th resistor R114 are connected to the first output port of the second sub-filtering module (indicated by AIN7P), and the second end of the 174th capacitor C174 is grounded;

[0091] The first-one-hundred-and-fifteenth resistor R115 is connected in series between the second output port of the first-stage differential amplifier module 3 and the first end of the first-one-hundred-and-fifteenth capacitor C175, the second output port (indicated by AIN7N) of the second sub-filtering module is connected between the first end of the first-one-hundred-and-fifteenth capacitor C175 and the first-one-hundred-and-fifteenth resistor R115, and the second end of the first-one-hundred-and-fifteenth capacitor C175 is grounded.

[0092] The differential output signal then passes through the second-stage passive RC low-pass filter circuit (green box), which can further attenuate the high-frequency noise in the differential signal.

[0093] In a specific implementation, Figure 5 As shown, Figure 5 FIG. 2 shows a schematic diagram of the circuit structure of the second-stage differential amplifier module 5 and the differential ADC module 7. The differential ADC module 7 includes 8 differential ADC circuits, which correspond to the 8 second-stage differential amplifier modules 5, respectively. Figure 5 As shown, a schematic diagram of a second-stage differential amplifier module 5 and a differential ADC circuit is shown, and the second-stage differential amplifier module 5 and the differential ADC circuit are implemented by an analog front-end integrated circuit ADS1299, and its circuit diagram is shown Figure 5 As shown. ADS1299 is a high-performance physiological signal acquisition integrated chip, which contains 8 low-noise programmable gain amplifiers (PGA) and 8 synchronous sampling analog / digital converters (ADC). The input end can be configured as a differential input, with a common mode rejection ratio (CMRR) of up to 110dB and a DC input impedance of up to 1GΩ. The amplification gain of PGA can be selected from 1, 2, 4, 6, 8, 12 and 24 specifications, the ADC conversion accuracy is up to 24bit, and the sampling rate ranges from 250SPS to 16k SPS, which is very suitable for weak EEG signal acquisition.

[0094] In a specific implementation, Figure 6 As shown, the bias drive signal generating module 6 includes a bias drive amplifier 61, a drive signal source network 62, an external resistor R f , compensation capacitor C f , a first resistor R1 and a second resistor R2, wherein,

[0095] The driving signal source network 62 is connected to the second type output ports of the 8-way second-stage differential amplifier module 5, and the output ports of the driving signal source network 62 are connected to the external resistor R f The first end of the compensation capacitor C f The first end of the bias driving amplifier 61 is connected to the inverting input end of the bias driving amplifier 61, and the external resistor R f The second end of the compensation capacitor C fThe second end of is connected to the output end of the bias driving amplifier 61, the non-inverting input end of the bias driving amplifier 61 is connected to the first end of the first resistor R1 and the first end of the second resistor R2, the second end of the first resistor R1 is connected to the positive power supply port, and the second end of the second resistor R2 is connected to the negative power supply port.

[0096] The driving signal source network 62 includes 8 pairs of R p 1. R n 1, are respectively connected to the corresponding EEG signal differential pairs, and the EEG signal differential pairs are represented as EEG signal 1 differential pair to EEG signal 8 differential pair.

[0097] The bias drive amplifier 61 (BIAS amp) is a built-in bias drive amplifier of ADS1299. The drive signal source of the drive signal source network 62 comes from the differential signal of the 8 channels of the second-stage differential amplifier circuit, that is, the DC bias in the EEG signals of the 8 channels are superimposed, and a common-mode voltage BIAS_OUT with opposite polarity is generated through a reverse proportional amplifier circuit, and then connected to the surface of human skin through a bias drive electrode to provide a common-mode reference voltage with opposite polarity for the human body. In this way, most of the common-mode interference signals can be offset, thereby achieving suppression of common-mode noise on the EEG signal at the input end, greatly improving the signal-to-noise ratio of the entire circuit.

[0098] C in the circuit f To compensate the capacitance, phase compensation is performed on the amplifier circuit to prevent the circuit from self-oscillating. The positive input of the op amp is half of the sum of the positive power supply AVDD and the negative power supply AVSS, thus forming a closed loop.

[0099] In a specific implementation, the capacitance value of the compensation capacitor ranges from 1.5 nF to 500 pF.

[0100] In a specific implementation, the first-stage filtering module 2 includes a low-pass filtering circuit and a high-pass filtering circuit, the cut-off frequency of the low-pass filtering circuit is a frequency value between 1.5KHz and 40kHz, and the cut-off frequency of the high-pass filtering circuit is less than 0.5Hz.

[0101] In a specific implementation, the amplification gain value of the first-stage differential amplification module 3 is an amplification gain value between 2-10.

[0102] In a specific implementation, the embodiment of the present application also provides a circuit parameter design scheme for a first-stage filtering module 2, a first-stage differential amplifier module 3, a second-stage filtering module 4, a second-stage differential amplifier module 5, a bias drive signal generating module 6, and a differential ADC module 7, which are as follows:

[0103] 1) Electrical parameter design of the first-stage filter module 2:

[0104] The first-stage filtering module 2 includes a low-pass filtering circuit and a high-pass filtering circuit. According to actual engineering application experience, this design sets the passband of the bandpass filtering circuit composed of low-pass and high-pass filtering circuits to be larger, thereby ensuring that the wider-band EEG signal enters the post-amplification circuit for processing without attenuation or with less attenuation.

[0105] Depend on Figure 7 It can be seen that in the pre-RC low-pass filter circuit, the resistor R is selected as 4.02kΩ, the capacitor C is selected as 10nF, and the cut-off frequency calculation formula is The cutoff frequency of the low-pass filter circuit is about 3.9kHz. According to engineering experience, the signal within 0.1 times the cutoff frequency can be considered to pass without attenuation, that is, the frequency of the low-pass filter circuit without attenuation is set to 390Hz, covering the effective frequency range of the EEG signal. Experimental verification shows that the quality of EEG signal acquisition can be guaranteed when the low-pass cutoff frequency fc is in the range of 1.5KHz to 40kHz.

[0106] In the pre-RC high-pass filter circuit, the resistor R is selected as 220kΩ, the capacitor C is selected as 4.7uF, and the cut-off frequency is calculated by the formula The cutoff frequency of the high-pass filter circuit is about 0.15Hz. According to engineering experience, signals above 10 times the cutoff frequency can be considered to pass without attenuation, that is, the frequency of the high-pass filter circuit without attenuation is set to 1.5Hz, covering the effective frequency range of the EEG signal. Experimental verification shows that the quality of EEG signal acquisition can be guaranteed when the high-pass cutoff frequency fc is less than 0.5Hz.

[0107] Through comparison of experimental results, the non-attenuation frequency range of the bandpass filter circuit composed of low-pass and high-pass filter circuits was finally set to 1.5Hz to 390Hz.

[0108] 2) Electrical parameter design of the first stage differential amplifier module 3

[0109] This design uses a two-stage amplifier circuit. In order to avoid reducing the signal-to-noise ratio of the circuit due to excessive amplification noise, the gain of the first-stage amplifier circuit is set lower. Figure 8 As shown, the amplification gain of the first-stage differential amplifier circuit is uniquely determined by the 112th resistor R112. The 112th resistor R112 is set to 12.4 kΩ. According to the gain formula: The calculation shows that the amplification gain is about 5. Experimental verification shows that when the gain of the first-stage amplifier circuit is between 2 and 10, the signal-to-noise ratio index can be maintained at a high level.

[0110] 3) Electrical parameter design of the second-stage filter module 4

[0111] In order to further filter out high-frequency interference in the effective signal, such as Figure 8 As shown, the 114th resistor R114 and the 115th resistor R115 of the second sub-filter module in the second-stage filter module 4 are set to 8.2 kΩ, the 174th capacitor C174 and the 175th capacitor C175 are set to 10 nF, and the cut-off frequency is calculated by the formula The cutoff frequency of the second sub-filter module is about 1.9kHz. According to engineering experience, the signal within 0.1 times the cutoff frequency can be considered to pass without attenuation, that is, the frequency of the second sub-filter module without attenuation is set to 190Hz, which can meet the requirements of EEG signal acquisition in the effective frequency band. Experimental verification shows that the quality of EEG signal acquisition can be guaranteed when the low-pass cutoff frequency fc is in the range of 1.5KHz to 10kHz. The second sub-filter module is a low-pass filter circuit.

[0112] 4) Electrical parameter design of the second stage differential amplifier module 5

[0113] The second-stage differential amplifier module 5 is a programmable gain amplifier circuit. The gain of this stage of the circuit is set larger, which increases the dynamic application range of the subsequent AD conversion circuit and improves the accuracy of signal acquisition. At the same time, the differential amplifier circuit can also improve the signal-to-noise ratio again. It can be seen from the ADS1299 technical manual that when the gain is set to 24, the -3dB bandwidth of the ADC circuit is the lowest, about 27kHz, which can suppress high-frequency noise interference to a certain extent. In this way, the total gain of the two-stage amplifier circuit is 5×24=120. Experimental verification shows that when the gain of the second-stage differential amplifier module 5 is selected from the four specifications of 6, 8, 12, and 24, combined with the gain of the first-stage differential amplifier module 3, it is set between 2 and 10 to ensure that the total gain of the two-stage amplifier circuit is greater than 40, which can effectively guarantee the quality of signal acquisition.

[0114] 5) Differential ADC module 7 electrical parameter design

[0115] This design takes into account that the effective signal in EEG is in a lower frequency range, and the throughput of 8 parallel 24-bit AD acquisition channels is large. If the AD sampling rate is set higher, it will put a lot of communication pressure on the Bluetooth transmission channel in the system, which is easy to cause channel blocking and data loss, causing the entire system to work unstably. Finally, the AD sampling rate is set to 500SPS, which can match the overall parameters of the system and ensure high-precision and high-reliability data acquisition and transmission. Experimental verification shows that when the AD sampling rate is set between 200SPS and 1000SPS, the integrity of data acquisition and the reliability of data transmission can be effectively guaranteed.

[0116] 6) Design of electrical parameters of bias drive signal generating module 6

[0117] In order to fully consider and apply the DC bias of the 8 EEG signals, the driving signal source of the bias driving circuit is configured as the differential signal of the 8 channels from the second-stage differential amplifier module 5. In this way, the DC bias in the EEG signals of the 8 channels is superimposed, and a common mode voltage with opposite polarity is generated through the reverse proportional amplifier circuit. Fig.10 As shown, for an AC signal with a frequency of f, the gain formula of the proportional amplifier circuit is: Where Z F for: In order to offset most of the common-mode interference, the amplification gain of the bias drive circuit is required to be 1, that is, A=-1.

[0118] According to the ADS1299 manual, R in For 220kΩ, select R F is 1MΩ, Figure 8 The cutoff frequency of the second-stage low-pass filter circuit shown is set to 1.9kHz, and the compensation capacitor C can be calculated. F This parameter setting can provide a common-mode reference voltage with opposite polarity for the human body, which can effectively suppress most common-mode interference signals and improve the signal-to-noise ratio of the entire circuit. Experimental verification shows that the compensation capacitor C F The circuit can work normally when the resistance is in the range of 1.5nF to 500pF.

[0119] In a specific implementation, Figure 7 The PCB stacking structure diagram of the circuit board of the multi-stage EEG signal conditioning and amplification device is shown. Figure 7 As shown, it includes a top layer, a first GND layer, an intermediate signal layer, a power layer, a second GND layer and a bottom layer, wherein:

[0120] The first GND layer, the intermediate signal layer, the power layer, and the second GND layer are stacked in sequence between the top layer and the bottom layer, the first GND layer is adjacent to the top layer, and the second GND layer is adjacent to the bottom layer. The top layer, the intermediate signal layer, and the bottom layer are all used for signal transmission.

[0121] See also Figure 8 , Figure 8 A structural schematic diagram of a rigid-flex active electrode device is provided for an embodiment of the present application. Figure 8As shown, the rigid-flex active electrode device 300 includes: a reference electrode 101, a bias drive electrode module 102 and a first active electrode module 103, a second active electrode module 104, a third active electrode module 105, a fourth active electrode module 106, a fifth active electrode module 107, a sixth active electrode module 108, a seventh active electrode module 109, an eighth active electrode module 120 and an interface module 121, wherein the reference electrode 101 includes a buffer drive circuit 111 and a wet electrode sheet 112, wherein:

[0122] The ninth input interface to the sixteenth input interface of the interface module 121 are respectively connected to the corresponding output interface of the first active electrode module 103 to the output interface of the eighth active electrode module 120 through a flexible board, the first interface of the interface module 121 is connected to the output interface of the buffer drive circuit 111 through a flexible board, the input interface of the buffer drive circuit 111 is connected to the wet electrode sheet 112 through an electrode wire, and the second interface of the interface module 121 is connected to the output interface of the bias drive electrode module 102 through a flexible board, and the flexible board is made by a rolled copper process;

[0123] The first active electrode module 103, the second active electrode module 104, the third active electrode module 105, the fourth active electrode module 106, the fifth active electrode module 107, the sixth active electrode module 108, the seventh active electrode module 109 and the eighth active electrode module 120 are used to collect the user's EEG signal;

[0124] The reference electrode 101 is used to collect the reference signal of the EEG signal by connecting to the wet electrode sheet 112 at the mastoid of the user;

[0125] The bias driving electrode module 102 is used to obtain a common mode bias voltage signal corresponding to an EEG signal from a user;

[0126] The rigid-flex active electrode device interconnects the EEG signal, reference signal, common-mode bias voltage signal, and power supply with the EEG signal multi-stage conditioning and amplification device 200 through the interface module 121 .

[0127] in, Fig. 9 The wiring structure diagram of the rigid-flex active electrode device is shown in FIG. The dotted line connection between the electrodes is used to indicate that the circuit connection is made by a flexible board instead of a wire connection. The buffer drive circuit 111 and the wet electrode sheet 112 in the reference electrode 101 are connected by an electrode wire.

[0128] In this example, the interface module 121 is connected to the remaining electrode modules through a flexible board, and the flexible board is made using a rolled copper process, so that the ductility, bending resistance and conductivity of the rigid-flexible active electrode device are better than the conventional electrolytic copper process. At the same time, it also provides a good electrical reference plane for EEG signal transmission, effectively ensuring signal integrity, greatly reducing the electromagnetic interference of EEG signals due to wire transmission, and improving the signal-to-noise ratio of EEG signals.

[0129] In a specific implementation, Fig.10 As shown, the first active electrode module 103 includes a first active electrode 1031 and a first buffer driving circuit, the first buffer driving circuit includes a first gain buffer 321, a first resistor R1, a second resistor R2, a third resistor R3, a thirteenth resistor R13, a thirty-ninth resistor R39, a fifth capacitor C5, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13 and a first electrostatic diode D1, wherein,

[0130] The first active electrode 1031 is connected to the first port, the fifth port, the sixth port, and the tenth port of the first gain buffer 321 through the thirty-ninth capacitor, the first end of the first electrostatic diode D1 is connected between the first active electrode 1031 and the port connected to the thirty-ninth resistor R39, and the second end of the second electrostatic diode is grounded, the second port of the first gain buffer 321 is connected to the output interface of the first active electrode 1031 through the thirteenth resistor R13, the fourth port of the first gain buffer 321 is connected to the output interface of the first active electrode 1031 through the first resistor R1, and the seventh port of the first gain buffer 321 is connected to the first active electrode 1031 through the second resistor R2. The output interface of the first active electrode 1031 is connected to the ninth port of the first gain buffer 321, the ninth port of the first gain buffer 321 is connected to the output interface of the first active electrode 1031 through the third resistor R3, the third port of the first gain buffer 321 is connected to the first end of the fifth capacitor C5, the first end of the tenth capacitor C10, and the first end of the eleventh capacitor C11, the first end of the tenth capacitor C10 and the second end of the eleventh capacitor C11 are connected and then grounded, the eighth port of the first gain buffer 321 is connected to the second end of the fifth capacitor C5, the first end of the twelfth capacitor C12, and the first end of the thirteenth capacitor C13, the second end of the twelfth capacitor C12 is connected to the second end of the thirteenth capacitor C13 and then grounded;

[0131] The eighth port of the first gain buffer 321 is a negative power supply port, and the third port of the first gain buffer 321 is a positive power supply port.

[0132] The negative power supply port is represented by AVSS_-2V5, and the positive power supply port is represented by AVSS_2V5. The output port of the first active electrode module 103 is represented by CH OUT1, and the electrode connection pad is connected to the first active electrode.

[0133] Specifically, the circuit structures of the second active electrode module 104 to the eighth active electrode module 120 are the same as the circuit structure of the first active electrode module 103 .

[0134] The circuit structure of the buffer driving circuit in the reference electrode 101 is the same as the circuit structure of the first buffer driving circuit.

[0135] In this example, a first electrostatic diode D1 is set at the input end of the first gain buffer 321, which can reduce the damage of the first gain buffer 321 caused by electrostatic discharge and improve the safety of the first gain buffer 321; and a plurality of capacitors are set at the positive and negative power supply ports of the first gain buffer 321, which can filter out high-frequency interference in the power supply and improve the stability of the power supply voltage.

[0136] In a specific implementation, the first gain buffer 321 is an AD8244 chip, the first electrostatic diode D1 is an ESD electrostatic diode, the tenth capacitor C10, the eleventh capacitor C11, the twelfth capacitor C12 and the thirteenth capacitor C13 are decoupling capacitors, and the fifth capacitor C5 is a ceramic capacitor.

[0137] Specifically, in a preferred embodiment, the capacity of the tenth capacitor C10 can be 0.1uF, the capacity of the eleventh capacitor C11 can be 4.7uF, the capacity of the twelfth capacitor C12 can be 0.1uF, the capacity of the thirteenth capacitor C13 can be 4.7uF, the capacity of the fifth capacitor C5 can be 4.7uF, and the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the thirteenth resistor R13 can be 51Ω. The above values ​​are only preferred embodiments, not all implementations of the present application, and the parameters that can specifically meet the corresponding performance indicators are in line with the technical solutions of the present application.

[0138] AD8244 is a four-channel unity gain buffer with a maximum bias current of 2pA, a current noise of 0.8fA, a voltage noise of 0.4uVpp, and an input impedance of 10TΩ. Therefore, even if the source impedance is at the MΩ level, there will be no input error due to the load effect. The output resistance of the device is basically zero, and the output voltage has a high load capacity. Fig. 9The structure of the first active electrode module 103 shown uses four buffers in parallel to achieve isolation buffering of one EEG signal. This structure reduces the voltage noise density, and the effective value of the noise is reduced to half of the effective value of the noise when the single buffer is used, thereby improving the signal-to-noise ratio. A small resistor of 51Ω is placed at each buffer output pin, the main purpose of which is to prevent the flow of additional current caused by slight differences between the outputs of each channel, further improving the stability of the signal.

[0139] In a specific implementation, Fig.11 As shown, the bias driving electrode module 102 includes a bias driving electrode 1021, a ninth electrostatic diode D9 and a thirty-third resistor R33, wherein:

[0140] The output end of the bias driving electrode 1021 is connected to the first end of the ninth electrostatic diode D9 and the first end of the thirty-third resistor R33. The second end of the ninth electrostatic diode D9 is grounded. The second end of the thirty-third resistor R33 is the output end of the bias driving electrode module 102.

[0141] The electrode connection pad is connected to a bias driving electrode. The input port of the bias driving electrode module 102 is represented by OUT_BIAS.

[0142] The bias drive electrode module 102 is used to provide an electrical reference point for the user's body. The actual output is the common-mode reference voltage generated by the filter amplification acquisition device, which can reduce the common-mode interference of the EEG signals on the active electrode and the reference electrode 101. The thirty-third resistor R33 is connected in series to ensure impedance matching on the signal transmission link, prevent signal reflection, contribute to signal integrity, and effectively suppress noise interference; the ninth electrostatic diode D9 is terminated at the electrode to avoid the influence of static electricity on the front-stage signal output circuit and improve performance.

[0143] In a specific implementation, the thirty-third resistor R33 is used to perform impedance matching on the bias driving electrode module 102 .

[0144] In a specific implementation, the circuit boards corresponding to the reference electrode 101, the bias drive electrode module 102 and the first active electrode module 103, the second active electrode module 104, the third active electrode module 105, the fourth active electrode module 106, the fifth active electrode module 107, the sixth active electrode module 108, the seventh active electrode module 109, and the eighth active electrode module 120 are FR4 hard boards.

[0145] In a specific implementation, Fig.12As shown, the FR4 hard board adopts a six-layer PCB architecture, and the stack includes a top layer, a GND layer, an intermediate signal layer, a -2.5V power layer, a +2.5V power layer and a bottom layer, wherein:

[0146] The GND layer, the intermediate signal layer, the -2.5V power layer, and the +2.5V power layer are sequentially arranged between the top layer and the bottom layer, the intermediate signal layer is arranged adjacent to the top layer, the +2.5V power layer is arranged adjacent to the bottom layer, and the intermediate signal layer is used for signal transmission.

[0147] Among them, the signals transmitted in the middle layer include EEG signals, reference signals, and common-mode bias voltage signals, etc. The signals are transmitted in the middle signal layer, sandwiched by the complete GND layer and power layer, which provides a good electrical reference plane for EEG signal transmission, effectively guarantees signal integrity, reduces electromagnetic interference to EEG signals caused by wire transmission, and helps improve the signal-to-noise ratio.

[0148] The flexible board adopts a four-layer PCB structure, which is the same as the middle four layers of the FR4 hard board. Fig.12 As described above, the stacking order from top to bottom is GND layer, middle signal layer, -2.5V power layer, +2.5V power layer. The signals on the electrodes are all transmitted in the middle signal layer of the flexible board, sandwiched between the complete GND layer and the power layer, providing a good electrical reference plane for EEG signal transmission, effectively ensuring signal integrity, reducing electromagnetic interference to EEG signals caused by wire transmission, and helping to improve the signal-to-noise ratio.

[0149] The high signal-to-noise ratio dry electrode EEG signal acquisition system provided in the embodiment of the present application has the following operating effects when it is tested and operated:

[0150] During the test, the distance between the subject's eyes and the screen in the SSVEP experiment was about 50 cm, and the experiment used a 27-inch monitor to display the stimulus interface. The experiment included 8 classification tests, and the stimulus frequencies were 8, 9, 10, 11, 12, 13, 14, and 15 Hz. The squares used for stimulation were located around the screen, and the brightness flashed in a sinusoidal form according to the stimulus frequency. At the beginning of each experiment, the prompt time indicating the target stimulus was 1 second, after which the stimulus block began to flash at the stimulus frequency for 5 seconds.

[0151] Perform spectrum analysis on the sampled data. Fig.13 The spectrum diagram of the data with a sampling frequency of 500Hz under a stimulation frequency of 15Hz. Fig.13It can be seen that the EEG signal collected by the dry electrode contains clear stimulation frequency information. At the same time, it can be seen that without 50Hz notch processing, the power frequency interference in the EEG signal is equivalent to the EEG signal amplitude and is not significant, which fully demonstrates that the circuit design effectively suppresses the power frequency noise and achieves the expected design goal.

[0152] Specifically, during the experiment, the specific task classification results are as follows:

[0153] Based on the collected EEG signals, the decoding of the steady-state visual evoked potential brain-computer interface task is performed, and the decoding accuracy of the classic FBCCA algorithm without training is shown in the following table. From the results, it can be seen that a relatively simple decoding algorithm can still achieve a high decoding accuracy in the 8-category task with only 1s of data.

[0154] SSVEP task eight-category test results

[0155] Stimulus data duration 4s 3s 2s 1s Accuracy 97.50％ 97.50％ 90.00％ 65.00％ ITR 41.42 55.22 67.51 65

[0156] The calculation formula of information transmission rate ITR in the table is:

[0157]

[0158] ITR = B*C;

[0159] Where: B is the bit rate, N is the number of selectable targets, P is the target recognition accuracy, C is the number of decisions the system can make per unit time, T is the response time, t s is the model identification time, t b is the sliding window time.

[0160] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0161] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0162] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be electrical or other forms.

[0163] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0164] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A high signal-to-noise ratio dry electrode EEG signal acquisition system, characterized in that: The system includes a rigid-flexible active electrode device and an EEG signal multi-stage conditioning and amplification device, wherein the rigid-flexible active electrode device is connected to the EEG signal multi-stage conditioning and amplification device by using a high-density and ultra-low-height board connector, wherein: The rigid-flexible active electrode device is used to send the collected EEG signal, reference signal and common-mode bias voltage signal to the EEG signal multi-stage conditioning and amplification device through the interface module; The EEG signal multi-stage conditioning and amplification device is used to filter and perform differential amplification processing on the received EEG signal and the reference signal to obtain the final usable EEG signal.

2. The high signal-to-noise ratio dry electrode EEG signal acquisition system according to claim 1, characterized in that: The rigid-flex active electrode device includes a reference electrode, a bias drive electrode module and a first active electrode module, a second active electrode module, a third active electrode module, a fourth active electrode module, a fifth active electrode module, a sixth active electrode module, a seventh active electrode module, an eighth active electrode module and an interface module.

3. The high signal-to-noise ratio dry electrode EEG signal acquisition system according to claim 2, characterized in that: The first active electrode module includes a first active electrode and a first buffer driving circuit, wherein: The first active electrode is used to collect the user's brain electrical signal.

4. The high signal-to-noise ratio dry electrode EEG signal acquisition system according to any one of claims 1 to 3, characterized in that: The EEG signal multi-stage conditioning and amplification device includes a reference signal buffer distribution module, a first-stage filtering module, 8-way first-stage differential amplification modules, a second-stage filtering module, 8-way second-stage differential amplification modules, a bias drive signal generation module and a differential ADC module.

5. The high signal-to-noise ratio dry electrode EEG signal acquisition system according to claim 4, characterized in that: The reference signal buffer distribution module is used to generate 8 identical and independent reference signals according to the reference signal of the collected EEG signal; The first-stage filtering module is used to filter out high-frequency noise and DC bias signals in the EEG signal; The second-stage filtering module is used to filter out high-frequency noise in the EEG signal; The first-stage differential amplifier module is used to perform a first-stage amplification process on the EEG signal; The second-stage differential amplifier module is used to perform secondary amplification processing on the EEG signal. The differential ADC module is used to convert the EEG signal into a digital signal; The gain of the first-stage differential amplifier module is smaller than the gain of the second-stage differential amplifier module.

6. The high signal-to-noise ratio dry electrode EEG signal acquisition system according to claim 5, characterized in that: The bias drive signal generating module is used to generate a common mode reference voltage, and the common mode reference voltage is used to suppress the common mode noise of the electroencephalogram signal.

7. The multi-stage electroencephalogram signal conditioning and amplification device according to claim 5 or 6, characterized in that: The amplification gain value of the first-stage differential amplification module is an amplification gain value between 2 and 10.

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