High signal-to-noise ratio dry electrode electroencephalogram signal acquisition system

Abstract

The embodiment of the application relates to the field of electroencephalogram signal processing and brain-computer interface, and provides a high-signal-to-noise ratio dry electrode electroencephalogram signal acquisition system, the system comprises a rigid-flex active electrode device and an electroencephalogram signal multistage conditioning amplification device, the rigid-flex active electrode device is connected to the electroencephalogram signal multistage conditioning amplification device through a high-density ultra-low-height board connector. Through active signal following and step-by-step conditioning amplification, the signal quality and reliability of the electroencephalogram signal acquisition are improved.

Description

Technical Field

[0001] The present application relates to the technical fields of electroencephalogram (EEG) signal processing and brain-computer interface (BCI), and in particular to a high signal-to-noise ratio (SNR) dry electrode EEG signal acquisition system. Background Art

[0002] Obtaining stable and reliable EEG signals is the premise of scalp brain-computer interface technology. Electroencephalogram (EEG) is the spontaneous bioelectric activity at the scale of brain cell groups. EEG signals are usually very weak, with an amplitude generally between 1 and 100 μV, and are easily interfered with by various physiological and environmental noises, which reduces the signal-to-noise ratio. Among them, electromagnetic interference is the most critical noise, such as the 1 / f noise of the components themselves, the thermal noise generated by the circuit, the 50Hz mains frequency noise, the differential mode noise caused by circuit asymmetry, and the DC bias error. In order to reduce the impact of these noises and improve the signal-to-noise ratio, it is necessary to continuously improve the EEG signal conditioning and acquisition system, which is crucial to improving the accuracy and reliability of EEG signal research.

[0003] In the EEG signal acquisition system, due to the low connection reliability between devices, more noise interference is easily introduced, resulting in poor processing effect of the collected EEG signals. Summary of the Invention

[0004] The embodiment of the present application provides a high signal-to-noise ratio dry electrode EEG signal acquisition system, which improves the signal quality and reliability of EEG signal acquisition through active signal following and step-by-step conditioning and amplification.

[0005] A first aspect of an embodiment of the present application provides a high signal-to-noise ratio dry electrode EEG signal acquisition system, characterized in that the system includes a rigid-flexible active electrode device and an EEG signal multi-stage conditioning and amplification device, wherein the rigid-flexible active electrode device is interconnected through the EEG signal multi-stage conditioning and amplification device using a high-density, ultra-low-height board connector, wherein:

[0006] The rigid-flex active electrode device is used to send the collected EEG signal, reference signal and common-mode bias voltage signal to the EEG signal multi-stage conditioning and amplification device through the interface module;

[0007] The EEG signal multi-stage conditioning and amplification device is used to filter and differentially amplify the received EEG signal and reference signal to obtain the final usable EEG signal.

[0008] In this example, the high signal-to-noise ratio dry electrode EEG signal acquisition system includes a rigid-flexible active electrode device and an EEG signal multi-stage conditioning and amplification device. The rigid-flexible active electrode device is interconnected through the EEG signal multi-stage conditioning and amplification device using a high-density and ultra-low-height board connector. Therefore, the signal quality and reliability of EEG signal acquisition are improved through active signal following and step-by-step conditioning and amplification.

[0009] In one possible implementation, the rigid-flex active electrode device includes a reference electrode, a bias drive electrode module and a first active electrode module, a second active electrode module, a third active electrode module, a fourth active electrode module, a fifth active electrode module, a sixth active electrode module, a seventh active electrode module, an eighth active electrode module and an interface module.

[0010] In a possible implementation, the first movable electrode module includes a first movable electrode and a first buffer drive circuit, wherein:

[0011] The first active electrode is used to collect the user's brain electrical signal.

[0012] In one possible implementation, the EEG signal multi-stage conditioning and amplification device includes a reference signal buffer distribution module, a first-stage filtering module, an 8-channel first-stage differential amplification module, a second-stage filtering module, an 8-channel second-stage differential amplification module, a bias drive signal generation module and a differential ADC module.

[0013] In a possible implementation, the reference signal buffer allocation module is used to generate 8 identical and independent reference signals according to the reference signal of the collected EEG signal;

[0014] The first-stage filtering module is used to filter out high-frequency noise and DC bias signals in the EEG signal;

[0015] The second-stage filtering module is used to filter out high-frequency noise in the EEG signal;

[0016] The first-stage differential amplifier module is used to perform a first-stage amplification processing on the EEG signal;

[0017] The second-stage differential amplifier module is used to perform secondary amplification processing on the EEG signal.

[0018] The differential ADC module is used to convert the EEG signal into a digital signal;

[0019] The gain of the first-stage differential amplification module is smaller than the gain of the second-stage differential amplification module.

[0020] In one possible implementation, the bias drive signal generating module is used to generate a common-mode reference voltage, and the common-mode reference voltage is used to suppress common-mode noise of the EEG signal.

[0021] In a possible implementation, the first-stage differential amplification module has an amplification gain value of 2-10.

[0022] The high signal-to-noise ratio dry electrode electroencephalogram signal acquisition system provided by the embodiment of the application adopts various technical methods to process and correct the electroencephalogram signals, so as to support the acquisition of more accurate electroencephalogram signals. The specific technical methods include the following:

[0023] The driving-amplification separation design:

[0024] In order to guarantee the quality of the electroencephalogram signals, first, the first part needs to design a high-resistance active buffer conditioning circuit (corresponding to the rigid-flex active electrode device) near the scalp, to reduce the influence of the high internal resistance of the electroencephalogram signal source, improve the driving capability of the electroencephalogram signal, and reduce the problem of easy noise interference caused by high contact resistance; then, the second part is a multi-stage conditioning amplification circuit (corresponding to the electroencephalogram signal multi-stage conditioning amplification device), which performs multi-stage filtering and differential amplification processing on the electroencephalogram signals to effectively improve the signal-to-noise ratio. The multi-stage conditioning amplification circuit is interconnected with the rigid-flex active electrode device through a high-density connector. Since the active electrode device realizes driving isolation of the electroencephalogram signal source, this part of the circuit does not have to consider the influence of the high internal resistance characteristics of the electroencephalogram signal source on the circuit, and can be designed and assembled independently of the active electrode device, with strong flexibility and scalability.

[0025] The pre-active driving circuit design:

[0026] The electroencephalogram high-resistance buffer conditioning circuit is equipped with one such circuit (bias driving electrode module) for each dry electrode, which can flexibly realize the design of dry electrode distribution in the brain area and driving isolation transmission of the electroencephalogram signal, and abandon the long wire transmission of the electroencephalogram signal, and adopt a rigid-flex circuit board structure to provide a good reference plane for the electroencephalogram signal, effectively guaranteeing the signal integrity and anti-interference capability. The pre-active driving circuit realizes: ultra-high input impedance, reduces signal attenuation and noise caused by high contact resistance and its changes; reduces the equivalent impedance of the circuit, and reduces the noise introduced by line coupling.

[0027] The step-by-step conditioning amplification design:

[0028] The system utilizes a two-stage passive filter circuit and a two-stage differential amplifier circuit, alternating between the filter and differential amplifier circuits. This effectively filters out noise interference from EEG signals, suppresses common-mode interference, and significantly improves the signal-to-noise ratio. The first stage of the two-stage differential amplifier circuit is a high-impedance, low-gain differential amplifier, which mitigates the effects of the high internal resistance of the preceding filter circuit, suppresses noise, and initially improves the signal-to-noise ratio. The second stage is a high-impedance, high-gain differential amplifier, achieving a secondary improvement in the signal-to-noise ratio. This effectively improves the signal-to-noise ratio through the two-stage differential amplifier circuit.

[0029] Anti-interference design:

[0030] A variety of anti-interference designs are used in circuit design to reduce noise interference. In the PCB design of the rigid-flex active electrode device, a printed shielded circuit design is adopted, with independent power and ground layers, providing a good reference plane for EEG signals and effectively shielding noise interference. In the PCB design of the multi-stage EEG signal conditioning and amplification device, multiple layers of power and ground layers are also used, providing a good reference plane for the multi-stage conditioning and amplification of EEG signals and ensuring signal integrity. Moreover, in the PCB design of the multi-stage EEG signal conditioning and amplification device, the analog circuit and the digital circuit are well laid out and divided, which can effectively avoid interference of the digital circuit on the analog circuit. Both two-stage differential amplifier circuits use low-input noise differential amplifiers with a common-mode rejection ratio of up to 120dB, which can effectively suppress common-mode interference in the circuit and reduce the impact of the circuit's own noise.

[0031] Four-level fitting structure design:

[0032] In order to further ensure that the dry electrode fits well with the scalp and reduce the contact impedance of the dry electrode scalp interface, a flexible comb-shaped electrode and a multi-level adaptive fitting design are used. First, the use of a flexible comb-shaped dry electrode makes it easier for the electrode to pass through the hair and contact the scalp; second, the middle detail design of the dry electrode (active electrode) makes the dry electrode as a whole adaptable; third, the looser structural design of the electrode holder and the flexible active drive electrode design ensure that the electrode can move flexibly in the electrode holder, further improving the adaptability; fourth, the electrode is fixed in an elastic shell, which is designed based on anthropometric head circumference data and fixed with elastic straps to ensure overall fit with different head shapes. The four-level fitting design ensures that the electrode can fit well with the scalp and have a stable contact effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 A schematic structural diagram of a high signal-to-noise ratio dry electrode EEG signal acquisition system is provided for an embodiment of the present application;

[0035] Figure 2 A schematic structural diagram of a multi-stage EEG signal conditioning and amplification device is provided for an embodiment of the present application;

[0036] Figure 3 A schematic structural diagram of a reference signal buffer allocation module is provided for an embodiment of the present application;

[0037] Figure 4 A structural diagram of a first-stage differential amplifier module is provided for an embodiment of the present application;

[0038] Figure 5 A circuit structure diagram of a second-stage differential amplifier module and a differential ADC module is provided for an embodiment of the present application;

[0039] Figure 6 A schematic diagram of the circuit structure of a bias drive signal generating module is provided for an embodiment of the present application;

[0040] Figure 7 A PCB stacking structure diagram of a circuit board of a multi-stage EEG signal conditioning and amplification device is provided for an embodiment of the present application;

[0041] Figure 8 A structural diagram of a rigid-flex active electrode device is provided for an embodiment of the present application;

[0042] Figure 9 A structural schematic diagram of a first movable electrode module is provided for an embodiment of the present application;

[0043] Figure 10 A schematic structural diagram of a bias drive electrode module is provided for an embodiment of the present application;

[0044] Figure 11 A schematic diagram of the architecture of an FR4 hard board is provided for an embodiment of the present application;

[0045] Figure 12 A schematic diagram of the architecture of a flexible board is provided for an embodiment of the present application;

[0046] Figure 13 A schematic diagram of a collected EEG signal is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0048] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0049] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this application may be combined with other embodiments.

[0050] In order to better understand the multi-stage EEG signal conditioning and amplification device provided in the embodiment of the present application, the EEG signal acquisition scheme in the existing scheme is briefly introduced below.

[0051] EEG acquisition and amplification circuits based on wet electrodes are relatively mature. However, wet electrodes have problems such as long preparation time and inconvenience in wearing, which seriously restrict the practical application of brain-computer interfaces. EEG signal acquisition based on dry electrodes, due to the high contact impedance between dry electrodes and the skin, is prone to introducing more noise interference, resulting in a low signal-to-noise ratio of the collected EEG signals, which affects the clarity and accuracy of the signals. In addition, the contact state between the electrodes and the skin may be affected by various factors, such as sweating, oil secretion, and interference from hair, resulting in large signal fluctuations, which places higher requirements on the filtering, amplification, and acquisition of EEG signals.

[0052] Specifically, EEG signal acquisition often faces the following technical difficulties: 1) weak signals, with amplitudes ranging from a few microvolts to several hundred microvolts; 2) high contact impedance; and 3) susceptibility to interference. Tiny signals are susceptible to various noise interferences, while high amplification factors can lead to simultaneous amplification of noise. The high contact impedance of dry electrodes can easily cause signal attenuation and introduce environmental noise into the acquisition process.

[0053] To address the above difficulties, the high signal-to-noise ratio dry electrode EEG signal acquisition system provided in the embodiments of this application improves the signal quality and reliability of EEG signal acquisition through active signal tracking and step-by-step conditioning and amplification. The specific technical solutions include: a separate drive-amplifier design, a pre-active drive circuit design, a step-by-step conditioning and amplification design, an anti-interference design, and a four-stage bonding structure design, as follows:

[0054] Driver-amplifier separation design:

[0055] To ensure EEG signal quality, the first part requires designing a high-impedance active buffer conditioning circuit (corresponding to the rigid-flex active electrode device) close to the scalp to reduce the impact of the high internal resistance of the EEG signal source itself, improve the EEG signal driving capability, and reduce the susceptibility to noise interference caused by high contact impedance. Then, the second part consists of a multi-stage conditioning and amplification circuit (corresponding to the EEG signal multi-stage conditioning and amplification device), which performs multi-stage filtering and differential amplification on the EEG signal to effectively improve the signal-to-noise ratio. The multi-stage conditioning and amplification circuit is interconnected with the rigid-flex active electrode device via a high-density connector. Because the active electrode device achieves drive isolation of the EEG signal source, this part of the circuit no longer needs to consider the impact of the EEG signal source's high internal resistance on the circuit. It can be designed and assembled independently of the active electrode device, with strong flexibility and scalability.

[0056] Front active drive circuit design:

[0057] Each dry electrode is equipped with a high-impedance buffer conditioning circuit (bias drive electrode module), allowing for flexible dry electrode distribution design within the brain and isolated EEG signal transmission. Efforts to transmit EEG signals through long wires are eliminated, and a rigid-flex circuit board structure is employed instead, providing a good reference plane for EEG signals and effectively ensuring signal integrity and anti-interference capabilities. The front active drive circuit achieves: ultra-high input impedance, reducing signal attenuation and noise caused by high contact impedance and its variations; and lowering the equivalent impedance of the circuit, minimizing noise introduced by line coupling.

[0058] Step-by-step adjustment and amplification design:

[0059] The system utilizes a two-stage passive filter circuit and a two-stage differential amplifier circuit, alternating between the filter and differential amplifier circuits. This effectively filters out noise interference from EEG signals, suppresses common-mode interference, and significantly improves the signal-to-noise ratio. The first stage of the two-stage differential amplifier circuit is a high-impedance, low-gain differential amplifier, which mitigates the effects of the high internal resistance of the preceding filter circuit, suppresses noise, and initially improves the signal-to-noise ratio. The second stage is a high-impedance, high-gain differential amplifier, achieving a secondary improvement in the signal-to-noise ratio. This effectively improves the signal-to-noise ratio through the two-stage differential amplifier circuit.

[0060] Anti-interference design:

[0061] A variety of anti-interference designs are used in circuit design to reduce noise interference. In the PCB design of the rigid-flex active electrode device, a printed shielded circuit design is adopted, with independent power and ground layers, providing a good reference plane for EEG signals and effectively shielding noise interference. In the PCB design of the multi-stage EEG signal conditioning and amplification device, multiple layers of power and ground layers are also used, providing a good reference plane for the multi-stage conditioning and amplification of EEG signals and ensuring signal integrity. Moreover, in the PCB design of the multi-stage EEG signal conditioning and amplification device, the analog circuit and the digital circuit are well laid out and divided, which can effectively avoid interference of the digital circuit on the analog circuit. Both two-stage differential amplifier circuits use low-input noise differential amplifiers with a common-mode rejection ratio of up to 120dB, which can effectively suppress common-mode interference in the circuit and reduce the impact of the circuit's own noise.

[0062] Four-level fitting structure design:

[0063] In order to further ensure that the dry electrode fits well with the scalp and reduce the contact impedance of the dry electrode scalp interface, a flexible comb-shaped electrode and a multi-level adaptive fitting design are used. First, the use of a flexible comb-shaped dry electrode makes it easier for the electrode to pass through the hair and contact the scalp; second, the middle detail design of the dry electrode (active electrode) makes the dry electrode as a whole adaptable; third, the looser structural design of the electrode holder and the flexible active drive electrode design ensure that the electrode can move flexibly in the electrode holder, further improving the adaptability; fourth, the electrode is fixed in an elastic shell, which is designed based on anthropometric head circumference data and fixed with elastic straps to ensure overall fit with different head shapes. The four-level fitting design ensures that the electrode can fit well with the scalp and have a stable contact effect.

[0064] See also Figure 1 , Figure 1 The present invention provides a schematic structural diagram of a high signal-to-noise ratio dry electrode EEG signal acquisition system. Figure 1 As shown, the high signal-to-noise ratio dry electrode EEG signal acquisition system 100 includes an EEG signal multi-stage conditioning and amplification device 200 and a rigid-flexible active electrode device 300. The rigid-flexible active electrode device is connected to the EEG signal multi-stage conditioning and amplification device. The rigid-flexible active electrode device is used to send the collected EEG signal and reference signal to the EEG signal multi-stage conditioning and amplification device. The EEG signal multi-stage conditioning and amplification device is used to amplify and condition the received EEG signal, and generate a common-mode bias voltage signal to send to the EEG signal multi-stage conditioning and amplification device.

[0065] The brain electrical signal multi-stage conditioning amplifier 200 greatly improves the signal quality and signal-to-noise ratio of the acquired brain electrical signal after filtering, differential amplification and processing of the received brain electrical signal and the reference signal.

[0066] Specifically, the brain electrical signal multi-stage conditioning amplifier 200 and the rigid-flex active electrode device 300 are connected by high-density ultra-low-height board connectors AXT616124 and AXT516124, the terminals of the connectors are made of copper alloy and are treated with bottom layer Ni plating and surface layer Au plating, and the stability and durability of the contact are improved.

[0067] Please refer to Figure 2 , Figure 2 The application provides a structure diagram of a brain electrical signal multi-stage conditioning amplifier. As shown in Figure 2 The method is applied to a high signal-to-noise ratio dry electrode brain electrical signal acquisition system, and the device comprises a reference signal buffer distribution module 1, a first-stage filter module 2, an 8-way first-stage differential amplifier module 3, a second-stage filter module 4, an 8-way second-stage differential amplifier module 5, a bias driving signal generation module 6 and a differential ADC module 7, wherein

[0068] The signal output port of the reference signal buffer distribution module 1 is connected with the first-type input port of the first filter module, and the second-type input port of the first filter module is the signal receiving port of the 8-way brain electrical signal;

[0069] The 8-way first-type signal output ports of the first-stage filter module are respectively connected with the first input ports of the 8-way first-stage differential amplifier module, and the 8-way second-type signal output ports of the first-stage filter module 2 are respectively connected with the second input ports of the 8-way first-stage differential amplifier module 3,

[0070] The output ports of the 8-way first-stage differential amplifier module 3 are connected with the corresponding 8-way input ports of the second-stage filter module, the 8-way output ports of the second-stage filter module 4 are respectively connected with the input ports of the 8-way second-stage differential amplifier module 5, the first-type output ports of the 8-way second-stage differential amplifier module 5 are connected with the corresponding signal input ports in the differential ADC module 7, the second-type output ports of the 8-way second-stage differential amplifier module 5 are connected with the input ports of the bias driving signal generation module, and the corresponding signal output ports in the differential ADC module 7 are connected with the microprocessor; the output port of the bias driving signal generation module 6 is connected with the bias driving electrode;

[0071] The reference signal buffer distribution module 1 is used for receiving the reference signal of the acquired brain electrical signal, and generating 8-way same and independent reference signals according to the reference signal;

[0072] The gain of the first-stage differential amplification module 3 is smaller than the gain of the second-stage differential amplification module 5 .

[0073] The first-stage filter module 2 includes 16 first-stage sub-filter modules, each of which includes a first-stage low-pass filter circuit and a first-stage high-pass filter circuit. Among the 16 first-stage sub-filter modules, 8 signal input ports are first-class input ports, and the other 8 signal input ports are second-class input ports. The 8 first-stage sub-filter modules of the second-class input ports respectively receive corresponding EEG signals, with a total of 8 EEG signal channels. The 8 first-stage sub-filter modules of the first-class input ports respectively receive reference signals for the corresponding EEG signals. The electrical parameters of the 16 first-stage sub-filter modules are the same. The first-stage low-pass filter circuit is a passive RC low-pass filter circuit; the first-stage high-pass filter circuit can be a passive RC high-pass filter circuit. The output end of the first-stage low-pass filter circuit is connected to the input end of the first-stage high-pass filter circuit.

[0074] The EEG signal passes through a first-stage low-pass filter circuit to attenuate high-frequency interference, and then passes through a first-stage high-pass filter circuit to remove the DC bias component in the signal, thereby retaining the EEG signal in the effective frequency band. At the same time, the reference signal passes through a buffer distribution circuit to generate eight identical and independent reference signals, which serve as differential reference input signals for the eight EEG signals. These signals are then conditioned by low-pass and high-pass filter circuits with the same electrical parameters as the EEG signals. Next, the processed EEG signal of each channel and the corresponding reference signal are input as a differential pair into the first-stage differential amplifier module 3 of the corresponding channel for amplification to improve the signal-to-noise ratio. The output differential signal then passes through a second-stage filter module 4 to further attenuate high-frequency noise in the signal, and then enters a second-stage differential amplifier module 5 for further amplification. Finally, an eight-way parallel differential ADC circuit performs analog-to-digital conversion of the eight EEG signals. Ultimately, the MCU controller realizes the acquisition, transmission and processing of the EEG signals.

[0075] The device also generates and outputs a bias drive signal. This DC bias is applied to the output signal of the second-stage differential amplifier module 5, generating a common-mode voltage signal with opposite polarity via the bias drive circuit. This signal is connected to the human body via the bias drive electrode, providing a common-mode reference voltage for the body and limiting common-mode interference noise to a very narrow range, helping to reduce common-mode interference between the EEG signals at the active and reference electrodes. This signal is extremely weak and will not adversely affect the human body.

[0076] In this example, the EEG signal is filtered by the first-stage filtering module 2 and the EEG signal of the effective frequency band is retained. At the same time, the reference signal is generated by the buffer distribution circuit to generate 8 identical and independent reference signals, which are used as differential reference input signals of the 8 EEG signals respectively. Similarly, after filtering and conditioning consistent with the electrical parameters of the EEG signal, the EEG signal of each channel and the corresponding reference signal are processed as a differential pair and input into the first-stage differential amplifier circuit of the corresponding channel for amplification to improve the signal-to-noise ratio. The output differential signal is then passed through the second-stage low-pass filtering circuit to further attenuate the high-frequency noise in the signal and then enters the second-stage differential amplifier circuit. The differential amplifier circuit amplifies the signal again, and finally an 8-way parallel differential ADC circuit realizes the analog-to-digital conversion of the 8-way EEG signal. Finally, the MCU controller realizes the acquisition, transmission and processing of the EEG signal. At the same time, the bias drive signal generation and output are also realized, that is, the DC bias of the output signal of the second-stage differential amplifier circuit is used to generate a common-mode voltage signal with opposite polarity through the bias drive signal generation module 6. The signal is connected to the human body through the bias drive electrode, providing a common-mode reference voltage for the human body, and limiting the common-mode interference noise to a very narrow range, reducing the common-mode interference of the EEG signal, and further improving the signal-to-noise ratio of the EEG signal.

[0077] In a specific implementation, Figure 3 As shown, the reference signal buffer distribution module 1 includes a first unity gain buffer 11, a second unity gain buffer 12, a 60th capacitor C60, a 61st capacitor C61, a 62nd capacitor C62 and a 63rd capacitor C63, wherein:

[0078] The first port, the fifth port, the sixth port, and the tenth port of the first unity gain buffer 11 are used to receive a reference signal of the EEG signal. The third port of the first unity gain buffer 11 is connected to the positive power supply port and the first end of the 60th capacitor C60, and the second end of the 60th capacitor C60 is grounded. The eighth port of the first unity gain buffer 11 is connected to the negative power supply port and the first end of the 61st capacitor C61, and the second end of the 61st capacitor C61 is grounded. The second port, the fourth port, the seventh port, and the ninth port of the first unity gain buffer 11 are respectively connected to the corresponding first-class input ports in the first filtering module;

[0079] The first port, fifth port, sixth port and tenth port of the second unit gain buffer are used to receive a reference signal of the EEG signal. The third port of the second unit gain buffer 12 is connected to the positive power supply port and the first end of the sixty-second capacitor C62. The second end of the sixty-second capacitor C62 is grounded. The eighth port of the second unit gain buffer 12 is connected to the negative power supply port and the first end of the sixty-third capacitor C63. The second end of the sixty-third capacitor C63 is grounded. The second port, fourth port, seventh port and ninth port of the second unit gain buffer 12 are respectively connected to the corresponding first-class input ports in the first filtering module.

[0080] The input signal of the reference signal buffer distribution module 1 is the reference signal of the EEG signal. After receiving this reference signal, the first unit-gain buffer 11, the second unit-gain buffer 12, and its peripheral circuits generate eight identical and independent reference signals. These eight identical and independent reference signals are respectively input into the corresponding eight first-stage differential amplifier modules 3. The first unit-gain buffer 11 and the second unit-gain buffer 12 are identical unit-gain buffers, specifically AD8244 unit-gain buffers. The ability to generate eight identical and independent reference signals improves the reference signal driving capability and reduces coupling interference between channels.

[0081] In a specific implementation, Figure 4 As shown, the first-stage differential amplifier module 3 includes a first amplifier chip 31, a 168th capacitor C168, a 112th resistor R112, a 169th capacitor C169, a 170th capacitor C170, a 171st capacitor C171, a 172nd capacitor C172, a 173rd capacitor C173, and a 113th resistor R113, wherein:

[0082] A 168th capacitor C168 is connected in parallel between the first signal input port and the second signal input port of the first-stage differential amplifier module 3, and then connected to the first port of the first amplifier chip 31 and the fourth port of the first amplifier chip 31 respectively. A 112th resistor R112 is connected in series between the second port and the third port of the first amplifier chip 31;

[0083] The fifth port of the first amplifier chip 31 is connected to the first end of the 169th capacitor C169 and the positive power supply port, and the second end of the 169th capacitor C169 is grounded;

[0084] The sixth port of the first amplifier chip 31 is connected to the fourteenth port, and the fourteenth port of the first amplifier chip 31 is the second output port of the first-stage differential amplifier module 3;

[0085] The seventh port of the first amplifier chip 31 is grounded, the eighth port of the first amplifier chip 31 is connected to the negative power supply port, the zeroth port, and the first end of the 170th capacitor C170, the second end of the 170th capacitor C170 is grounded, and the ninth port of the first amplifier chip 31 is grounded;

[0086] The twelfth port of the first amplifier chip 31 is connected to the first end of the first-hundred-and-seventy-third capacitor C173 and the first end of the first-hundred-and-thirteenth resistor R113. The second end of the first-hundred-and-thirteenth capacitor C173 is grounded. The second end of the first-hundred-and-thirteenth resistor R113 is connected to the fifteenth port of the first amplifier chip 31. The fifteenth port of the first amplifier chip 31 is the second output port of the first-stage differential amplifier module 3.

[0087] The thirteenth port of the first amplifier chip 31 is connected to the first end of the first-hundred-and-seventy-second capacitor C172 and the negative power supply port, and the second end of the first-hundred-and-seventy-second capacitor C172 is grounded. The sixteenth port of the first amplifier chip 31 is connected to the first end of the first-hundred-and-seventy-first capacitor C171 and the positive power supply port, and the second end of the first-hundred-and-seventy-first capacitor C171 is grounded.

[0088] The first amplifier chip 31 can be a dual-channel precision instrumentation amplifier. The eight first-stage differential amplifier modules 3 have identical electrical parameters. The resulting single-channel fully differential amplifier circuit incorporates an RC low-pass filter circuit consisting of R113 and C173 to ensure the stability of the negative feedback loop.

[0089] In a specific implementation, Figure 2 As shown, the second-stage filtering module 4 includes 8 second sub-filtering modules 41. The electrical parameters of the 8 second sub-filtering modules 41 are the same. The input ports of the 8 second sub-filtering modules 41 are respectively connected to the output ports of the corresponding first-stage differential amplifier modules 3, and the output ports of the 8 second sub-filtering modules 41 are respectively connected to the input ports of the corresponding second-stage differential amplifier modules 5.

[0090] like Figure 4 As shown, the second sub-filtering module 41 includes a 114th resistor R114, a 115th resistor R115, a 174th capacitor C174 and a 175th capacitor C175. The 114th resistor R114 is connected in series between the first output port of the first-stage differential amplifier module 3 and the first end of the 174th capacitor C174. The first end of the 174th capacitor C174 is connected to the first output port of the second sub-filtering module (indicated by AIN7P) between the first end of the 174th capacitor C174 and the 114th resistor R114. The second end of the 174th capacitor C174 is grounded.

[0091] The first-one-hundred-fifteenth resistor R115 is connected in series between the second output port of the first-stage differential amplification module 3 and the first end of the first-one-hundred-seventy-fifth capacitor C175, the second output port of the second sub-filtering module (indicated by AIN7N) is connected between the first end of the first-one-hundred-seventy-fifth capacitor C175 and the first-one-hundred-fifteenth resistor R115, and the second end of the first-one-hundred-seventy-fifth capacitor C175 is grounded.

[0092] The differential output signal then passes through a second-stage passive RC low-pass filter circuit (green box), which can further attenuate high-frequency noise in the differential signal.

[0093] In a specific implementation, Figure 5 As shown, Figure 5 FIG2 shows a schematic diagram of the circuit structure of the second-stage differential amplifier module 5 and the differential ADC module 7. The differential ADC module 7 includes 8 differential ADC circuits, which correspond to the 8 second-stage differential amplifier modules 5, respectively. Figure 5 As shown, a schematic diagram of a second-stage differential amplifier module 5 and a differential ADC circuit is shown. The second-stage differential amplifier module 5 and the differential ADC circuit are implemented by an analog front-end integrated circuit ADS1299. Figure 5 The ADS1299 is a high-performance integrated circuit for physiological signal acquisition. It contains eight low-noise programmable gain amplifiers (PGAs) and eight synchronous sampling analog-to-digital converters (ADCs). Its inputs can be configured as differential inputs, with a common-mode rejection ratio (CMRR) of up to 110dB and a DC input impedance of up to 1GΩ. The PGAs offer selectable gains of 1, 2, 4, 6, 8, 12, and 24. The ADCs offer up to 24-bit accuracy and a selectable sampling rate from 250 SPS to 16k SPS, making them ideal for acquiring weak EEG signals.

[0094] In a specific implementation, Figure 6 As shown, the bias drive signal generating module 6 includes a bias drive amplifier 61, a drive signal source network 62, an external resistor R f , compensation capacitor C f , a first resistor R1 and a second resistor R2, wherein,

[0095] The driving signal source network 62 is connected to the second type output port of the 8-way second stage differential amplifier module 5, and the output port of the driving signal source network 62 is connected to the external resistor R f The first end of the compensation capacitor C f The first end of the bias drive amplifier 61 is connected to the inverting input end of the bias drive amplifier 61, and the external resistor R f The second end of the compensation capacitor C fThe second end of is connected to the output end of the bias driving amplifier 61, the non-inverting input end of the bias driving amplifier 61 is connected to the first end of the first resistor R1 and the first end of the second resistor R2, the second end of the first resistor R1 is connected to the positive power supply port, and the second end of the second resistor R2 is connected to the negative power supply port.

[0096] The driving signal source network 62 includes 8 pairs of R p 1. R n 1, are respectively connected to the corresponding EEG signal differential pairs, and the EEG signal differential pairs are represented as EEG signal 1 differential pair to EEG signal 8 differential pair.

[0097] The bias drive amplifier 61 (BIAS amp) is a built-in bias drive amplifier of the ADS1299. The drive signal source of the drive signal source network 62 comes from the differential signals of the 8 channels of the second-stage differential amplifier circuit, that is, the DC bias in the EEG signals of the 8 channels are superimposed, and a common-mode voltage BIAS_OUT with opposite polarity is generated through the reverse proportional amplification circuit, and then connected to the surface of the human skin through the bias drive electrode to provide the human body with a common-mode reference voltage with opposite polarity. In this way, most of the common-mode interference signals can be offset, thereby achieving suppression of the common-mode noise on the EEG signal at the input end, greatly improving the signal-to-noise ratio of the entire circuit.

[0098] C in the circuit f To compensate for the capacitance, phase compensation is performed on the amplifier circuit to prevent self-oscillation. The positive input of the op amp is half the sum of the positive power supply AVDD and the negative power supply AVSS, thus forming a closed loop.

[0099] In a specific implementation, the capacitance value of the compensation capacitor ranges from 1.5 nF to 500 pF.

[0100] In a specific implementation, the first-stage filtering module 2 includes a low-pass filtering circuit and a high-pass filtering circuit. The cutoff frequency of the low-pass filtering circuit is a frequency value between 1.5KHz and 40kHz, and the cutoff frequency of the high-pass filtering circuit is less than 0.5Hz.

[0101] In a specific implementation, the amplification gain value of the first-stage differential amplification module 3 is an amplification gain value between 2 and 10.

[0102] In a specific implementation, the embodiment of the present application further provides a circuit parameter design scheme for the first-stage filtering module 2, the first-stage differential amplifier module 3, the second-stage filtering module 4, the second-stage differential amplifier module 5, the bias drive signal generating module 6, and the differential ADC module 7, as follows:

[0103] 1) Electrical parameter design of the first-stage filter module 2:

[0104] The first-stage filtering module 2 includes a low-pass filtering circuit and a high-pass filtering circuit. According to actual engineering application experience, this design sets the passband of the band-pass filtering circuit composed of the low-pass and high-pass filtering circuits to be larger, so as to ensure that the wider-band EEG signals enter the post-amplification circuit for processing without attenuation or with little attenuation.

[0105] Depend on Figure 7 It can be seen that in the pre-RC low-pass filter circuit, the resistor R is selected as 4.02kΩ and the capacitor C is selected as 10nF. According to the cut-off frequency calculation formula The low-pass filter circuit's cutoff frequency is approximately 3.9kHz. Based on engineering experience, signals within 0.1 times the cutoff frequency are considered to pass through unattenuated. This means the low-pass filter circuit's unattenuated signal frequency is set to 390Hz, covering the effective frequency range of EEG signals. Experimental verification shows that EEG signal acquisition quality is guaranteed within the low-pass cutoff frequency range of 1.5kHz to 40kHz.

[0106] In the pre-RC high-pass filter circuit, the resistor R is selected as 220kΩ and the capacitor C is selected as 4.7uF. The cut-off frequency is calculated by the formula The high-pass filter circuit's cutoff frequency is approximately 0.15Hz. Based on engineering experience, signals above 10 times the cutoff frequency are considered to pass through unattenuated. This means the high-pass filter circuit's unattenuated signal frequency is set to 1.5Hz, covering the effective frequency range of EEG signals. Experimental verification shows that EEG signal acquisition quality is guaranteed within the high-pass cutoff frequency range of less than 0.5Hz.

[0107] Through comparison of experimental results, the non-attenuation frequency range of the band-pass filter circuit composed of low-pass and high-pass filter circuits was finally set to 1.5Hz to 390Hz.

[0108] 2) Electrical parameter design of the first-stage differential amplifier module 3

[0109] This design uses a two-stage amplifier circuit. In order to avoid reducing the signal-to-noise ratio of the circuit due to excessive amplification noise, the gain of the first-stage amplifier circuit is set lower. Figure 8 As shown, the amplification gain of the first-stage differential amplifier circuit is uniquely determined by the 112th resistor R112. The 112th resistor R112 is set to 12.4 kΩ. According to the gain formula: The calculation shows that the amplification gain is about 5. Experimental verification shows that when the gain of the first-stage amplifier circuit is between 2 and 10, the signal-to-noise ratio index can be maintained at a high level.

[0110] 3) Electrical parameter design of the second-stage filter module 4

[0111] In order to further filter out high-frequency interference in the effective signal, such as Figure 8 As shown, the 114th resistor R114 and the 115th resistor R115 of the second sub-filter module in the second-stage filter module 4 are set to 8.2kΩ, the 174th capacitor C174 and the 175th capacitor C175 are set to 10nF, and the cut-off frequency is calculated by the formula The cutoff frequency of the second sub-filter module is approximately 1.9kHz. Based on engineering experience, signals within 0.1 times the cutoff frequency are considered to pass unattenuated. Therefore, the unattenuated signal frequency of the second sub-filter module is set to 190Hz, which meets the requirements for EEG signal acquisition in the effective frequency band. Experimental verification shows that the quality of EEG signal acquisition is guaranteed within the low-pass cutoff frequency fc range of 1.5kHz to 10kHz. The second sub-filter module is a low-pass filter circuit.

[0112] 4) Electrical parameter design of the second-stage differential amplifier module 5

[0113] The second-stage differential amplifier module 5 is a programmable gain amplifier circuit. Setting the gain of this stage higher increases the dynamic range of the subsequent ADC circuit, improving signal acquisition accuracy. The differential amplifier circuit also further enhances the signal-to-noise ratio. The ADS1299 technical manual indicates that when the gain is set to 24, the ADC circuit's -3dB bandwidth is minimized at approximately 27kHz, which, to a certain extent, suppresses high-frequency noise interference. This results in a total gain of 5 × 24 = 120 for the two-stage amplifier circuit. Experimental verification shows that when the gain of the second-stage differential amplifier module 5 is set between 6, 8, 12, and 24, combined with the gain of the first-stage differential amplifier module 3 between 2 and 10, the total gain of the two-stage amplifier circuit is greater than 40, effectively ensuring signal acquisition quality.

[0114] 5) Differential ADC module 7 electrical parameter design

[0115] This design takes into account the relatively low frequency range of effective EEG signals and the high throughput of eight parallel 24-bit AD acquisition channels. Setting the AD sampling rate higher would place significant pressure on the system's Bluetooth transmission channels, potentially leading to channel blockage, data loss, and overall system instability. Ultimately, the AD sampling rate was set to 500 SPS, which aligned the overall system parameters and ensured high-precision, high-reliability data acquisition and transmission. Experimental verification shows that setting the AD sampling rate between 200 SPS and 1000 SPS effectively ensures data acquisition integrity and data transmission reliability.

[0116] 6) Electrical parameter design of bias drive signal generation module 6

[0117] In order to fully consider and apply the DC bias of the eight EEG signals, the driving signal source of the bias driving circuit is configured as the differential signal of the eight channels from the second-stage differential amplifier module 5. In this way, the DC bias in the EEG signals of the eight channels is superimposed and a common mode voltage with opposite polarity is generated through the reverse proportional amplifier circuit. Figure 10 As shown in the figure, for an AC signal with a frequency of f, the gain formula of the proportional amplifier circuit is: where Z F for: In order to offset most of the common-mode interference, the amplification gain of the bias drive circuit is required to be 1, that is, A=-1.

[0118] According to the ADS1299 manual, R in For 220kΩ, select R F is 1MΩ, Figure 8 The cutoff frequency of the second-stage low-pass filter circuit shown is set to 1.9kHz, and the compensation capacitor C can be calculated. F This parameter setting can provide a common-mode reference voltage with opposite polarity for the human body, effectively suppressing most common-mode interference signals and improving the signal-to-noise ratio of the entire circuit. F The circuit can work normally when the resistance is in the range of 1.5nF to 500pF.

[0119] In a specific implementation, Figure 7 The PCB stacking structure diagram of the circuit board of the multi-stage EEG signal conditioning and amplification device is shown. Figure 7 As shown, it includes a top layer, a first GND layer, an intermediate signal layer, a power layer, a second GND layer and a bottom layer, wherein,

[0120] The first GND layer, the intermediate signal layer, the power layer, and the second GND layer are stacked sequentially between the top layer and the bottom layer, with the first GND layer adjacent to the top layer and the second GND layer adjacent to the bottom layer. The top layer, the intermediate signal layer, and the bottom layer are all used for signal transmission.

[0121] See also Figure 8 , Figure 8 The present invention provides a structural diagram of a rigid-flex active electrode device. Figure 8As shown, the rigid-flex active electrode device 300 includes: a reference electrode 101, a bias drive electrode module 102 and a first active electrode module 103, a second active electrode module 104, a third active electrode module 105, a fourth active electrode module 106, a fifth active electrode module 107, a sixth active electrode module 108, a seventh active electrode module 109, an eighth active electrode module 120 and an interface module 121. The reference electrode 101 includes a buffer drive circuit 111 and a wet electrode sheet 112, wherein:

[0122] The ninth to sixteenth input interfaces of the interface module 121 are respectively connected to the corresponding output interfaces of the first active electrode module 103 to the output interface of the eighth active electrode module 120 via flexible boards. The first interface of the interface module 121 is connected to the output interface of the buffer drive circuit 111 via a flexible board. The input interface of the buffer drive circuit 111 is connected to the wet electrode sheet 112 via an electrode wire. The second interface of the interface module 121 is connected to the output interface of the bias drive electrode module 102 via a flexible board. The flexible board is manufactured using a rolled copper process.

[0123] The first active electrode module 103, the second active electrode module 104, the third active electrode module 105, the fourth active electrode module 106, the fifth active electrode module 107, the sixth active electrode module 108, the seventh active electrode module 109 and the eighth active electrode module 120 are used to collect the user's EEG signals;

[0124] The reference electrode 101 is used to collect the reference signal of the EEG signal by connecting to the wet electrode sheet 112 at the user's mastoid process;

[0125] The bias driving electrode module 102 is used to obtain a common mode bias voltage signal corresponding to an EEG signal from a user;

[0126] The rigid-flex active electrode device interconnects the EEG signal, reference signal, common-mode bias voltage signal, and power supply with the EEG signal multi-stage conditioning and amplification device 200 through the interface module 121 .

[0127] in, Figure 9 Figure 2 shows the wiring structure of a rigid-flex active electrode device. The dotted lines between the electrodes indicate the use of flexible boards for circuit connection, rather than wires. The buffer drive circuit 111 and the wet electrode sheet 112 in the reference electrode 101 are connected via electrode wires.

[0128] In this example, the interface module 121 is connected to the remaining electrode modules through a flexible board, and the flexible board is made using a rolled copper process, so that the ductility, bending resistance and conductivity of the rigid-flexible active electrode device are better than the conventional electrolytic copper process. At the same time, it also provides a good electrical reference plane for EEG signal transmission, effectively ensuring signal integrity, greatly reducing the electromagnetic interference of EEG signals due to wire transmission, and improving the signal-to-noise ratio of EEG signals.

[0129] In a specific implementation, Figure 10 As shown, the first movable electrode module 103 includes a first movable electrode 1031 and a first buffer driving circuit, the first buffer driving circuit includes a first gain buffer 321, a first resistor R1, a second resistor R2, a third resistor R3, a thirteenth resistor R13, a thirty-ninth resistor R39, a fifth capacitor C5, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13 and a first electrostatic diode D1, wherein:

[0130] The first movable electrode 1031 is connected to the first port, the fifth port, the sixth port, and the tenth port of the first gain buffer 321 through the thirty-ninth capacitor. The first end of the first electrostatic diode D1 is connected between the first movable electrode 1031 and the port connected to the thirty-ninth resistor R39. The second end of the second electrostatic diode is grounded. The second port of the first gain buffer 321 is connected to the output interface of the first movable electrode 1031 through the thirteenth resistor R13. The fourth port of the first gain buffer 321 is connected to the output interface of the first movable electrode 1031 through the first resistor R1. The seventh port of the first gain buffer 321 is connected to the first movable electrode 1031 through the second resistor R2. The output interface of the first movable electrode 1031 is connected to the output interface of the first movable electrode 1031, the ninth port of the first gain buffer 321 is connected to the output interface of the first movable electrode 1031 through the third resistor R3, the third port of the first gain buffer 321 is connected to the first end of the fifth capacitor C5, the first end of the tenth capacitor C10, and the first end of the eleventh capacitor C11, the first end of the tenth capacitor C10 and the second end of the eleventh capacitor C11 are connected and then grounded, the eighth port of the first gain buffer 321 is connected to the second end of the fifth capacitor C5, the first end of the twelfth capacitor C12, and the first end of the thirteenth capacitor C13, the second end of the twelfth capacitor C12 and the second end of the thirteenth capacitor C13 are connected and then grounded;

[0131] The eighth port of the first gain buffer 321 is a negative power supply port, and the third port of the first gain buffer 321 is a positive power supply port.

[0132] The negative power supply port is represented by AVSS_-2V5, and the positive power supply port is represented by AVSS_2V5. The output port of the first active electrode module 103 is represented by CH OUT1, and the electrode connection pad is connected to the first active electrode.

[0133] Specifically, the circuit structures of the second movable electrode module 104 to the eighth movable electrode module 120 are the same as the circuit structure of the first movable electrode module 103 .

[0134] The circuit structure of the buffer driving circuit in the reference electrode 101 is the same as the circuit structure of the first buffer driving circuit.

[0135] In this example, a first electrostatic diode D1 is provided at the input end of the first gain buffer 321, which can reduce the damage to the first gain buffer 321 caused by electrostatic discharge and improve the safety of the first gain buffer 321; and multiple capacitors are provided at the positive and negative power supply ports of the first gain buffer 321, which can filter out high-frequency interference in the power supply and improve the stability of the power supply voltage.

[0136] In a specific implementation, the first gain buffer 321 is an AD8244 chip, the first electrostatic diode D1 is an ESD electrostatic diode, the tenth capacitor C10, the eleventh capacitor C11, the twelfth capacitor C12 and the thirteenth capacitor C13 are decoupling capacitors, and the fifth capacitor C5 is a ceramic capacitor.

[0137] Specifically, in a preferred embodiment, the capacity of the tenth capacitor C10 can be 0.1uF, the capacity of the eleventh capacitor C11 can be 4.7uF, the capacity of the twelfth capacitor C12 can be 0.1uF, the capacity of the thirteenth capacitor C13 can be 4.7uF, the capacity of the fifth capacitor C5 can be 4.7uF, and the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the thirteenth resistor R13 can be 51Ω. The above values ​​are only preferred embodiments and not all implementations of the present application. The parameters that can specifically meet the corresponding performance indicators are in line with the technical solutions of the present application.

[0138] The AD8244 is a four-channel unity-gain buffer with a maximum bias current of 2pA, a current noise of 0.8fA, a voltage noise of 0.4uVpp, and an input impedance of 10TΩ. Therefore, even if the source impedance is at the MΩ level, there will be no input error due to the load effect. The output resistance of this device is essentially zero, and the output voltage has a high load capacity. Figure 9The structure of the first active electrode module 103 shown uses four parallel buffers to isolate and buffer one EEG signal. This structure reduces voltage noise density, reducing the effective noise value to half that of a single buffer, thereby improving the signal-to-noise ratio. A small 51Ω resistor is placed at each buffer output pin to prevent additional current flow caused by slight differences between the outputs, further improving signal stability.

[0139] In a specific implementation, Figure 11 As shown, the bias driving electrode module 102 includes a bias driving electrode 1021, a ninth electrostatic diode D9 and a thirty-third resistor R33, wherein:

[0140] The output end of the bias driving electrode 1021 is connected to the first end of the ninth electrostatic diode D9 and the first end of the thirty-third resistor R33. The second end of the ninth electrostatic diode D9 is grounded. The second end of the thirty-third resistor R33 is the output end of the bias driving electrode module 102.

[0141] The electrode connection pad is connected to a bias driving electrode. The input port of the bias driving electrode module 102 is represented by OUT_BIAS.

[0142] The bias drive electrode module 102 provides an electrical reference point for the user's body. It actually outputs a common-mode reference voltage generated by the filtering, amplification, and acquisition device, which reduces common-mode interference between the EEG signals at the active and reference electrodes 101. The series connection of resistor R33 ensures impedance matching in the signal transmission link, preventing signal reflections and contributing to signal integrity while also effectively suppressing noise interference. The connection of diode D9 to the electrode terminals prevents static electricity from affecting the preceding signal output circuit, improving performance.

[0143] In a specific implementation, the thirty-third resistor R33 is used to perform impedance matching on the bias driving electrode module 102 .

[0144] In a specific implementation, the circuit boards corresponding to the reference electrode 101, the bias drive electrode module 102 and the first active electrode module 103, the second active electrode module 104, the third active electrode module 105, the fourth active electrode module 106, the fifth active electrode module 107, the sixth active electrode module 108, the seventh active electrode module 109, and the eighth active electrode module 120 are FR4 hard boards.

[0145] In a specific implementation, Figure 12As shown, the FR4 hard board adopts a six-layer PCB structure, and the stack includes a top layer, a GND layer, an intermediate signal layer, a -2.5V power layer, a +2.5V power layer and a bottom layer, wherein,

[0146] The GND layer, the intermediate signal layer, the -2.5V power layer, and the +2.5V power layer are sequentially arranged between the top layer and the bottom layer. The intermediate signal layer is arranged adjacent to the top layer, and the +2.5V power layer is arranged adjacent to the bottom layer. The intermediate signal layer is used for signal transmission.

[0147] The signals transmitted in the middle layer include EEG signals, reference signals, and common-mode bias voltage signals. Signals are transmitted in the middle signal layer, sandwiched between the intact GND layer and power layer. This provides a good electrical reference plane for EEG signal transmission, effectively ensuring signal integrity and reducing electromagnetic interference caused by wire transmission on EEG signals, thereby improving the signal-to-noise ratio.

[0148] The flexible board adopts a four-layer PCB structure, which is the same as the middle four layers of the FR4 hard board. Figure 12 The stacking order from top to bottom is GND layer, intermediate signal layer, -2.5V power layer, and +2.5V power layer. The signals from the electrodes are all transmitted in the intermediate signal layer of the flexible board, sandwiched between the intact GND and power layers. This provides a good electrical reference plane for EEG signal transmission, effectively ensuring signal integrity, reducing electromagnetic interference caused by wire transmission, and helping to improve the signal-to-noise ratio.

[0149] The high signal-to-noise ratio dry electrode EEG signal acquisition system provided in the embodiment of the present application has the following operating effects when it is tested and operated:

[0150] During the SSVEP experiment, subjects maintained a distance of approximately 50 cm between their eyes and the screen, and the stimulus interface was displayed on a 27-inch monitor. The experiment included an eight-category test, with stimulus frequencies of 8, 9, 10, 11, 12, 13, 14, and 15 Hz. Stimulus squares were positioned around the screen, and their brightness flashed sinusoidally at the stimulus frequency. Each trial began with a 1-second cue indicating the target stimulus, after which the stimulus block began flashing at the stimulus frequency for 5 seconds.

[0151] Perform spectrum analysis on the sampled data. Figure 13 The spectrum of the data with a sampling frequency of 500Hz under a stimulation frequency of 15Hz is shown in Figure 2. Figure 13It can be seen that the EEG signal collected by the dry electrode contains clear stimulation frequency information. At the same time, it can be seen that without 50Hz notch processing, the power frequency interference in the EEG signal is comparable to the EEG signal amplitude and is not significant. This fully demonstrates that the circuit design effectively suppresses the power frequency noise and achieves the expected design goal.

[0152] Specifically, during the experiment, the specific task classification results are as follows:

[0153] The following table shows the decoding accuracy of the steady-state visual evoked potential (SVP) brain-computer interface task using the collected EEG signals, using the classic, untrained FBCCA algorithm. These results demonstrate that a relatively simple decoding algorithm can achieve high decoding accuracy in the 8-category task using only 1 second of data.

[0154] SSVEP task eight-category test results

[0155] Stimulation data duration 4s 3s 2s 1s Accuracy 97.50％ 97.50％ 90.00％ 65.00％ ITR 41.42 55.22 67.51 65

[0156] The calculation formula for the information transmission rate ITR in the table is:

[0157]

[0158] ITR = B*C;

[0159] Where: B is the bit rate, N is the number of selectable targets, P is the target recognition accuracy, C is the number of decisions the system can make per unit time, T is the response time, t s is the model identification time, t b is the sliding window time.

[0160] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0161] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0162] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0163] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0164] The above is a detailed introduction to the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A high signal-to-noise ratio dry electrode EEG signal acquisition system, characterized in that: The system includes a rigid-flex active electrode device and an EEG signal multi-stage conditioning and amplification device, wherein the rigid-flex active electrode device is interconnected through the EEG signal multi-stage conditioning and amplification device using a high-density and ultra-low-height board connector, wherein: The rigid-flex active electrode device is used to send the collected EEG signal, reference signal and common-mode bias voltage signal to the EEG signal multi-stage conditioning and amplification device through the interface module; The EEG signal multi-stage conditioning and amplification device is used to filter and differentially amplify the received EEG signal and the reference signal to obtain the final usable EEG signal; The device includes a reference signal buffer distribution module, a first-stage filtering module, an 8-way first-stage differential amplifier module, a second-stage filtering module, an 8-way second-stage differential amplifier module, a bias drive signal generation module and a differential ADC module; The reference signal buffer distribution module includes a first unity gain buffer, a second unity gain buffer, a sixtieth capacitor, a sixtieth capacitor, a sixtieth capacitor, a sixtieth capacitor, and a sixtieth capacitor; The bias drive signal generating module includes a bias drive amplifier, a drive signal source network, an external resistor Rf, a compensation capacitor Cf, a first resistor R1 and a second resistor R2; The rigid-flex active electrode device includes: a reference electrode, a bias drive electrode module and a first active electrode module, a second active electrode module, a third active electrode module, a fourth active electrode module, a fifth active electrode module, a sixth active electrode module, a seventh active electrode module, an eighth active electrode module and an interface module. The reference electrode includes a buffer drive circuit and a wet electrode sheet, wherein: The ninth to sixteenth input interfaces of the interface module are respectively connected to the output interfaces of the first to eighth active electrode modules via flexible boards; the first interface of the interface module is connected to the output interface of the buffer drive circuit via a flexible board; the input interface of the buffer drive circuit is connected to the wet electrode sheet via an electrode conductor; the second interface of the interface module is connected to the output interface of the bias drive electrode module via a flexible board, and the flexible board is manufactured using a rolled copper process; The first active electrode module, the second active electrode module, the third active electrode module, the fourth active electrode module, the fifth active electrode module, the sixth active electrode module, the seventh active electrode module and the eighth active electrode module are used to collect the user's electroencephalogram (EEG) signals; The circuit boards corresponding to the reference electrode, the bias drive electrode module, and the first movable electrode module, the second movable electrode module, the third movable electrode module, the fourth movable electrode module, the fifth movable electrode module, the sixth movable electrode module, the seventh movable electrode module, and the eighth movable electrode module are FR4 hard boards; The FR4 hard board adopts a six-layer PCB structure, and the stack includes a top layer, a GND layer, a middle signal layer, a -2.5V power layer, a +2.5V power layer and a bottom layer.

2. The high signal-to-noise ratio dry electrode EEG signal acquisition system according to claim 1, characterized in that: The first movable electrode module includes a first movable electrode and a first buffer driving circuit, wherein: The first active electrode is used to collect the user's brain electrical signal.

3. The high signal-to-noise ratio dry electrode EEG signal acquisition system according to claim 2, characterized in that: The reference signal buffer distribution module is used to generate 8 identical and independent reference signals according to the reference signal of the collected EEG signal; The first-stage filtering module is used to filter out high-frequency noise and DC bias signals in the EEG signal; The second-stage filtering module is used to filter out high-frequency noise in the EEG signal; The first-stage differential amplifier module is used to perform a first-stage amplification processing on the EEG signal; The second-stage differential amplifier module is used to perform secondary amplification processing on the EEG signal; The differential ADC module is used to convert the EEG signal into a digital signal; The gain of the first-stage differential amplification module is smaller than the gain of the second-stage differential amplification module.

4. The high signal-to-noise ratio dry electrode EEG signal acquisition system according to claim 3, characterized in that: The bias drive signal generating module is used to generate a common mode reference voltage, and the common mode reference voltage is used to suppress the common mode noise of the EEG signal.

5. The multi-stage EEG signal conditioning and amplification device according to claim 3 or 4, characterized in that: The amplification gain value of the first-stage differential amplification module is an amplification gain value between 2 and 10.

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