Equipment testing system and method

Abstract

The invention relates to the technical field of equipment testing, and discloses an equipment testing system and method.The equipment testing system comprises a computer, a card reader, tested equipment, a control unit and a feedback unit; the computer is in communication connection with the card reader, and the computer is configured to issue a test instruction; the card reader is in communication connection with the tested equipment, and the card reader is configured to perform signal interaction with the tested equipment according to the test instruction; the feedback unit is arranged in the tested equipment, the control unit is in communication connection with the card reader and the feedback unit, the feedback unit is configured to feed back working parameter information of the tested equipment to the control unit, and the control unit is configured to test the tested equipment based on the working parameter information. The feedback unit can feed back the working parameter information comprehensively in real time, the control unit tests the tested equipment based on the working parameter information, the accuracy and efficiency of equipment testing can be remarkably improved, and the high-precision and high-efficiency testing requirements are met.

Description

Technical Field

[0001] The present disclosure relates to the technical field of device testing, for example, to a device testing system and method. Background Art

[0002] In device testing scenarios, especially for testing of devices under test such as smart cards, the card reader usually needs to obtain the operating parameter information of the device under test to evaluate its performance and reliability. Currently, there are two main ways to obtain this operating parameter information:

[0003] The card reader actively sends commands: The card reader actively sends commands to request the device under test to return its current working parameter information. However, due to the time delay between command sending and response, it is impossible to obtain real-time working parameter information in time. Moreover, the types of working parameter information obtained through commands are limited and cannot cover all possible status information.

[0004] Card reader monitoring current or power consumption: The card reader indirectly infers the working parameter information of the device under test by monitoring the current or power consumption data. However, there is also a time delay in the collection and processing of monitoring data, and real-time monitoring cannot be achieved. The types of working parameter information indirectly obtained through current or power consumption data are limited, and it is difficult to fully reflect the actual working status of the device.

[0005] In summary, the related art methods of obtaining working parameter information have obvious deficiencies in terms of real-time performance and information types, and cannot meet the testing requirements of high precision and high efficiency.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a device testing system and method, which can significantly improve the accuracy and efficiency of device testing and meet the testing requirements of high precision and high efficiency.

[0009] According to a first aspect of the present disclosure, there is provided a device testing system, comprising a computer, a card reader, a device under test, a control unit, and a feedback unit;

[0010] The computer is connected to the card reader for communication, and the computer is configured to issue a test instruction;

[0011] The card reader is in communication connection with the device under test, and the card reader is configured to perform signal interaction with the device under test according to the test instruction;

[0012] The feedback unit is arranged in the device under test, the control unit is respectively connected to the card reader and the feedback unit for communication, the feedback unit is configured to actively feed back the working parameter information of the device under test to the control unit, and the control unit is configured to test the device under test based on the working parameter information.

[0013] In some embodiments, the operating parameter information includes the start and end times of the memory erase and write operations of the device under test;

[0014] The feedback unit is configured to actively feed back the start and end time information of the memory erase and write operation of the device under test to the control unit;

[0015] The control unit is configured to determine the execution time period of the memory erase and write operation based on the start and end time information, and control the card reader to perform a power-off test on the device under test during the execution time period.

[0016] In some embodiments, the operating parameter information includes page addresses involved in memory erase and write operations of the device under test;

[0017] The feedback unit is configured to actively feed back to the control unit a page address involved in a memory erase and write operation of the device under test;

[0018] The control unit is configured to count the number of erase and write times of each page in the memory based on the page address, and evaluate the wear leveling status of the memory based on the number of erase and write times of each page.

[0019] In some embodiments, the operating parameter information includes debugging information of the device under test;

[0020] The feedback unit is configured to actively feed back debugging information of the device under test to the control unit;

[0021] The control unit is configured to perform error analysis or test control based on the debugging information.

[0022] In some embodiments, the communication interface between the card reader and the device under test includes any one of the following: ISO / IEC7816 interface, SPI, and I2C interface.

[0023] In some embodiments, the communication interface between the control unit and the feedback unit includes any one of the following: GPIO interface, UART interface, SPI, I2C interface.

[0024] In some embodiments, the control unit is a separate unit disposed outside the card reader.

[0025] In some embodiments, the control unit is disposed within the card reader.

[0026] According to a second aspect of the present disclosure, a device testing method is provided, which is applied to the device testing system provided in the first aspect of the present disclosure. The device testing method includes:

[0027] The computer issues test instructions;

[0028] The card reader exchanges signals with the device under test according to the test instructions;

[0029] The feedback unit actively feeds back the working parameter information of the device under test to the control unit;

[0030] The control unit tests the device under test based on the operating parameter information.

[0031] In some embodiments, the operating parameter information includes the start and end times of the memory erase and write operations of the device under test;

[0032] The feedback unit actively feeds back the working parameter information of the device under test to the control unit, including: the feedback unit actively feeds back the start and end time information of the memory erase and write operation of the device under test to the control unit;

[0033] The control unit tests the device under test based on the working parameter information, including: the control unit determines the execution time period of the memory erase and write operation based on the start and end time information, and controls the card reader to perform a power-off test on the device under test during the execution time period.

[0034] In some embodiments, the operating parameter information includes page addresses involved in memory erase and write operations of the device under test;

[0035] The feedback unit actively feeds back the working parameter information of the device under test to the control unit, including: the feedback unit actively feeds back the page address involved in the memory erase and write operation of the device under test to the control unit;

[0036] The control unit tests the device under test based on the working parameter information, including: the control unit counts the number of erase and write times of each page in the memory based on the page address, and evaluates the wear leveling of the memory based on the number of erase and write times of each page.

[0037] In some embodiments, the operating parameter information includes debugging information of the device under test;

[0038] The feedback unit actively feeds back the working parameter information of the device under test to the control unit, including: the feedback unit actively feeds back the debugging information of the device under test to the control unit;

[0039] The control unit tests the device under test based on the working parameter information, including: the control unit performs error analysis or test control based on the debugging information.

[0040] The device testing system and method provided by the embodiments of the present disclosure can achieve the following technical effects:

[0041] The device testing system provided by the embodiment of the present disclosure introduces an active feedback mechanism by configuring a control unit and a feedback unit. The feedback unit monitors the working parameter information of the device under test in real time and actively feeds back the working parameter information of the device under test to the control unit, eliminating the time delay between command sending and response, and realizing true real-time monitoring. Moreover, the feedback unit embedded in the device under test can collect various types of working parameter information, expand the types of information obtained, and fully reflect the actual working status of the device under test. The control unit can test the device under test based on the working parameter information, which can significantly improve the accuracy and efficiency of the device test and meet the testing requirements of high precision and high efficiency.

[0042] The foregoing general description and the following description are exemplary and explanatory only and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0044] Figure 1 is a schematic diagram of a device testing system provided by an embodiment of the present disclosure;

[0045] Figure 2 is a schematic diagram of another device testing system provided by an embodiment of the present disclosure;

[0046] Figure 3 It is a schematic diagram of the feedback unit according to an embodiment of the present disclosure feeding back the start time and end time of the memory erase and write operation;

[0047] Figure 4 It is a schematic diagram of a feedback unit provided in an embodiment of the present disclosure feeding back a page address involved in a memory erase and write operation of a device under test;

[0048] Figure 5 is a schematic diagram of a device testing method provided by an embodiment of the present disclosure;

[0049] Figure 6 It is a schematic diagram of a computer provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0051] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0052] Unless otherwise stated, the term "plurality" means two or more.

[0053] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0054] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0055] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0056] Combination Figure 1 and Figure 2 As shown, an embodiment of the present disclosure provides a device testing system, including a computer, a card reader, a device under test, a control unit, and a feedback unit.

[0057] The computer is connected to the card reader for communication, and the computer is configured to issue a test instruction. The card reader is connected to the device under test for communication, and the card reader is configured to perform signal interaction with the device under test according to the test instruction.

[0058] The computer, as the main control terminal, is responsible for configuring test parameters, starting tests, monitoring the test process, and analyzing test results. The computer can interact with the user through the software interface, allowing the user to input test requirements and expected goals.

[0059] The card reader can be used to read and write data stored in various types of cards, tags or other storage media. The card reader interacts with these storage media through a specific communication interface and is widely used in finance, transportation, access control, payment, logistics and other fields. Specifically, the card reader can read data from storage media, such as smart cards, NFC (Near Field Communication) tags, magnetic stripe cards, etc. The card reader can write data to the storage medium, such as user information, transaction records, etc. The card reader can perform identity authentication and security authentication to ensure the integrity and security of the data. The card reader can monitor the status of the storage medium, such as the remaining storage space, battery power, etc. The device under test can be a smart card, NFC tag, embedded security module, and terminal supporting NFC function. The communication interface between the card reader and the device under test includes any of the following: ISO / IEC7816 interface, SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit) interface.

[0060] Alternatively, if Figure 1 As shown, the control unit is an independent unit arranged outside the card reader.

[0061] Alternatively, if Figure 2 As shown, the control unit is arranged in the card reader.

[0062] The feedback unit is arranged in the device under test, and the control unit is respectively connected to the card reader and the feedback unit for communication. The communication interface between the control unit and the feedback unit includes any one of the following: GPIO (General Purpose Input / Output) interface, UART (Universal Asynchronous Receiver-Transmitter) interface, SPI, I2C interface.

[0063] The feedback unit and the control unit are both internally deployed with software programs, and the feedback unit and the control unit can realize corresponding functions through the software programs inside the actuator. Specifically, the feedback unit is configured to actively feed back the working parameter information of the device under test to the control unit, and the control unit is configured to test the device under test based on the working parameter information.

[0064] The device testing system provided by the embodiment of the present disclosure introduces an active feedback mechanism by configuring a control unit and a feedback unit. The feedback unit monitors the working parameter information of the device under test in real time and actively feeds back the working parameter information of the device under test to the control unit, eliminating the time delay between command sending and response, and realizing true real-time monitoring. Moreover, the feedback unit embedded in the device under test can collect various types of working parameter information, expand the types of information obtained, and fully reflect the actual working status of the device under test. The control unit tests the device under test based on real-time and comprehensive working parameter information, which can significantly improve the accuracy and efficiency of the device test and meet the testing requirements of high precision and high efficiency.

[0065] In some embodiments, the working parameter information includes the start and end time of the memory erase and write operation of the device under test. The feedback unit is configured to actively feed back the start and end time information of the memory erase and write operation of the device under test to the control unit. The control unit is configured to determine the execution time period of the memory erase and write operation based on the start and end time information, and control the card reader to perform a power-off test on the device under test during the execution time period.

[0066] Memory erase and write operation refers to the process of writing and erasing data to the memory in the device under test. The memory in the device under test includes Flash, EEPROM (Electrically Erasable Programmable Read-Only Memory), SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), etc.

[0067] In the embodiment of the present disclosure, the start and end time of the memory erase and write operation includes the start time and the end time of the memory erase and write operation. Figure 3A schematic diagram showing the feedback unit feeding back the start time and end time of two memory erase and write operations, wherein, when the memory erase and write operation starts, the level output by the feedback unit changes from V1 to 0; when the memory erase and write operation ends, the level output by the feedback unit changes from 0 to V1. t1start represents the start time of the first memory erase and write operation, t1end represents the end time of the first memory erase and write operation, t2start represents the start time of the second memory erase and write operation, and t2end represents the end time of the second memory erase and write operation. The control unit can determine the execution time period of the memory erase and write operation based on the start time and end time of the memory erase and write operation. It can be understood that the time period between t1start and t1end is the execution time period of the first memory erase and write operation, and the time period between t2start and t2end is the execution time period of the second memory erase and write operation.

[0068] In the embodiment of the present disclosure, after the control unit determines the execution time period of the memory erase and write operation based on the start and end time information, the control unit can send a notification to the card reader to start the power-off test, and the card reader can perform a power-off test on the device under test during the execution time period after receiving the notification. By performing a power-off test on the device under test during the execution time period, it is possible to more realistically simulate the situation that the user may encounter in actual use, ensuring that the device can still maintain data consistency and integrity when encountering an unexpected power outage, thereby improving the reliability of the product and user experience. At the same time, since performing a power-off test on the device under test during the execution time period can more realistically simulate the situation of encountering an unexpected power outage, performing a power-off test on the device under test only during the execution time period and not during other time periods can reduce invalid testing processes and improve the efficiency of the power-off test.

[0069] In some embodiments, the operating parameter information includes a page address involved in a memory erase and write operation of the device under test. The feedback unit is configured to actively feed back to the control unit the page address involved in the memory erase and write operation of the device under test. The control unit is configured to count the number of erase and write times of each page in the memory based on the page address, and evaluate the wear leveling of the memory based on the number of erase and write times of each page.

[0070] In the disclosed embodiment, a block is the basic erase unit of a memory, and a block contains multiple pages. A page is the basic write unit of a memory, and a page contains multiple bytes. A page address is a unique address of each page in the memory, which is used to identify the location of the page.

[0071] Figure 4The schematic diagram shows the feedback unit feeding back the page address involved in the memory erase and write operation of the device under test, wherein when the level is V2, it means that the memory erase and write operation is being performed, and when the level is 0, it means that the memory erase and write operation is not being performed. Figure 4 In the test, a total of three memory erase and write operations were performed. Each time a memory erase and write operation was performed, the feedback unit actively fed back the page address involved in the memory erase and write operation of the device under test to the control unit. After receiving the page address involved in the memory erase and write operation, the control unit determines the number of erase and write times of each page in the memory by counting the page addresses. After obtaining the number of erase and write times of each page in the memory, the control unit evaluates the wear leveling of the memory based on the number of erase and write times of each page.

[0072] In the disclosed embodiment, the total number of erase times of all pages in the memory and the total number of pages in the memory are counted based on the number of erase times of each page, and then the average number of erase times of each page is calculated. Based on the number of erase times of each page, the page with the most erase times and the page with the least erase times are determined, and the standard deviation of the number of erase times of each page is calculated based on the number of erase times of the page with the most erase times and the number of erase times of the page with the least erase times. The standard deviation of the number of erase times of each page can evaluate the discreteness of the number of erase times.

[0073] In the disclosed embodiment, after determining the average number of erase and write times and the standard deviation of the number of erase and write times per page, the wear leveling is evaluated based on the average number of erase and write times and the standard deviation of the number of erase and write times per page. Optionally, the ratio of the standard deviation of the number of erase and write times per page to the average number of erase and write times can be calculated, and the ratio is used as a uniformity index. The smaller the uniformity index, the more uniform the distribution of the number of erase and write times, and the better the wear leveling; the larger the uniformity index, the uneven distribution of the number of erase and write times, and the serious wear of some pages, which may shorten the life of the memory.

[0074] In some embodiments, the working parameter information includes debugging information of the device under test, wherein the debugging information may include error information, key variable values, program execution order, etc. The feedback unit is configured to actively feed back the debugging information of the device under test to the control unit. The control unit is configured to perform error analysis or test control based on the debugging information.

[0075] In combination with the device testing system provided by the embodiment of the present disclosure, the embodiment of the present disclosure provides a device testing method, in combination with Figure 5 As shown, the device testing method includes:

[0076] S501, the computer sends a test instruction.

[0077] S502, the card reader performs signal interaction with the device under test according to the test instruction.

[0078] S503: The feedback unit actively feeds back the operating parameter information of the device under test to the control unit.

[0079] S504: The control unit tests the device under test based on the working parameter information.

[0080] The device testing method provided by the embodiment of the present disclosure introduces an active feedback mechanism based on the control unit and feedback unit configured in the device testing system. The feedback unit monitors the working parameter information of the device under test in real time and actively feeds back the working parameter information of the device under test to the control unit, eliminating the time delay between command sending and response, and realizing true real-time monitoring. Moreover, the feedback unit embedded in the device under test can collect various types of working parameter information, expand the types of information obtained, and fully reflect the actual working status of the device under test. The control unit tests the device under test based on real-time and comprehensive working parameter information, which can significantly improve the accuracy and efficiency of the device test and meet the testing requirements of high precision and high efficiency.

[0081] In some embodiments, the operating parameter information includes the start and end time of the memory erase and write operations of the device under test.

[0082] The feedback unit actively feeds back the working parameter information of the device under test to the control unit, including: the feedback unit actively feeds back the start and end time information of the memory erase and write operation of the device under test to the control unit.

[0083] The control unit tests the device under test based on the working parameter information, including: the control unit determines the execution time period of the memory erase and write operation based on the start and end time information, and controls the card reader to perform a power-off test on the device under test during the execution time period.

[0084] In the embodiment of the present disclosure, the start and end time of the memory erase and write operation includes the start time and the end time of the memory erase and write operation. Figure 3 A schematic diagram showing the feedback unit feeding back the start time and end time of two memory erase and write operations, wherein, when the memory erase and write operation starts, the level output by the feedback unit changes from V1 to 0; when the memory erase and write operation ends, the level output by the feedback unit changes from 0 to V1. t1start represents the start time of the first memory erase and write operation, t1end represents the end time of the first memory erase and write operation, t2start represents the start time of the second memory erase and write operation, and t2end represents the end time of the second memory erase and write operation. The control unit can determine the execution time period of the memory erase and write operation based on the start time and end time of the memory erase and write operation. It can be understood that the time period between t1start and t1end is the execution time period of the first memory erase and write operation, and the time period between t2start and t2end is the execution time period of the second memory erase and write operation.

[0085] In the embodiment of the present disclosure, after the control unit determines the execution time period of the memory erase and write operation based on the start and end time information, the control unit can send a notification to the card reader to start the power-off test, and the card reader can perform a power-off test on the device under test during the execution time period after receiving the notification. By performing a power-off test on the device under test during the execution time period, it is possible to more realistically simulate the situation that the user may encounter in actual use, ensuring that the device can still maintain data consistency and integrity when encountering an unexpected power outage, thereby improving the reliability of the product and user experience. At the same time, since performing a power-off test on the device under test during the execution time period can more realistically simulate the situation of encountering an unexpected power outage, performing a power-off test on the device under test only during the execution time period and not during other time periods can reduce invalid testing processes and improve the efficiency of the power-off test.

[0086] In some embodiments, the operating parameter information includes page addresses involved in memory erase and write operations of the device under test.

[0087] The feedback unit actively feeds back the working parameter information of the device under test to the control unit, including: the feedback unit actively feeds back the page address involved in the memory erase and write operation of the device under test to the control unit.

[0088] The control unit tests the device under test based on the working parameter information, including: the control unit counts the number of erase and write times of each page in the memory based on the page address, and evaluates the wear leveling of the memory based on the number of erase and write times of each page.

[0089] Figure 4 The schematic diagram shows the feedback unit feeding back the page address involved in the memory erase and write operation of the device under test, wherein when the level is V2, it means that the memory erase and write operation is being performed, and when the level is 0, it means that the memory erase and write operation is not being performed. Figure 4 In the test, a total of three memory erase and write operations were performed. Each time a memory erase and write operation was performed, the feedback unit actively fed back the page address involved in the memory erase and write operation of the device under test to the control unit. After receiving the page address involved in the memory erase and write operation, the control unit determines the number of erase and write times of each page in the memory by counting the page addresses. After obtaining the number of erase and write times of each page in the memory, the control unit evaluates the wear leveling of the memory based on the number of erase and write times of each page.

[0090] In the disclosed embodiment, the total number of erase times of all pages in the memory and the total number of pages in the memory are counted based on the number of erase times of each page, and then the average number of erase times of each page is calculated. Based on the number of erase times of each page, the page with the most erase times and the page with the least erase times are determined, and the standard deviation of the number of erase times of each page is calculated based on the number of erase times of the page with the most erase times and the number of erase times of the page with the least erase times. The standard deviation of the number of erase times of each page can evaluate the discreteness of the number of erase times.

[0091] In the disclosed embodiment, after determining the average number of erase and write times and the standard deviation of the number of erase and write times per page, the wear leveling is evaluated based on the average number of erase and write times and the standard deviation of the number of erase and write times per page. Optionally, the ratio of the standard deviation of the number of erase and write times per page to the average number of erase and write times can be calculated, and the ratio is used as a uniformity index. The smaller the uniformity index, the more uniform the distribution of the number of erase and write times, and the better the wear leveling; the larger the uniformity index, the uneven distribution of the number of erase and write times, and the serious wear of some pages, which may shorten the life of the memory.

[0092] In some embodiments, the working parameter information includes debugging information of the device under test, wherein the debugging information may include error information, key variable values, program execution order, etc.

[0093] The feedback unit actively feeds back the working parameter information of the device under test to the control unit, including: the feedback unit actively feeds back the debugging information of the device under test to the control unit.

[0094] The control unit tests the device under test based on the working parameter information, including: the control unit performs error analysis or test control based on the debugging information.

[0095] Combination Figure 6 As shown, the embodiment of the present disclosure provides a computer 1, which includes a processor 11 and a memory 12. Optionally, the computer 1 may also include a communication interface 13 and a bus 14. The processor 11, the communication interface 13, and the memory 12 may communicate with each other through the bus 14. The communication interface 13 may be used for information transmission.

[0096] In addition, the logic instructions in the memory 12 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0097] The memory 12 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 11 executes functional applications and data processing by running the program instructions / modules stored in the memory 12, that is, implementing the NFC signal detection method in the above embodiment.

[0098] The memory 12 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 12 may include a high-speed random access memory and may also include a non-volatile memory.

[0099] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0100] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0101] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0102] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0103] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A device testing system, characterized in that: It includes a computer, a card reader, a device under test, a control unit and a feedback unit; The computer is connected to the card reader for communication, and the computer is configured to issue a test instruction; The card reader is in communication connection with the device under test, and the card reader is configured to perform signal interaction with the device under test according to the test instruction; The feedback unit is arranged in the device under test, the control unit is respectively connected to the card reader and the feedback unit for communication, the feedback unit is configured to actively feed back the working parameter information of the device under test to the control unit, and the control unit is configured to test the device under test based on the working parameter information.

2. The device testing system according to claim 1, characterized in that: The working parameter information includes the start and end time of the memory erase and write operation of the device under test; The feedback unit is configured to actively feed back the start and end time information of the memory erase and write operation of the device under test to the control unit; The control unit is configured to determine the execution time period of the memory erase and write operation based on the start and end time information, and control the card reader to perform a power-off test on the device under test during the execution time period.

3. The device testing system according to claim 1, characterized in that: The working parameter information includes page addresses involved in the memory erase and write operations of the device under test; The feedback unit is configured to actively feed back to the control unit a page address involved in a memory erase and write operation of the device under test; The control unit is configured to count the number of erase and write times of each page in the memory based on the page address, and evaluate the wear leveling status of the memory based on the number of erase and write times of each page.

4. The device testing system according to claim 1, characterized in that: The working parameter information includes the debugging information of the device under test; The feedback unit is configured to actively feed back debugging information of the device under test to the control unit; The control unit is configured to perform error analysis or test control based on the debugging information.

5. The device testing system according to any one of claims 1 to 4, characterized in that: The communication interface between the card reader and the device under test includes any of the following: ISO / IEC7816 interface, SPI, I2C interface; And / or, the communication interface between the control unit and the feedback unit includes any one of the following: GPIO interface, UART interface, SPI, I2C interface.

6. The device testing system according to any one of claims 1 to 4, characterized in that: The control unit is an independent unit arranged outside the card reader, or the control unit is arranged inside the card reader.

7. A device testing method, characterized in that: Applied to the device testing system according to any one of claims 1 to 6, the device testing method comprises: The computer issues test instructions; The card reader exchanges signals with the device under test according to the test instructions; The feedback unit actively feeds back the working parameter information of the device under test to the control unit; The control unit tests the device under test based on the operating parameter information.

8. The device testing method according to claim 7, characterized in that: The working parameter information includes the start and end time of the memory erase and write operation of the device under test; The feedback unit actively feeds back the working parameter information of the device under test to the control unit, including: the feedback unit actively feeds back the start and end time information of the memory erase and write operation of the device under test to the control unit; The control unit tests the device under test based on the working parameter information, including: the control unit determines the execution time period of the memory erase and write operation based on the start and end time information, and controls the card reader to perform a power-off test on the device under test during the execution time period.

9. The device testing method according to claim 7, characterized in that: The working parameter information includes page addresses involved in the memory erase and write operations of the device under test; The feedback unit actively feeds back the working parameter information of the device under test to the control unit, including: the feedback unit actively feeds back the page address involved in the memory erase and write operation of the device under test to the control unit; The control unit tests the device under test based on the working parameter information, including: the control unit counts the number of erase and write times of each page in the memory based on the page address, and evaluates the wear leveling of the memory based on the number of erase and write times of each page.

10. The device testing method according to claim 7, characterized in that: The working parameter information includes the debugging information of the device under test; The feedback unit actively feeds back the working parameter information of the device under test to the control unit, including: the feedback unit actively feeds back the debugging information of the device under test to the control unit; The control unit tests the device under test based on the working parameter information, including: the control unit performs error analysis or test control based on the debugging information.

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