Defect Detection Method and Device for Electric Control Components of New Energy Vehicles

Abstract

The present invention discloses a method and device for detecting defects in an electronic control component of a new energy vehicle. Among them, the method for detecting defects in the electronic control component of the new energy vehicle includes applying an alternating current signal in the range of 100 kHz - 10 MHz to the electronic control component, and obtaining the impedance response characteristics of each parasitic coupling region of the power device by using a differential detection method; performing multi-port network analysis on the impedance response characteristics to extract the distributed capacitance values of each parasitic coupling region; performing time-frequency feature analysis on the distributed capacitance values to obtain the parasitic characteristics during the switching process; calculating the capacitance deviation amount according to the parasitic characteristics to determine the defect region and its type; verifying the stability of the defect region and its type under temperature cycle and vibration stress conditions to obtain a reliability evaluation result. The technical solution of the present invention can accurately identify and evaluate the reliability of the micro-defects caused by abnormal parasitic capacitance inside the electronic control component of the new energy vehicle.

Description

Technical Field

[0001] The present invention relates to the technical field of defect detection for new energy vehicle electronic control components, and particularly to a method and device for defect detection of new energy vehicle electronic control components. Background Art

[0002] The electronic control components of new energy vehicles are key components in the vehicle power system, mainly including power semiconductor devices and their drive circuits. Among them, the power devices are responsible for the energy conversion of the high-voltage DC bus, and control the switching state through the gate drive signal to achieve the speed regulation and voltage regulation of the motor. To improve the system power density and reduce the switching loss, the operating frequency of modern electronic control components is constantly increasing. Especially after using new semiconductor materials such as silicon carbide, the switching frequency has reached the range of 100 kHz - 10 MHz.

[0003] With the increase of the operating frequency, the problems caused by parasitic parameters in the electronic control components become increasingly prominent. Especially the parasitic capacitances inside the power devices, including the gate-source capacitance, drain-source capacitance, and Miller capacitance, etc., will cause abnormal phenomena such as parasitic oscillation and increased switching loss under high-frequency operating conditions. These abnormalities often originate from the tiny defects inside the devices, such as gate oxide layer defects, PN junction breakdown, etc. Traditional static parameter testing methods are difficult to detect such defects, and conventional dynamic testing cannot accurately locate the fault position. Therefore, there is an urgent need for a method that can accurately detect and evaluate the abnormal parasitic capacitances inside the electronic control components under high-frequency operating conditions to ensure the reliable operation of new energy vehicles. Summary of the Invention

[0004] The main purpose of the present invention is to solve the technical problem of how to accurately identify the tiny defects caused by abnormal parasitic capacitances inside the devices and evaluate their reliability when the electronic control components of new energy vehicles operate at high frequencies.

[0005] The first aspect of the present invention provides a method for defect detection of new energy vehicle electronic control components, and the method for defect detection of new energy vehicle electronic control components includes:

[0006] Applying an alternating current signal in the range of 100 kHz - 10 MHz to the electronic control component, and obtaining the impedance response characteristics of each parasitic coupling region of the power device by using a differential detection method;

[0007] Performing multi-port network analysis on the impedance response characteristics to extract the distributed capacitance values of each parasitic coupling region;

[0008] Performing time-frequency characteristic analysis on the distributed capacitance values to obtain the parasitic characteristics during the switching process;

[0009] Calculating the capacitance deviation amount according to the parasitic characteristics to determine the defect region and its type;

[0010] Verify the stability of the defect area and its type under temperature cycle and vibration stress conditions to obtain the reliability evaluation result.

[0011] Optionally, apply an alternating current signal in the range of 100 kHz - 10 MHz to the electronic control component, and use the differential detection method to obtain the impedance response characteristics of each parasitic coupling area of the power device, including:

[0012] Set high-frequency response probes on the first parasitic coupling surface between the gate and source electrodes and the second parasitic coupling surface between the drain and source electrodes of the power device as the reference detection terminals;

[0013] Set differential probes on the gate-drain coupling surface in the Miller plateau region and the coupling surface between the power supply and ground of the power loop as the differential detection terminals;

[0014] Apply an alternating current scanning signal with an initial frequency of 100 kHz to the reference detection terminals, and gradually increase the excitation frequency to 10 MHz in steps of 50 kHz according to the switching frequency characteristics of the power device;

[0015] Collect the high-frequency response data of the reference detection terminals and the differential detection terminals, and calculate the impedance response characteristics of each parasitic coupling area.

[0016] Optionally, applying an alternating current scanning signal with an initial frequency of 100 kHz to the reference detection terminals, and gradually increasing the excitation frequency to 10 MHz in steps of 50 kHz according to the switching frequency characteristics of the power device, includes:

[0017] Take the gate drive voltage when the power device is turned on as the reference, and set the initial amplitude of the alternating current scanning signal to 30% of it;

[0018] Apply a scanning signal with an initial frequency of 100 kHz to the reference detection terminals, and record the gate turn-on threshold point of the power device;

[0019] Dynamically calculate the signal application time of the next frequency point according to the response time of the gate turn-on threshold point;

[0020] Compensate the signal application time in steps of 50 kHz to eliminate the phase delay caused by the parasitic loop;

[0021] Gradually increase the signal frequency to 10 MHz at the compensated time, and maintain the trigger synchronization of each frequency point.

[0022] Optionally, collecting the high-frequency response data of the reference detection terminals and the differential detection terminals, and calculating the impedance response characteristics of each parasitic coupling area, includes:

[0023] Perform amplitude normalization processing on the high-frequency response data of the reference detection terminals to obtain the reference response sequence;

[0024] Calibrate the high-frequency response data of the differential detection end according to the reference response sequence to obtain a differential response sequence;

[0025] Calculate the phase difference between the reference response sequence and the differential response sequence to obtain a coupling phase characteristic;

[0026] Compensate the high-frequency response data according to the coupling phase characteristic to obtain an actual impedance value;

[0027] Map the actual impedance value according to the physical position of the parasitic coupling region to obtain an impedance response characteristic.

[0028] Optionally, perform multi-port network analysis on the impedance response characteristic to extract the distributed capacitance values of each parasitic coupling region, including:

[0029] Perform fast Fourier transform on the impedance response characteristic in the gate drive loop and the power main loop respectively to obtain a double-loop amplitude-frequency characteristic;

[0030] Establish an interconnected network equation for the double-loop amplitude-frequency characteristic according to three groups of coupling relationships of gate-source, drain-source, and gate-drain to obtain the transfer function of each coupling region;

[0031] Perform odd-even mode separation on the transfer function to obtain common-mode and differential-mode impedance components;

[0032] Perform data reconstruction on the common-mode and differential-mode impedance components within a fixed time window of the Miller plateau to obtain the equivalent parameters of each coupling region;

[0033] Correct and compensate the equivalent parameters according to the actual switching frequency points to obtain the distributed capacitance values of each parasitic coupling region.

[0034] Optionally, perform time-frequency characteristic analysis on the distributed capacitance values to obtain parasitic characteristics during the switching process, including:

[0035] Segment the distributed capacitance values according to the conduction stage, Miller plateau stage, and turn-off stage of the power device to obtain three-segment characteristic sequences;

[0036] Calculate the voltage change rate of the characteristic sequences in the conduction stage and the turn-off stage to obtain switching stress characteristics;

[0037] Perform parasitic oscillation analysis on the characteristic sequence in the Miller plateau stage to obtain plateau oscillation characteristics;

[0038] Synchronously mark the switching stress characteristics and the plateau oscillation characteristics based on the voltage flip points of the switching period to obtain the timing characteristics of the parasitic parameters;

[0039] Reconstruct the timing characteristics under different switching rate conditions to obtain the parasitic characteristics during the switching process.

[0040] Optionally, performing parasitic oscillation analysis on the characteristic sequence of the Miller plateau stage to obtain the oscillation characteristics during the plateau period, including:

[0041] Identifying the boundaries of the gate voltage plateau period for the characteristic sequence to obtain the start and end times of the Miller plateau;

[0042] Extracting the peak and valley values of the oscillation waveform of the drain voltage within the start and end times to obtain the oscillation amplitude sequence;

[0043] Calculating the attenuation coefficient of the oscillation amplitude sequence to obtain the damping characteristics of each oscillation;

[0044] Correlating the damping characteristics with the drain current change rate to obtain the triggering characteristics of parasitic oscillation;

[0045] Establishing an oscillation energy distribution map based on the triggering characteristics and attenuation law to obtain the oscillation characteristics during the plateau period.

[0046] Optionally, calculating the capacitance deviation based on the parasitic characteristics to determine the defective area and its type, including:

[0047] Comparing the parasitic parameters in the gate-source region of the parasitic characteristics with the reference value to obtain the first deviation;

[0048] Comparing the parasitic parameters in the drain-source region of the parasitic characteristics with the reference value to obtain the second deviation;

[0049] Locating the points where the first deviation and the second deviation exceed the threshold according to the chip layout coordinate system to obtain the physical coordinates of the abnormal area;

[0050] Matching the physical coordinates of the abnormal area with the PN junction distribution map of the power device to obtain the defect type;

[0051] Calculating the difference between the parasitic parameters in the area corresponding to the defect type and the standard threshold to obtain the capacitance deviation.

[0052] Optionally, verifying the stability of the defective area and its type under temperature cycle and vibration stress conditions to obtain the reliability evaluation result, including:

[0053] During the temperature cycle, scanning the impedance characteristics of the defective area at four temperature points of -40°C, 25°C, 85°C, and 125°C to obtain the temperature stress response curve;

[0054] During the vibration process, the parameters are measured at five frequency points of 10Hz, 100Hz, 500Hz, 1000Hz and 2000Hz as required by automotive electronic standards to obtain the vibration stress response curve;

[0055] Extract parameters of the temperature stress response curve at the fundamental wave, second harmonic and third harmonic of the switching frequency of the power device to obtain the temperature stress influencing factor;

[0056] The vibration stress response curve is re-measured at the defect position in three states: on, Miller platform and off, to obtain the vibration stress influencing factor;

[0057] According to the acceleration effect of the temperature stress influencing factor and the vibration stress influencing factor on the defect parameters, a reliability evaluation result is obtained.

[0058] A second aspect of the present invention provides a defect detection device for electric control components of new energy vehicles, comprising:

[0059] The signal injection module is used to apply an AC signal in the range of 100kHz-10MHz to the electronic control component, and obtain the impedance response characteristics of each parasitic coupling area of ​​the power device by differential detection;

[0060] A network analysis module, used to perform multi-port network analysis on the impedance response characteristics and extract the distributed capacitance value of each parasitic coupling area;

[0061] A time-frequency processing module, used to perform time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process;

[0062] A defect recognition module, used to calculate the capacitance deviation according to the parasitic characteristics, and determine the defect area and its type;

[0063] The reliability evaluation module is used to verify the stability of the defect area and its type under temperature cycle and vibration stress conditions to obtain a reliability evaluation result.

[0064] The defect detection method for the electronic control components of new energy vehicles provided by the present invention realizes the high-precision acquisition of the impedance characteristics of each parasitic coupling region of power devices by adopting the differential detection method. In particular, detection terminals are set at key coupling surfaces such as the gate-source and drain-source, and combined with a broadband scanning signal of 100 kHz - 10 MHz, the frequency-domain characteristics of parasitic parameters can be comprehensively captured. Further, through the multi-port network analysis technology, the complex impedance characteristics are successfully decomposed into distributed capacitance values, laying a data foundation for subsequent defect identification. In the time-frequency feature analysis link, the switching process of the power device is divided into three stages: conduction, Miller plateau, and turn-off, and the parasitic characteristics are extracted respectively, making the defect detection more targeted. At the same time, the present invention establishes a defect location method based on the capacitance deviation, and combined with temperature cycle and vibration stress verification, it can not only accurately identify the defect location and type, but also evaluate its stability in the actual working environment. This multi-dimensional detection and evaluation scheme effectively solves the problem of accurate detection of abnormal parasitic capacitance in the high-frequency working state, and provides technical support for the reliability guarantee of the electronic control components of new energy vehicles. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0066] Figure 1 It is a schematic diagram of an embodiment of the defect detection method for the electronic control components of new energy vehicles in an embodiment of the present invention;

[0067] Figure 2 It is a schematic diagram of an embodiment of the defect detection device for the electronic control components of new energy vehicles in an embodiment of the present invention.

[0068] The realization, functional characteristics and advantages of the purpose of the present invention will be further described in combination with the embodiments with reference to the drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0069] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0070] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present invention, the directional indications are only used to explain the relative positional relationship, movement conditions, etc. between components in a certain specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0071] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, "and / or" throughout the text includes three scenarios. Taking A and / or B as an example, it includes the technical solution of A, the technical solution of B, and the technical solution that A and B are satisfied simultaneously. In addition, the technical solutions between various embodiments can be combined with each other, which must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions conflicts with each other or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0072] An embodiment of the present application provides a method for detecting defects in new energy vehicle electronic control components. Figure 1 FIG. is a flowchart of a method for detecting defects in new energy vehicle electronic control components provided by an embodiment of the present application. In this embodiment, the method includes:

[0073] Please refer to Figure 1 , apply an alternating current signal in the range of 100 kHz - 10 MHz to the electronic control component, and use a differential detection method to obtain the impedance response characteristics of each parasitic coupling region of the power device;

[0074] In an embodiment of the present invention, the step of applying an alternating current signal in the range of 100 kHz - 10 MHz to the electronic control component and using a differential detection method to obtain the impedance response characteristics of each parasitic coupling region of the power device includes: setting high-frequency response probes on the first parasitic coupling surface between the gate and source electrodes and the second parasitic coupling surface between the drain and source electrodes of the power device as the reference detection terminals; setting differential probes on the gate-drain coupling surface in the Miller plateau region and the coupling surface between the power supply and ground of the power loop as the differential detection terminals; applying an alternating current scanning signal with an initial frequency of 100 kHz to the reference detection terminals, and gradually increasing the excitation frequency to 10 MHz in steps of 50 kHz according to the switching frequency characteristics of the power device; collecting the high-frequency response data of the reference detection terminals and the differential detection terminals, and calculating the impedance response characteristics of each parasitic coupling region.

[0075] Specifically, during the defect detection process of new energy vehicle electronic control components, it is first necessary to understand the structural characteristics of the detection object. The core device of the electronic control component is the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET for short), which is a power switching device used for power conversion and is responsible for converting the DC bus voltage (usually 400 volts to 800 volts) into the AC voltage required to drive the motor. The MOSFET mainly consists of three electrodes: the gate, the source, and the drain. By applying a voltage to the gate, the conduction or cutoff between the source and the drain is controlled, thereby realizing the switching function. In the application of new energy vehicles, to improve the energy conversion efficiency, silicon carbide MOSFETs are increasingly used. The switching frequency of this device can reach hundreds of kilohertz, but at the same time, it also brings the problem of aggravated parasitic parameter effects.

[0076] When conducting defect detection, it is first necessary to set detection probes at key positions of the MOSFET. Specifically, high-frequency response probes are set as the reference detection terminals at the first parasitic coupling surface between the gate and the source (i.e., the overlapping area of the gate metal layer and the source metal layer of the power device chip. This area will form a small capacitor, with a typical value of a few nanofarads, which directly affects the switching speed of the device) and the second parasitic coupling surface between the drain and the source (i.e., the overlapping area of the drain metal layer and the source metal layer of the chip. The parasitic capacitance of this area is usually between a few hundred picofarads and a few nanofarads, which affects the turn-off characteristics of the device). Taking a silicon carbide MOSFET with a rated voltage of 1200V as an example, the high-frequency response probe set between its gate and source adopts a metal microstrip line structure (width 0.2 mm, thickness 35 μm), and the probe is 0.5 mm away from the chip surface. The microstrip line structure is selected because it has good high-frequency transmission characteristics and its characteristic impedance can be accurately controlled (usually designed to be 50 ohms, which matches the test system). The bandwidth of the probe needs to reach more than 50 MHz (-3 dB bandwidth point) to ensure that the high-frequency response characteristics can be accurately captured.

[0077] Meanwhile, differential probes are set as differential detection terminals at the gate-drain coupling surface in the Miller plateau region and at the coupling surface between the power supply and ground of the power loop. Here, the Miller plateau region refers to a special time period during the MOSFET switching process: when the device switches from the off state to the on state, due to the rapid drop of the drain voltage (typical value is 50 volts per microsecond), through the coupling effect of the Miller capacitance (the parasitic capacitance between the gate and the drain), the gate voltage will remain constant at a certain voltage value (usually 2 - 3 times the device threshold voltage), and this plateau period usually lasts for 1 - 2 microseconds. The power loop refers to the current path formed from the positive power supply through the MOSFET to the negative power supply. The parasitic inductance of the wiring in this loop (typical value is 10 - 20 nanohenries) will resonate with the parasitic capacitance of the device, generating high-frequency oscillations.

[0078] The differential probes are arranged symmetrically, that is, one probe is placed on each side of the Miller region, and the distance between the two probes is kept within 10 millimeters to reduce the loss during the transmission of differential signals. For example, in the power loop, one differential probe is placed 5 millimeters away from the power supply end, and the other is placed 5 millimeters away from the ground end. The probe adopts a coaxial structure (inner conductor diameter 0.5 millimeters, outer shield diameter 2 millimeters), and the outer shield is grounded. Through the shielding effect, the external electromagnetic field interference is reduced by more than 40 decibels.

[0079] After the probe arrangement is completed, an AC sweep signal is applied to the reference detection terminal. The reason for choosing an initial frequency of 100 kHz is that: at this time, the impedance generated by the parasitic capacitance of the MOSFET (counted as 10 nanofarads) is about 160 ohms. This resistance value can not only ensure that the signal has sufficient strength to be transmitted but also prevent the signal from short-circuiting due to too low impedance. The sweep signal uses a sine wave, and the amplitude is set to 1 volt (this value is much lower than the gate threshold voltage of the device, which is 3 - 5 volts, so it will not trigger the device switching action), and it is transmitted through a coaxial cable with a characteristic impedance of 50 ohms. The frequency is increased step by step according to a step size of 50 kHz. The basis for choosing this step value is that the impedance change between adjacent frequency points does not exceed 5%, which not only ensures the measurement accuracy but also makes the entire sweep process controlled within 1 minute.

[0080] Data acquisition is performed using a high-speed data acquisition system. Its core indicators include: a sampling rate of 100 MHz, a resolution of 12 bits (able to distinguish a signal change of 0.025%), and a dynamic range of 70 dB. The sampling rate is set to be more than 10 times the signal frequency to accurately reconstruct the waveform and avoid spectral aliasing. For example, at an excitation frequency of 10 MHz, the sampling rate is 100 MHz, that is, 10 points are collected per signal cycle. Through these discrete points, an interpolation algorithm can be used to reconstruct the complete response waveform. The collected data is processed by a band-pass filter (the passband range is ±10% of the excitation frequency), and after filtering out power frequency interference and high-frequency noise, it is used to calculate the impedance response characteristics of each parasitic coupling region. Finally, common-mode noise is eliminated through differential processing (i.e., subtracting the data of the reference detection end from the data of the differential detection end) to obtain accurate impedance characteristics. This method can increase the signal-to-noise ratio by more than 20 dB, which is equivalent to increasing the measurement accuracy by 10 times.

[0081] In an embodiment of the present invention, an AC scanning signal with an initial frequency of 100 kHz is applied to the reference detection end, and according to the switching frequency characteristics of the power device, the excitation frequency is gradually increased to 10 MHz in steps of 50 kHz, including: using the gate drive voltage when the power device is turned on as a reference, setting the initial amplitude of the AC scanning signal to 30% of it; applying a scanning signal with an initial frequency of 100 kHz to the reference detection end and recording the gate turn-on threshold point of the power device; dynamically calculating the signal application time of the next frequency point according to the response time of the gate turn-on threshold point; compensating the signal application time in steps of 50 kHz to eliminate the phase delay caused by the parasitic loop; gradually increasing the signal frequency to 10 MHz at the compensated time while maintaining the trigger synchronization of each frequency point.

[0082] Specifically, in order to achieve precise detection of MOSFET devices, it is first necessary to determine an appropriate amplitude of the excitation signal. In the normal operation of a MOSFET, the gate drive voltage (usually 12 volts or 15 volts) is a key parameter to ensure reliable device conduction. This drive voltage needs to be sufficiently greater than the gate threshold voltage (for silicon carbide MOSFETs, the typical value is 2.5 - 3.5 volts) to reduce conduction losses. When performing defect detection, 30% of the gate drive voltage when turned on is selected as the initial amplitude of the AC scanning signal. For example, if the drive voltage is 15 volts, the scanning signal amplitude is set to 4.5 volts. The reason for choosing this ratio is that this amplitude is large enough to ensure the signal-to-noise ratio of signal detection (usually greater than 40 dB) and will not cause the device to turn on accidentally (because after the scanning signal is superimposed on the gate-source bias voltage, the total voltage is still lower than the turn-on threshold).

[0083] After applying a scanning signal with an initial frequency of 100 kHz to the reference detection terminal, it is necessary to record the gate turn-on threshold point of the power device. This threshold point refers to the moment when the gate voltage reaches the minimum voltage value required for the device to turn on. For a silicon carbide MOSFET, this value is typically around 3 volts. The recording method is to use a high-speed voltage probe (bandwidth not less than 500 MHz) at the gate terminal, and the input capacitance of the probe needs to be less than 2 picofarads to avoid affecting the measurement accuracy. At the same time, a reference voltage probe is set at the source terminal, and the accurate gate-source voltage is obtained through differential measurement. In actual operation, it can be observed that during the period when the gate-source voltage rises from 0 to the threshold voltage, the inflection point where the drain current starts to rise rapidly, and the moment corresponding to this inflection point is the turn-on threshold point.

[0084] After obtaining the threshold point, dynamically calculate the signal application time for the next frequency point according to its response time. The response time is defined as the time interval from applying the scanning signal to reaching the threshold point, and this time reflects the influence of the parasitic parameters of the device on signal transmission. For example, if the measured response time at 100 kHz is 200 nanoseconds, then when calculating the signal application time for 150 kHz (the frequency point after increasing the step by 50 kHz), this delay needs to be considered. The specific calculation method is: divide the response time by the current frequency period to obtain the phase delay angle, and this angle will be used for subsequent compensation.

[0085] During the process of adjusting the frequency in steps of 50 kHz, it is necessary to compensate for the signal application time. This is because there is a resonant circuit formed by parasitic inductance (mainly from leads and packages, with a typical value of a few nanohenries) and parasitic capacitance in the power device, and this circuit will cause phase delay during signal transmission. The compensation method is: advance the signal application time according to the phase delay measured at the previous frequency point. Taking the 150 kHz frequency point as an example, if the measured phase delay at 100 kHz is 30 degrees, then when applying the 150 kHz signal, it is necessary to advance the trigger time by a time equivalent to 30 degrees of phase (i.e., 555.6 nanoseconds).

[0086] Finally, during the process of gradually increasing the frequency to 10 MHz, it is necessary to maintain the trigger synchronization at each frequency point. This means that at each frequency point, the signal application time should maintain a fixed phase relationship with the switching cycle of the device. The implementation method is to use a phase-locked loop circuit to lock the phase of the scanning signal to the phase of the device gate drive signal. The bandwidth of the phase-locked loop is set to 1 / 10 of the scanning frequency, so that while ensuring phase tracking, it can avoid interfering with the measurement signal. Through this synchronization mechanism, it is ensured that the data obtained during the entire scanning process has time correlation, providing a reliable basis for subsequent parameter extraction.

[0087] In one embodiment of the present invention, collecting high-frequency response data of the reference detection end and the differential detection end and calculating impedance response characteristics of each parasitic coupling region includes: performing amplitude normalization processing on the high-frequency response data of the reference detection end to obtain a reference response sequence; calibrating the high-frequency response data of the differential detection end according to the reference response sequence to obtain a differential response sequence; calculating the phase difference between the reference response sequence and the differential response sequence to obtain a coupling phase characteristic; compensating the high-frequency response data according to the coupling phase characteristic to obtain an actual impedance value; mapping the actual impedance value according to the physical position of the parasitic coupling region to obtain impedance response characteristics.

[0088] Specifically, in the process of obtaining the parasitic characteristics of a power device, the collected raw data needs to be processed. First, amplitude normalization processing is performed on the high-frequency response data of the reference detection end. The data collected by the reference detection end includes voltage and current information obtained from two coupling surfaces between the gate-source and drain-source. The amplitude range of these data may vary from a few millivolts to several volts. The specific method of normalization processing is: dividing the response amplitude of each frequency point by the amplitude of the excitation signal at that frequency. For example, when the amplitude of the excitation signal is 4.5 volts, if the measured response amplitude at a certain frequency point is 2.25 volts, the normalized value is 0.5. This processing eliminates the influence of the amplitude fluctuation of the excitation signal at different frequency points, making the data comparable.

[0089] When calibrating the data of the differential detection end, the reference response sequence needs to be used as a reference. The differential detection end is located at the gate-drain coupling surface in the Miller plateau region and the coupling surface between the power supply and the ground in the power loop. The parasitic effects at these positions are more complex. The calibration process first needs to consider the frequency response characteristics of the probe itself: in the frequency range of 100 kHz to 10 MHz, the gain and phase response of the probe are not completely flat, and the calibration coefficient of the probe needs to be used for correction. For example, if at the 5 MHz frequency point, the gain attenuation of the probe is -0.5 dB and the phase shift is -2 degrees, the measurement data needs to be compensated accordingly. The calibrated differential response sequence reflects the true parasitic characteristics of each coupling region.

[0090] The calculation of the phase difference between the reference response sequence and the differential response sequence is the key to identifying the parasitic coupling effect. During the switching process of the MOSFET, due to the charge and discharge effect of the parasitic capacitance, there will be a phase difference in the responses of different coupling regions. The calculation method is as follows: First, obtain the analytic signals of the two sequences through the Hilbert transform, and then calculate the difference in their instantaneous phases. For example, during the Miller plateau, if the phase of the reference sequence is 30 degrees and the phase of the differential sequence is 45 degrees, the phase difference is 15 degrees, which reflects the signal delay effect caused by the Miller capacitance. By analyzing the change trend of the phase difference at different frequency points, the coupling phase characteristics can be obtained, which quantify the dynamic influence of the parasitic parameters.

[0091] After obtaining the coupling phase characteristics, it is necessary to compensate the high-frequency response data to obtain the actual impedance value. The compensation process takes into account three aspects: First is the inductive reactance component caused by the parasitic inductance (for example, for a parasitic inductance of 5 nH, the inductive reactance at a frequency of 5 MHz is 157 ohms), second is the capacitive reactance component caused by the parasitic capacitance (for a parasitic capacitance of 10 nF, the capacitive reactance at a frequency of 5 MHz is 3.18 ohms), and finally is the on-resistance component (usually in the range of dozens to hundreds of milliohms). Through complex number operations, these components are combined to obtain the actual impedance value at each test point.

[0092] The last step is to map the actual impedance value to the physical structure of the device. The chip structure of the MOSFET usually contains multiple units, and each unit has a source region, a drain region, and a gate region. The mapping process needs to establish the correspondence between the test points and the physical positions on the chip. For example, for a chip with an area of 10 square millimeters, a 10×10 grid coordinate system can be established, and the measured impedance values are corresponding to the specific physical positions. Through this mapping, the spatial distribution characteristics of the parasitic parameters can be visually displayed. For example, in the region where the gate metal layer overlaps more with the source metal layer, the parasitic capacitance value will be significantly larger. This distribution characteristic provides an important basis for subsequent defect detection because abnormal impedance distribution often indicates potential quality problems.

[0093] Please continue to refer to Figure 1 for the multi-port network analysis of the impedance response characteristics to extract the distributed capacitance values of each parasitic coupling region;

[0094] In an embodiment of the present invention, the multi-port network analysis of the impedance response characteristics to extract the distributed capacitance values of each parasitic coupling region includes: performing fast Fourier transform on the impedance response characteristics in the gate drive loop and the power main loop respectively to obtain the double-loop amplitude-frequency characteristics; establishing an interconnected network equation based on the double-loop amplitude-frequency characteristics according to three groups of coupling relationships of gate-source, drain-source, and gate-drain to obtain the transfer function of each coupling region; performing odd-even mode separation on the transfer function to obtain the common-mode and differential-mode impedance components; performing data reconstruction on the common-mode and differential-mode impedance components within a fixed time window of the Miller plateau to obtain the equivalent parameters of each coupling region; and performing calibration compensation on the equivalent parameters according to the actual switching frequency points to obtain the distributed capacitance values of each parasitic coupling region.

[0095] Specifically, in the electronic control components of new energy vehicles, the parasitic parameters of MOSFETs are distributed in the gate drive loop and the power main loop. First, it is necessary to perform fast Fourier transform processing on the obtained impedance response characteristics, which converts the time-domain signal to the frequency domain. Among them, the gate drive loop mainly includes the connection path from the gate drive chip to the MOSFET gate, and the measured voltage range is usually 0-20 volts; the power main loop includes the large-current path from the positive power supply through the MOSFET to the negative power supply, and the measured voltage can reach several hundred volts. When performing the transformation, 2048-point FFT (fast Fourier transform) is used, so that a frequency resolution of 0.5 kHz can be obtained. For example, when the switching transient voltage of the gate drive loop is 12 volts and the rise time is 100 nanoseconds, the main frequency components can be obtained around 3.5 MHz through FFT.

[0096] When using the obtained double-loop amplitude-frequency characteristics to establish the interconnected network equation, three main groups of coupling relationships need to be considered. The coupling between the gate and the source is mainly determined by the gate oxide capacitance (typical value is 2-3 nF); the coupling between the drain and the source is affected by the junction capacitance (space-charge layer capacitance, which changes with the drain-source voltage, and the typical value ranges from a few hundred picofarads to a few nanofarads); and the coupling between the gate and the drain (i.e., the Miller capacitance) directly affects the switching characteristics. For example, in a certain model of 1200V silicon carbide MOSFET, when the drain-source voltage is 600V, the junction capacitance is about 200 pF and the Miller capacitance is about 50 pF. The interconnected network equation established based on these parameters adopts the Y-parameter form, which can intuitively represent the admittance relationship between each port.

[0097] The purpose of separating the odd and even modes of the transfer function is to distinguish common-mode interference from differential-mode signals. During the MOSFET switching process, the common-mode signals mainly come from power supply ripple and ground noise, and are manifested as interference that is superimposed in-phase at each measurement point; while the differential-mode signals reflect the true switching characteristics. The separation method is as follows: perform eigenvalue decomposition on the measured transfer function matrix. The larger eigenvalue corresponds to the differential-mode component (usually 10 - 20 dB larger than the common-mode component), and the smaller eigenvalue corresponds to the common-mode component. Taking actual measurement as an example, if the transfer impedance measured at a frequency point of 5 MHz is 100 ohms, after separation, a differential-mode impedance of 80 ohms and a common-mode impedance of 20 ohms may be obtained.

[0098] When performing data reconstruction during the Miller plateau, the selected time window is usually 1 - 2 microseconds. This is because during the Miller plateau, the drain voltage of the MOSFET changes rapidly (typical change rate is 50 V / μs), while the gate voltage remains relatively stable, and the parasitic parameter characteristics are the most obvious at this time. The data reconstruction uses the moving average method, and the window length is selected as 1 / 10 of the switching period, which can effectively suppress high-frequency noise without losing valid information. For example, for a switching frequency of 100 kHz, a 1-microsecond time window is selected, and parameter calculations are performed every 0.1 microseconds.

[0099] Finally, when correcting and compensating the equivalent parameters, the characteristics of the actual switching frequency point need to be considered. For MOSFETs, their junction capacitance and Miller capacitance change at different switching frequencies, and this change is related to voltage stress and temperature. The compensation method is to establish a look-up table containing correction factors under different operating conditions. For example, when the device junction temperature rises from 25 degrees Celsius to 100 degrees Celsius, the parasitic capacitance may increase by 15 - 20%, and the parameter values need to be adjusted accordingly. Through this compensation, the finally obtained distributed capacitance value can accurately reflect the parasitic characteristics of the device under actual operating conditions, providing a reliable basis for defect detection.

[0100] Please continue to refer to Figure 1 and perform time-frequency characteristic analysis on the distributed capacitance value to obtain the parasitic characteristics during the switching process;

[0101] In an embodiment of the present invention, the time-frequency characteristic analysis of the distributed capacitance value to obtain the parasitic characteristics during the switching process includes: segmenting the distributed capacitance value into three time-sequence segments according to the conduction stage, Miller plateau stage, and turn-off stage of the power device to obtain three characteristic sequences; calculating the voltage change rate of the characteristic sequences in the conduction stage and turn-off stage to obtain the switching stress characteristics; performing parasitic oscillation analysis on the characteristic sequence in the Miller plateau stage to obtain the oscillation characteristics during the plateau period; synchronously marking the switching stress characteristics and the oscillation characteristics during the plateau period based on the voltage turning point of the switching period to obtain the time-sequence characteristics of the parasitic parameters; and reconstructing the time-sequence characteristics under different switching rate conditions to obtain the parasitic characteristics during the switching process.

[0102] Specifically, in order to accurately analyze the dynamic characteristics of the power device, it is necessary to perform time-sequence analysis on the obtained distributed capacitance value. The switching process of a MOSFET can be divided into three key stages: the conduction stage (the device changes from cutoff to fully conducting, lasting about 200 - 300 nanoseconds), the Miller plateau stage (this stage is also called the stable plateau period, which refers to the feedback effect caused by the rapid change of the drain voltage during the switching process, resulting in the gate voltage staying at a fixed level value. This fixed level is usually 2 - 3 times the gate threshold voltage and lasts about 1 - 2 microseconds), and the turn-off stage (the device changes from conducting to fully cutoff, lasting about 300 - 400 nanoseconds). When segmenting the distributed capacitance value according to these three stages, the change characteristics of the gate voltage are used as the segmentation basis. For example, when the gate voltage rises from 0 to the threshold voltage (about 3 volts), it is the starting point of the conduction stage; when the voltage reaches the stable plateau level (about 6 - 7 volts), it enters the Miller plateau stage; and when the voltage starts to drop, it enters the turn-off stage.

[0103] During the conduction and turn-off stages, the device bears the maximum voltage stress. The calculation method of the voltage change rate in the conduction stage is: measure the time required for the drain voltage to drop from a high level (e.g., 400 volts) to a low level (about 1 - 2 volts). The typical value is 50 volts per microsecond. In the turn-off stage, it is the opposite, measuring the change rate of the voltage rising from a low level to a high level. The voltage change rates in these two stages directly reflect the switching stress characteristics. For example, if the measured voltage change rate during the conduction process exceeds 100 volts per microsecond, it indicates that the device may have excessive switching stress, which is often related to excessive parasitic inductance (from device leads and PCB wiring, typical value is 10 - 20 nanohenries).

[0104] Parasitic oscillation analysis during the Miller platform stage is particularly important because the device is in its most sensitive operating state at this time. Oscillation analysis first involves identifying the characteristics of the oscillation waveform: the oscillation frequency (usually in the range of 5 - 20 MHz, determined by the resonance of parasitic inductance and junction capacitance), the amplitude (which should normally be less than 5% of the DC bus voltage), and the decay time constant (reflecting the damping characteristics of the circuit, with typical values of 200 - 300 nanoseconds). For example, at a 400 - volt DC bus voltage, if an oscillation amplitude exceeding 40 volts is observed and the decay time constant exceeds 500 nanoseconds, it indicates the presence of abnormal parasitic resonance.

[0105] The voltage transition point of the switching cycle is an important reference for feature synchronization. The voltage transition point refers to the moment when the drain voltage starts to change rapidly, which is usually synchronized with the gate voltage reaching the threshold voltage. During the synchronization marking process, the stress characteristics and oscillation characteristics within each switching cycle are aligned according to the time offset relative to the transition point. For example, if the oscillation during a certain switching process occurs 200 nanoseconds after the transition point, this time relationship needs to be consistent in all sampling cycles to correctly evaluate the dynamic characteristics of the parasitic parameters.

[0106] Finally, it is necessary to reconstruct the timing characteristics under different switching speed conditions. The switching speed is determined by the gate drive circuit and can usually be adjusted by changing the gate resistance (typical range from 2 ohms to 20 ohms). For each switching speed, the above - mentioned analysis process needs to be repeated. For example, when using a 5 - ohm gate resistance, the measured rise time may be 100 nanoseconds and the oscillation frequency is 15 MHz; while when using a 15 - ohm resistance, the rise time may extend to 300 nanoseconds and the oscillation frequency drops to 10 MHz. By comparing the characteristic changes under different conditions, the parasitic characteristics of the device can be comprehensively evaluated, especially the influence law of parasitic parameters on the switching performance. This comprehensive characteristic analysis provides reliable data support for subsequent defect diagnosis.

[0107] In an embodiment of the present invention, the parasitic oscillation analysis of the characteristic sequence during the Miller platform stage to obtain the oscillation characteristics during the platform period includes: identifying the boundaries of the gate - voltage platform period for the characteristic sequence to obtain the start and end times of the Miller platform; extracting the peak - to - valley values of the oscillation waveform of the drain voltage within the start and end times to obtain the oscillation amplitude sequence; calculating the decay coefficient of the oscillation amplitude sequence to obtain the damping characteristics of each oscillation; correlating the damping characteristics with the rate of change of the drain current to obtain the triggering characteristics of the parasitic oscillation; and establishing an oscillation energy distribution map based on the triggering characteristics and decay law to obtain the oscillation characteristics during the platform period.

[0108] Specifically, during the switching process of a MOSFET, the analysis of parasitic oscillations in the Miller plateau period is crucial for defect detection. First, it is necessary to identify the boundaries of the gate voltage plateau for the characteristic sequence. Specifically, the gate voltage will exhibit three distinct voltage phases during the switching process: first, it rapidly rises from 0 volts to the threshold voltage (about 3 volts), then maintains a constant voltage (about 6 - 7 volts) during the stable plateau period, and finally rapidly rises to the drive voltage (about 12 - 15 volts). The starting point of the plateau period refers to the moment when the gate voltage reaches the stable plateau level, and the ending point is the moment when the voltage begins the second rapid rise. For example, in a certain model of 1200V silicon carbide MOSFET, when a 15 - volt drive voltage is used, it can be observed that the gate voltage maintains a plateau period of about 1.5 microseconds at 6.5 volts.

[0109] Within the determined start and end moments of the plateau period, it is necessary to analyze the oscillation waveform of the drain voltage. These oscillations originate from the resonance formed by the parasitic inductance (mainly from device leads and PCB wiring, with a typical value of 10 - 20 nH) and the junction capacitance (which varies with the drain - source voltage, with a typical value of 100 - 500 pF). The peak - valley value extraction uses a local extreme detection algorithm, and a minimum amplitude threshold (usually 1% of the DC bus voltage) is set to filter out noise. For example, under the condition of a 400 - volt DC bus voltage, if the first peak of the observed oscillation waveform is 430 volts and the first valley is 370 volts, then the amplitude of the first oscillation is 30 volts. Record all peak - valley values in chronological order to form an oscillation amplitude sequence.

[0110] The decay of the oscillation amplitude sequence reflects the energy loss characteristics of the circuit. The decay coefficient is calculated using the logarithmic decay rate method: taking the natural logarithm of the amplitude ratio of adjacent oscillation periods. Under normal circumstances, due to the damping effect in the circuit (mainly from device on - resistance and PCB line losses), the oscillation will gradually decay. For example, if the amplitudes of three consecutive oscillation periods are 30 volts, 20 volts, and 13 volts respectively, then the decay coefficient of each period can be calculated to be approximately 0.4, and this value reflects the damping characteristics of the circuit. An overly small decay coefficient (such as less than 0.2) indicates insufficient circuit damping, which may lead to continuous high - frequency oscillations.

[0111] The triggering of parasitic oscillations is closely related to the rate of change of the drain current. During the Miller plateau period, the rate of change of the drain current (di / dt) is usually between several hundred amperes and several thousand amperes per microsecond. The rate - of - change data of the current can be obtained by measuring a current transformer (with a bandwidth of more than 50 MHz). For example, when the drain current changes at a rate of 1000 amperes per microsecond, if it is observed that the oscillation amplitude suddenly increases, this correlation reflects the triggering characteristics of parasitic oscillations. An overly large di / dt often excites stronger oscillations, which is directly related to the induction effect of the parasitic inductance (the induced voltage is equal to the inductance value multiplied by di / dt).

[0112] Finally, an oscillation energy distribution map needs to be established to comprehensively characterize the oscillation characteristics during the plateau period. The horizontal axis of the energy distribution map is time (covering the entire plateau period, usually 1 - 2 microseconds), and the vertical axis is frequency (usually in the range of 5 - 20 MHz). The energy intensity in the figure is represented by the shade of color. For example, it can be observed that within the first 200 nanoseconds of the plateau period, the oscillation energy near 10 MHz is the strongest and then gradually decays towards the low-frequency band. This time-frequency energy distribution characteristic can intuitively reflect the dynamic influence of parasitic parameters, especially the drift of the oscillation frequency and the attenuation process of energy. By comparing the energy distribution maps of different devices, abnormal parasitic oscillation phenomena can be effectively identified, providing an important basis for defect detection.

[0113] Please continue to refer to Figure 1 to calculate the capacitance deviation according to the parasitic characteristics and determine the defect area and its type;

[0114] In an embodiment of the present invention, calculating the capacitance deviation according to the parasitic characteristics and determining the defect area and its type includes: comparing the parasitic parameters in the gate-source region of the parasitic characteristics with a reference value to obtain a first deviation; comparing the parasitic parameters in the drain-source region of the parasitic characteristics with a reference value to obtain a second deviation; positioning the points where the first deviation and the second deviation exceed the threshold according to the chip layout coordinate system to obtain the physical coordinates of the abnormal area; matching the physical coordinates of the abnormal area with the PN junction distribution map of the power device to obtain the defect type; calculating the difference between the parasitic parameters in the area corresponding to the defect type and the standard threshold to obtain the capacitance deviation.

[0115] Specifically, in the defect detection of MOSFET devices, the measured parasitic characteristics need to be compared and analyzed with the standard values. First is the comparison of the parasitic parameters in the gate-source region, which mainly includes the gate oxide capacitance (for a 1200V silicon carbide MOSFET, the normal value is about 2 - 3 nanofarads) and the overlapping capacitance between the gate metallization layer and the source region. The reference value is selected based on the statistical average of qualified products in the same batch, and usually, the range of ±10% is used as the normal fluctuation interval. For example, if the measured value of the gate-source capacitance of a certain device is 3.5 nanofarads and the reference value is 3 nanofarads, then the first deviation is +16.7%, exceeding the normal fluctuation range, which may indicate a defect in the gate oxide layer.

[0116] The parameter comparison of the drain-source region is more complex because the parasitic capacitance (mainly the PN junction capacitance) in this region varies with the drain-source voltage. In a device with a rated voltage of 1200 volts, when the drain-source voltage is 0, the junction capacitance can reach 500 picofarads, while it drops to about 200 picofarads at a 600-volt bias voltage. The comparison needs to be carried out under the same bias conditions. For example, at a 600-volt bias, if the measured drain-source capacitance of a device is 300 picofarads and the reference value is 200 picofarads, the second deviation is +50%. Such a significant deviation is usually related to abnormal PN junction doping concentration or local breakdown.

[0117] The spatial localization of the deviation is achieved through the chip layout coordinate system. Modern power MOSFETs usually adopt a strip or hexagonal cell structure, and each chip contains thousands of basic cells. Taking a 10 mm × 10 mm chip as an example, a 100×100 grid coordinate system can be established with a resolution of 0.1 mm. If the gate-source capacitance deviation is detected to exceed 20% at the coordinate point (35, 42), then this point is marked as an abnormal area. Usually, points with a deviation exceeding ±15% are recorded, and the set of these points forms the boundary of the abnormal area.

[0118] The PN junction distribution of the power MOSFET has a specific geometric structure. In a vertical double-diffusion structure, the P-type body region is located under the source metal, and the N-type drift region is located below it until the drain. By matching the physical coordinates of the abnormal area with the PN junction distribution map, the specific type of defect can be judged. For example, if the abnormal points are mainly distributed at the edge of the gate area and show an abnormal increase in the gate-source capacitance, this usually indicates a breakdown of the gate oxide layer; if the abnormality is concentrated in the P-type region at the center of the cell and the drain-source capacitance is large, there may be a defect in the intrinsic layer (drift region); if the abnormality appears at the edge of the source metallization layer, showing instability of the parasitic capacitance, it may be the source floating phenomenon.

[0119] Finally, a quantitative evaluation of the identified defective area is required. The evaluation method is to calculate the difference between the parasitic parameters in the defective area and the standard threshold. The standard threshold is determined based on the design specifications of the device. For example, for a defect of the gate oxide layer breakdown type, if the gate-source capacitance in a certain area exceeds 1.5 times the standard value, the recorded capacitance deviation is +50%. Through this quantitative analysis, the severity of the defect can be evaluated, providing a basis for device screening and reliability prediction. For example, when the capacitance deviation in a certain area exceeds +30%, even if the device can still operate normally at present, it should be judged as a potential reliability risk.

[0120] Please continue to refer to Figure 1 , verify the stability of the defective area and its type under temperature cycling and vibration stress conditions to obtain the reliability evaluation result.

[0121] In one embodiment of the present invention, verifying the stability of the defect area and its type under temperature cycling and vibration stress conditions to obtain a reliability evaluation result includes: during the temperature cycling process, scanning the impedance characteristics of the defect area at four temperature points of -40°C, 25°C, 85°C and 125°C to obtain a temperature stress response curve; during the vibration process, measuring parameters at five frequency points of 10Hz, 100Hz, 500Hz, 1000Hz and 2000Hz required by automotive electronic standards to obtain a vibration stress response curve; extracting parameters of the temperature stress response curve at the fundamental wave, second harmonic and third harmonic of the switching frequency of the power device to obtain a temperature stress influence factor; retesting the defect position of the vibration stress response curve in three states of on, Miller platform and off to obtain a vibration stress influence factor; and obtaining a reliability evaluation result based on the acceleration effect of the temperature stress influence factor and the vibration stress influence factor on the defect parameters.

[0122] Specifically, MOSFET needs to withstand complex environmental stresses in practical applications, especially temperature cycling and mechanical vibration. In the reliability evaluation process, temperature cycling tests are first performed in accordance with automotive-grade standards. The reasons for selecting the four temperature points of -40°C, 25°C, 85°C and 125°C are: -40°C is the extreme operating temperature in winter in cold areas, when the carrier mobility of the device is significantly reduced; 25°C is the room temperature reference point; 85°C is the typical operating temperature in the engine compartment; 125°C is the maximum junction temperature limit of the power device. Stay at each temperature point for no less than 30 minutes to ensure that the temperature is fully stable. For example, when the device temperature rises from 25°C to 85°C, the gate-source capacitance may increase by 10-15%, and this change needs to be accurately captured by impedance characteristic scanning.

[0123] The vibration test follows the requirements of automotive electronic standards (such as AEC-Q101) and selects five typical frequency points of 10Hz, 100Hz, 500Hz, 1000Hz and 2000Hz. The selection of these frequency points is based on the actual working conditions of the vehicle: 10Hz corresponds to low-frequency vibration of the vehicle body, 100Hz reflects engine idling vibration, 500Hz represents medium-frequency mechanical resonance, and 1000Hz and 2000Hz correspond to high-frequency resonance and electromagnetic vibration. The vibration amplitude is set to 1.5G (about 14.7 meters per second squared) according to the standard. During the test, a professional vibration table is used to strictly fix the device and monitor the vibration parameters in real time through an acceleration sensor. For example, under 1000Hz vibration, it is necessary to observe the stress distribution of the device package pins and the fluctuation of parasitic parameters.

[0124] The parameter extraction of the temperature stress response curve focuses on the characteristic frequency points of the power device. For a device with a switching frequency of 100 kHz, it is necessary to analyze the response characteristics at 100 kHz (fundamental wave), 200 kHz (second harmonic), and 300 kHz (third harmonic). At each frequency point, three parameters are mainly concerned: the impedance amplitude (reflecting the temperature coefficient of the parasitic capacitance, with a typical value of 0.2% / °C), the phase angle (reflecting the dynamic characteristics of the parasitic parameters), and the quality factor (characterizing the loss characteristics). Taking the gate-source capacitance as an example, if the impedance amplitude measured at 85°C is 15% lower than that at 25°C, and the second harmonic component increases abnormally, this temperature stress influence factor indicates a potential reliability risk.

[0125] The vibration stress response curve needs to be analyzed under three key operating states of the device. In the turn-on state, the integrity of the gate drive waveform is concerned (vibration may cause distortion of the drive signal); during the Miller plateau, the change of parasitic oscillation is mainly monitored (mechanical vibration may exacerbate electrical oscillation); in the turn-off state, the stability of the drain-source voltage needs to be observed. For example, when vibrating at 1000 Hz, if the amplitude of the parasitic oscillation during the Miller plateau increases by 30% compared with the static condition, this vibration stress influence factor indicates a potential problem with the mechanical stability of the device.

[0126] Finally, by comprehensively analyzing the effects of temperature and vibration stress, the development trend of the defect can be evaluated. The acceleration effect is mainly reflected in three aspects: first, the thermo-mechanical stress caused by temperature cycling may accelerate the deterioration of the gate oxide layer (the failure rate approximately doubles for every 10°C increase); second, the mechanical fatigue caused by vibration will affect the reliability of the wire bonding; finally, the coupling effect of the two stresses often produces a synergistic effect. For example, if the deviation of the parasitic parameters in a certain defect area increases by more than 50% under 85°C and 1000 Hz vibration compared with the case of applying stress alone, the expected life of the device needs to be reduced to half of the nominal value. This quantitative reliability assessment result provides an important basis for the screening and application design of the device.

[0127] The method for detecting defects in the new energy vehicle electronic control component in the embodiment of the present invention has been described above. Next, the defect detection device for the new energy vehicle electronic control component in the embodiment of the present invention will be described. Please refer to Figure 2 One embodiment of the defect detection device for the new energy vehicle electronic control component in the embodiment of the present invention includes:

[0128] A signal injection module 201, configured to apply an alternating current signal in the range of 100 kHz - 10 MHz to the electronic control component, and obtain the impedance response characteristics of each parasitic coupling region of the power device by using a differential detection method;

[0129] The network analysis module 202 is configured to perform multi-port network analysis on the impedance response characteristics and extract the distributed capacitance values of each parasitic coupling region;

[0130] The time-frequency processing module 203 is configured to perform time-frequency characteristic analysis on the distributed capacitance values to obtain the parasitic characteristics during the switching process;

[0131] The defect identification module 204 is configured to calculate the capacitance deviation amount according to the parasitic characteristics and determine the defect region and its type;

[0132] The reliability evaluation module 205 is configured to verify the stability of the defect region and its type under temperature cycle and vibration stress conditions to obtain a reliability evaluation result.

[0133] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structural transformation made by using the content of the specification and drawings of the present invention under the inventive concept of the present invention, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A defect detection method for electric control components of new energy vehicles, characterized in that: include: Apply an AC signal in the range of 100kHz-10MHz to the electronic control component, and use a differential detection method to obtain the impedance response characteristics of each parasitic coupling area of ​​the power device; Performing multi-port network analysis on the impedance response characteristics to extract the distributed capacitance value of each parasitic coupling area; Performing time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process; Calculating capacitance deviation according to the parasitic characteristics, and determining defect areas and types thereof; The stability of the defect area and its type is verified under temperature cycling and vibration stress conditions to obtain reliability evaluation results.

2. The defect detection method for electric control components of new energy vehicles according to claim 1 is characterized in that: The method of applying an AC signal in the range of 100kHz-10MHz to the electric control component and obtaining the impedance response characteristics of each parasitic coupling region of the power device by a differential detection method includes: A high-frequency response probe is arranged at a first parasitic coupling surface between the gate and source of the power device and a second parasitic coupling surface between the drain and source as a reference detection end; A differential probe is arranged on the gate-drain coupling surface of the Miller platform area and the coupling surface between the power supply and the ground of the power loop as a differential detection terminal; Applying an AC scanning signal with an initial frequency of 100 kHz to the reference detection end, and gradually increasing the excitation frequency to 10 MHz in 50 kHz steps according to the switching frequency characteristics of the power device; The high frequency response data of the reference detection end and the differential detection end are collected, and the impedance response characteristics of each parasitic coupling region are calculated.

3. The defect detection method for electric control components of new energy vehicles according to claim 2 is characterized in that: The method of applying an AC scanning signal with an initial frequency of 100 kHz to the reference detection end and gradually increasing the excitation frequency to 10 MHz in 50 kHz steps according to the switching frequency characteristics of the power device includes: The gate drive voltage when the power device is turned on is used as the reference, and the initial amplitude of the AC scanning signal is set to 30% of it; Applying a scanning signal with an initial frequency of 100 kHz to the reference detection end, and recording a gate opening threshold point of a power device; Dynamically calculate the signal application time of the next frequency point according to the response time of the gate opening threshold point; The signal application time is compensated according to a 50kHz step amount to eliminate the phase delay caused by the parasitic loop; After compensation, the signal frequency is gradually increased to 10MHz to maintain the trigger synchronization of each frequency point.

4. The defect detection method for electric control components of new energy vehicles according to claim 2 is characterized in that: The collecting high frequency response data of the reference detection end and the differential detection end and calculating the impedance response characteristics of each parasitic coupling region includes: Performing amplitude normalization processing on the high frequency response data of the reference detection end to obtain a reference response sequence; Calibrate the high frequency response data of the differential detection end according to the reference response sequence to obtain a differential response sequence; Calculating the phase difference between the reference response sequence and the differential response sequence to obtain a coupling phase characteristic; Compensating the high frequency response data according to the coupling phase characteristics to obtain an actual impedance value; The actual impedance value is mapped according to the physical position of the parasitic coupling region to obtain an impedance response characteristic.

5. The defect detection method for electric control components of new energy vehicles according to claim 1 is characterized in that: The performing multi-port network analysis on the impedance response characteristics to extract the distributed capacitance value of each parasitic coupling area includes: Performing fast Fourier transform on the impedance response characteristics in the gate drive circuit and the power main circuit respectively to obtain dual-circuit amplitude-frequency characteristics; The dual-loop amplitude-frequency characteristics are used to establish interconnection network equations according to three sets of coupling relationships between gate-source, drain-source and gate-drain, and the transmission function of each coupling region is obtained; Performing odd-even mode separation on the transmission function to obtain common-mode and differential-mode impedance components; Reconstructing the common-mode and differential-mode impedance components within a fixed time window of the Miller platform to obtain equivalent parameters of each coupling region; The equivalent parameters are corrected and compensated according to the actual switching frequency point to obtain the distributed capacitance value of each parasitic coupling area.

6. The defect detection method for electric control components of new energy vehicles according to claim 1 is characterized in that: The performing time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process includes: The distributed capacitance value is segmented in time sequence according to the turn-on phase, Miller platform phase and turn-off phase of the power device to obtain three characteristic sequences; Calculating the voltage change rate of the characteristic sequences in the on-phase and the off-phase to obtain the switch stress characteristics; Performing parasitic oscillation analysis on the characteristic sequence of the Miller platform phase to obtain the oscillation characteristics of the platform phase; Based on the voltage reversal point of the switching cycle, the switch stress characteristics and the plateau oscillation characteristics are synchronously marked to obtain the timing characteristics of the parasitic parameters; The timing characteristics are reconstructed under different switching rate conditions to obtain parasitic characteristics during the switching process.

7. The defect detection method for electric control components of new energy vehicles according to claim 6 is characterized in that: The parasitic oscillation analysis is performed on the characteristic sequence of the Miller platform phase to obtain the oscillation characteristics of the platform phase, including: Identify the boundary of the gate voltage plateau period of the characteristic sequence to obtain the start and end time of the Miller platform; Extracting peak and valley values ​​of the oscillation waveform of the drain voltage within the start and end times to obtain an oscillation amplitude sequence; Calculating the attenuation coefficient of the oscillation amplitude sequence to obtain the damping characteristics of each oscillation; Correlating the damping characteristic with the rate of change of the drain current to obtain a triggering characteristic of the parasitic oscillation; An oscillation energy distribution diagram is established according to the trigger characteristics and attenuation law to obtain the plateau oscillation characteristics.

8. The defect detection method for electric control components of new energy vehicles according to claim 1 is characterized in that: The step of calculating the capacitance deviation according to the parasitic characteristics and determining the defect area and its type includes: Comparing the parasitic parameters of the gate-source region in the parasitic characteristics with a reference value to obtain a first deviation; Comparing the parasitic parameters of the drain-source region in the parasitic characteristics with the reference value to obtain a second deviation; Locate the points where the first deviation and the second deviation exceed the threshold value according to the chip layout coordinate system to obtain the physical coordinates of the abnormal area; Matching the physical coordinates of the abnormal area with the PN junction distribution map of the power device to obtain the defect type; The difference between the parasitic parameters of the area corresponding to the defect type and the standard threshold is calculated to obtain the capacitance deviation.

9. The defect detection method for electric control components of new energy vehicles according to claim 1, characterized in that: The stability of the defect area and its type is verified under temperature cycle and vibration stress conditions to obtain reliability evaluation results, including: During the temperature cycle, the impedance characteristics of the defect area are scanned at four temperature points: -40°C, 25°C, 85°C and 125°C, and the temperature stress response curve is obtained; During the vibration process, the parameters are measured at five frequency points of 10Hz, 100Hz, 500Hz, 1000Hz and 2000Hz as required by automotive electronic standards to obtain the vibration stress response curve; Extract parameters of the temperature stress response curve at the fundamental wave, second harmonic and third harmonic of the switching frequency of the power device to obtain the temperature stress influencing factor; The vibration stress response curve is re-measured at the defect position in three states: on, Miller platform and off, to obtain the vibration stress influencing factor; According to the acceleration effect of the temperature stress influencing factor and the vibration stress influencing factor on the defect parameters, a reliability evaluation result is obtained.

10. A defect detection device for electric control components of new energy vehicles, characterized in that: The defect detection device of the electric control component of the new energy vehicle comprises: The signal injection module is used to apply an AC signal in the range of 100kHz-10MHz to the electronic control component, and obtain the impedance response characteristics of each parasitic coupling area of ​​the power device by differential detection; A network analysis module, used to perform multi-port network analysis on the impedance response characteristics and extract the distributed capacitance value of each parasitic coupling area; A time-frequency processing module, used to perform time-frequency characteristic analysis on the distributed capacitance value to obtain parasitic characteristics during the switching process; A defect recognition module, used to calculate the capacitance deviation according to the parasitic characteristics, and determine the defect area and its type; The reliability evaluation module is used to verify the stability of the defect area and its type under temperature cycle and vibration stress conditions to obtain a reliability evaluation result.

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