Method for testing semiconductor element

Abstract

The invention provides a method for testing a semiconductor element. The method includes: providing a wafer on a chuck; moving the chuck to a first expected position below the probe card; moving the chuck from the first expected position to a second expected position, so that the plurality of crystal grains of the wafer are in contact with the plurality of probes of the probe card; testing a first portion of a die of the wafer; moving the chuck to a second expected position, so that the crystal grains of the wafer abut against the probes of the probe card; and testing a second portion of the die of the wafer. The test method of the semiconductor element not only can improve the yield of a plurality of crystal grains of the wafer, but also can avoid the problem of excessive needle marks.

Description

Technical Field

[0001] The invention relates to a testing method for a semiconductor element. Background Art

[0002] Since the probe card is allowed to perform a single test with only a single touchdown, there are 1536 devices under test (DUT) waiting for a single test. During the test, the yield may be poor due to excessive temperature or insufficient voltage, so the number of DUTs for a single test can be reduced by breaking the entire test into multiple touchdowns, and the DUTs can be repeatedly tested at fixed coordinates without leaving the probe of the probe card. However, during the subsequent probe mark inspection (PMI), the probes are checked and returned to the original coordinates for the next touchdown, resulting in too many needle marks on the DUT, which cannot meet customer needs. Summary of the invention

[0003] In view of this, an object of the present invention is to provide a testing method for a semiconductor device that can solve the above-mentioned problem.

[0004] In order to achieve the above-mentioned purpose, according to one embodiment of the present invention, a testing method of a semiconductor element includes: moving the chuck to a first expected position located below a probe card; moving the chuck from the first expected position to a second expected position so that multiple grains of the wafer contact multiple probes of the probe card; testing a first part of the grains of the wafer; moving the chuck to the second expected position so that the grains of the wafer abut against the probes of the probe card; and testing a second part of the grains of the wafer.

[0005] In one or more embodiments of the present invention, moving the chuck to a first desired position below the probe card causes the dies of the wafer to not contact the probes of the probe card.

[0006] In one or more embodiments of the present invention, the wafer contacts the probes of the probe card when the chuck is in the second desired position.

[0007] In one or more embodiments of the present invention, moving the chuck from the first desired position to the second desired position substantially moves the chuck upward.

[0008] In one or more embodiments of the present invention, the step of testing the second portion of the die of the wafer is performed after the step of testing the first portion of the die of the wafer.

[0009] In one or more embodiments of the present invention, the step of testing the second portion of the die on the wafer and the step of testing the first portion of the die on the wafer are performed when the chuck is in the second expected position.

[0010] In one or more embodiments of the present invention, the step of moving the chuck to the second desired position so that the die of the wafer abuts against the probe of the probe card is performed after the step of testing the first portion of the die of the wafer.

[0011] In one or more embodiments of the present invention, moving the chuck to the second desired position so that the die of the wafer abuts against the probes of the probe card substantially maintains the chuck at the second desired position.

[0012] In one or more embodiments of the present invention, the step of testing the second portion of the die on the wafer is performed after the step of moving the chuck to the second desired position so that the die on the wafer abuts against the probes of the probe card.

[0013] In one or more embodiments of the present invention, the method for testing a semiconductor device further includes moving the chuck from the second expected position to the first expected position after testing the second portion of the die on the wafer.

[0014] In order to achieve the above-mentioned purpose, according to one embodiment of the present invention, a testing method of a semiconductor element includes: moving a chuck to a first expected position located below a probe card, wherein a wafer is disposed on the chuck; moving the chuck from the first expected position to a second expected position so that a plurality of grains of the wafer contact a plurality of probes of the probe card; testing a first portion of the grains of the wafer; moving the chuck to a second expected position so that the grains of the wafer abut against the probes of the probe card; and testing a second portion of the grains of the wafer, wherein the second portion of the grains of the wafer is different from the first portion of the grains of the wafer.

[0015] In one or more embodiments of the present invention, moving the chuck to a first desired position below the probe card causes the dies of the wafer to not contact the probes of the probe card.

[0016] In one or more embodiments of the present invention, the wafer contacts the probes of the probe card when the chuck is in the second desired position.

[0017] In one or more embodiments of the present invention, moving the chuck from the first desired position to the second desired position substantially moves the chuck upward.

[0018] In one or more embodiments of the present invention, the step of testing the second portion of the die of the wafer is performed after the step of testing the first portion of the die of the wafer.

[0019] In one or more embodiments of the present invention, the step of testing the second portion of the die on the wafer and the step of testing the first portion of the die on the wafer are performed when the chuck is in the second expected position.

[0020] In one or more embodiments of the present invention, the step of moving the chuck to the second desired position so that the die of the wafer abuts against the probe of the probe card is performed after the step of testing the first portion of the die of the wafer.

[0021] In one or more embodiments of the present invention, moving the chuck to the second desired position so that the die of the wafer abuts against the probes of the probe card substantially maintains the chuck at the second desired position.

[0022] In one or more embodiments of the present invention, the step of testing the second portion of the die on the wafer is performed after the step of moving the chuck to the second desired position so that the die on the wafer abuts against the probes of the probe card.

[0023] In one or more embodiments of the present invention, the method for testing a semiconductor device further includes moving the chuck from the second expected position to the first expected position after testing the second portion of the die on the wafer.

[0024] In summary, in the testing method of the semiconductor element of the present invention, since the step of moving the chuck to the second expected position so that the multiple grains of the wafer abut against the multiple probes of the probe card is essentially to keep the chuck at the second expected position, and since the step of testing the first part of the multiple grains of the wafer and the step of testing the second part of the multiple grains of the wafer are performed when the chuck is at the second expected position, the probe card can be tested without leaving the multiple grains of the wafer, thereby achieving the effect of reducing the appearance of needle marks on the multiple grains of the wafer. In the testing method of the semiconductor element of the present invention, since the step of testing the first part of the multiple grains of the wafer and the step of testing the second part of the multiple grains of the wafer are performed separately, the probe card can perform multiple tests at the same coordinate without moving the chuck, thereby achieving the effect of avoiding the problem of excessive temperature or insufficient voltage during the test process. Overall, the testing method of the semiconductor element of the present invention can not only improve the yield of multiple grains of the wafer, but also avoid the problem of too many needle marks.

[0025] The above description is only used to illustrate the problems to be solved by the present invention, the technical means to solve the problems, and the effects produced, etc. The specific details of the present invention will be described in detail in the following implementation methods and related drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

[0027] Figure 1 FIG. 4 is a flow chart illustrating a method for testing a semiconductor device according to an embodiment of the present invention.

[0028] Figure 2FIG. 4 is a schematic diagram illustrating a wafer probe machine according to an embodiment of the present invention.

[0029] Figure 3 FIG. 4 is a cross-sectional view showing an intermediate stage of testing a semiconductor device according to an embodiment of the present invention.

[0030] Figure 4 FIG. 4 is a cross-sectional view showing an intermediate stage of testing a semiconductor device according to an embodiment of the present invention.

[0031] Figure 5 FIG. 4 is a cross-sectional view showing an intermediate stage of testing a semiconductor device according to an embodiment of the present invention.

[0032] Figure 6 FIG. 4 is a cross-sectional view showing an intermediate stage of testing a semiconductor device according to an embodiment of the present invention.

[0033] Figure 7 FIG. 4 is a cross-sectional view showing an intermediate stage of testing a semiconductor device according to an embodiment of the present invention.

[0034] Figure 8 FIG. 4 is a cross-sectional view showing an intermediate stage of testing a semiconductor device according to an embodiment of the present invention.

[0035] Fig. 9 FIG. 4 is a cross-sectional view showing an intermediate stage of testing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following disclosure provides many different embodiments or embodiments for realizing the different features of the provided patent subject matter. The specific embodiments of the components and configurations are described below to simplify the present invention. Of course, these are only embodiments and are not intended to be limiting. For example, in the following description, a first feature is formed above or on a second feature and may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in a variety of embodiments. Such repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0037] Additionally, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship between one element or feature and another element or feature shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative terms used herein may likewise be interpreted accordingly.

[0038] As used herein, "approximately," "about," "roughly," or "substantially" generally means within 20%, or within 10%, or within 5% of a given value or range. The numerical values ​​given herein are approximate, meaning that if not explicitly stated, the term "approximately," "about," "roughly," or "substantially" can be inferred.

[0039] Please refer to Figure 1 . Figure 1 FIG. 4 is a flow chart of a semiconductor device testing method M according to an embodiment of the present invention. Figure 1 The method M shown includes step S101, step S102, step S103, step S104, step S105, step S106 and step S107. For a better understanding of step S101, please refer to Figure 1 , Figure 2 as well as Figure 3 For a better understanding of step S102, please refer to Figure 1 as well as Figure 4 For a better understanding of step S103, please refer to Figure 1 as well as Figure 5 For a better understanding of step S104, please refer to Figure 1 as well as Figure 6 For a better understanding of step S105, please refer to Figure 1 as well as Figure 7 For a better understanding of step S106, please refer to Figure 1 as well as Figure 8 For a better understanding of step S107, please refer to Figure 1 as well as Fig. 9 .

[0040] Step S101 , step S102 , step S103 , step S104 , step S105 , step S106 , and step S107 are described in detail below.

[0041] Step S101 : providing a wafer WF on the chuck 120 .

[0042] Please refer to Figure 2 as well as Figure 3 . Figure 2FIG. 1 is a schematic diagram of a wafer probe machine 100 according to an embodiment of the present invention. Figure 3 FIG. 1 is a cross-sectional view of an intermediate stage of testing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, in this embodiment, a wafer prober 100 is provided. The wafer prober 100 includes a probe card 110, a chuck 120, and a display device SCR. The probe card 110 is disposed above the chuck 120. Figure 2 As shown, the probe card 110 is configured to perform one or more tests on the wafer WF. The wafer WF is provided on the chuck 120. More specifically, the chuck 120 is configured to support the wafer WF. In some embodiments, the wafer WF can be provided on the chuck 120 by a robot, a mechanical arm or other suitable lifting device. The display device SCR is configured to display images of the probe card 110, the chuck 120 and the wafer WF. In this embodiment, the wafer probe machine 100 further includes a processing unit (not shown). The processing unit is configured to move the chuck 120 located in the wafer probe machine 100. The processing unit is further configured to test the wafer WF via the probe card 110.

[0043] Please continue to refer to Figure 3 .like Figure 3 As shown, the probe card 110 includes a plurality of probes 112. The plurality of probes 112 are configured to transmit test signals from a processing unit of the wafer prober 100. The plurality of probes 112 correspond to a plurality of dies ( Figure 3 For simplicity of explanation, Figure 3 Nine probes 112 are shown. However, the present invention is not intended to be limited to the number of probes 112 of the probe card 110.

[0044] Step S102 : moving the chuck 120 to a first expected position P1 below the probe card 110 .

[0045] Please refer to Figure 4 . Figure 4 FIG. 1 is a cross-sectional view of an intermediate stage of testing a semiconductor device according to an embodiment of the present invention. Figure 4 As shown, in this embodiment, the chuck 120 is moved to the first expected position P1 below the probe card 110 through operation B. Specifically, operation B is performed so that the chuck 120 with the wafer WF placed thereon is moved to the first expected position P1 below the probe card 110. In some embodiments, the chuck 120 is moved laterally to the first expected position P1. Figure 4 As shown, the chuck 120 moves relative to the probe card 110 . In other words, the probe card 110 is relatively stationary. When the chuck 120 is at the first expected position P1 , the plurality of dies on the wafer WF do not contact the plurality of probes 112 of the probe card 110 .

[0046] In some embodiments, the step of providing the wafer WF on the chuck 120 (ie, step S101 ) is performed before the step of moving the chuck 120 to the first expected position P1 below the probe card 110 (ie, step S102 ).

[0047] In one use scenario, the processing unit of the wafer prober 100 performs operation B to move the chuck 120 to the first intended position P1 . More specifically, the processing unit laterally moves the chuck 120 to the first intended position P1 so that the dies of the wafer WF do not contact the probes 112 of the probe card 110 .

[0048] Step S103: moving the chuck 120 from the first expected position P1 to the second expected position P2.

[0049] Please refer to Figure 5 . Figure 5 FIG. 1 is a cross-sectional view of an intermediate stage of testing a semiconductor device according to an embodiment of the present invention. Figure 5 As shown, in this embodiment, the chuck 120 is moved from the first expected position P1 to the second expected position P2 by operation Z1. Specifically, operation Z1 is performed so that the chuck 120 with the wafer WF placed thereon is moved from the first expected position P1 to the second expected position P2, so that the plurality of dies of the wafer WF contact the plurality of probes 112 of the probe card 110. In some embodiments, the chuck 120 is moved upward to the second expected position P2. Figure 5 As shown, the chuck 120 moves relative to the probe card 110. In other words, the probe card 110 is relatively stationary. When the chuck 120 is at the second expected position P2, the multiple dies of the wafer WF contact the multiple probes 112 of the probe card 110. In some embodiments, the operation Z1 is performed so that the multiple dies of the wafer WF abut against the multiple probes 112 of the probe card 110. If the processing unit senses that the multiple dies of the wafer WF abut against the multiple probes 112 of the probe card 110, the processing unit terminates the operation Z1 to keep the chuck 120 with the wafer WF placed thereon at the second expected position P2.

[0050] In some embodiments, the step of moving the chuck 120 from the first expected position P1 to the second expected position P2 (ie, step S103 ) is performed after the step of moving the chuck 120 to the first expected position P1 under the probe card 110 (ie, step S102 ).

[0051] In one use scenario, the processing unit of the wafer prober 100 performs operation Z1 to move the chuck 120 from the first intended position P1 to the second intended position P2. More specifically, the processing unit moves the chuck 120 upward to the second intended position P2, so that the plurality of dies of the wafer WF contact the plurality of probes 112 of the probe card 110.

[0052] Step S104 : testing a first portion of the plurality of dies D on the wafer WF.

[0053] Please refer to Figure 6 . Figure 6 FIG. 1 is a cross-sectional view of an intermediate stage of testing a semiconductor device according to an embodiment of the present invention. Figure 6 As shown, in this embodiment, a plurality of dies D of the wafer WF are tested by operation T1. Specifically, operation T1 is performed so that the first portion of the plurality of dies D is tested by the plurality of probes 112 of the probe card 110. Figure 6 As shown, for example, the plurality of die D include die D1, die D2, die D3, die D4, die D5, die D6, die D7, die D8, die D9 and die D10. Die D1, die D2, die D3, die D4 and die D5 are the first part of the plurality of die D of the wafer WF, and die D6, die D7, die D8, die D9 and die D10 are the second part of the plurality of die D of the wafer WF. In other words, the second part of the plurality of die D of the wafer WF is different from the first part of the plurality of die D of the wafer WF. Each die D includes a plurality of test contact pads PD. As shown Figure 6 As shown, the plurality of probes 112 of the probe card 110 contact the plurality of test contact pads PD of the plurality of dies D of the wafer WF, and only the first portion of the plurality of dies D of the wafer WF (e.g., die D1, die D2, die D3, die D4, and die D5) is tested. In other words, the second portion of the plurality of dies D of the wafer WF (e.g., die D6, die D7, die D8, die D9, and die D10) is not tested in operation T1.

[0054] In some embodiments, the step of testing the first portion of the plurality of dies D of the wafer WF (ie, step S104 ) is performed after the step of moving the chuck 120 from the first expected position P1 to the second expected position P2 (ie, step S103 ).

[0055] In one use scenario, the processing unit of the wafer prober 100 performs operation T1 to test the first portion of the plurality of dies D of the wafer WF. More specifically, the plurality of probes 112 of the probe card 110 contact the plurality of test contact pads PD of the plurality of dies D of the wafer WF, but the processing unit sends the test signal only to the first portion of the plurality of dies D of the wafer WF via the plurality of probes 112 of the probe card 110. Figure 6 As shown, in some embodiments, after performing operation T1 , probe marks MK are generated on a plurality of test contact pads PD at a first portion of a plurality of dies D on the wafer WF.

[0056] Step S105: moving the chuck 120 to a second expected position P2.

[0057] Please refer to Figure 7 . Figure 7 FIG. 1 is a cross-sectional view of an intermediate stage of testing a semiconductor device according to an embodiment of the present invention. Figure 7 As shown, in this embodiment, the chuck 120 is moved to the second expected position P2 by operation Z2. Specifically, operation Z2 is performed so that the chuck 120 with the wafer WF placed thereon is moved to the second expected position P2, so that the plurality of dies D of the wafer WF abut against the plurality of probes 112 of the probe card 110. In some embodiments, during the execution of operation Z2, the chuck 120 is substantially moved upward to the second expected position P2. Figure 7 As shown, the chuck 120 moves relative to the probe card 110. In other words, the probe card 110 is relatively stationary. When the chuck 120 is at the second expected position P2, the multiple dies D of the wafer WF contact the multiple probes 112 of the probe card 110. In some embodiments, operation Z2 (i.e., step S105) substantially keeps the chuck 120 at the second expected position P2. More specifically, since the chuck 120 with the wafer WF placed thereon remains at the second expected position P2 after performing operation T1, even if the processing unit intends to move the chuck 120 during the execution of operation T1, the chuck 120 may actually stay at the second expected position P2. If the processing unit senses that the multiple dies D of the wafer WF abut against the multiple probes 112 of the probe card 110, the processing unit terminates operation Z2 to keep the chuck 120 with the wafer WF placed thereon at the second expected position P2.

[0058] In some embodiments, the step of moving the chuck 120 to the second expected position P2 to cause the plurality of dies D of the wafer WF to abut against the plurality of probes 112 of the probe card 110 (ie, step S105 ) is performed after the step of testing the first portion of the plurality of dies D of the wafer WF (ie, step S104 ).

[0059] In one use scenario, the processing unit of the wafer prober 100 performs operation Z2 to move the chuck 120 to the second expected position P2. More specifically, the processing unit moves the chuck 120 upward to the second expected position P2 until the plurality of dies D of the wafer WF contact the plurality of probes 112 of the probe card 110. However, in some embodiments, since the chuck 120 has been moved to the second expected position P2 during the previous operation, the chuck 120 is substantially maintained at the second expected position P2 during the execution of operation Z2.

[0060] Step S106 : testing the second portion of the plurality of dies D on the wafer WF.

[0061] Please refer to Figure 8 . Figure 8 FIG. 1 is a cross-sectional view of an intermediate stage of testing a semiconductor device according to an embodiment of the present invention. Figure 8 As shown, in this embodiment, the plurality of dies D of the wafer WF are tested by operation T2. ​​Specifically, operation T2 is performed so that the second portions of the plurality of dies D are tested by the plurality of probes 112 of the probe card 110. Figure 8 As shown, for example, die D6, die D7, die D8, die D9 and die D10 are the second part of the plurality of die D of the wafer WF. In other words, the second part of the plurality of die D of the wafer WF is different from the first part of the plurality of die D of the wafer WF. Figure 8 As shown, the plurality of probes 112 of the probe card 110 contact the plurality of test contact pads PD of the plurality of dies D of the wafer WF, and only the second portion of the plurality of dies D of the wafer WF (e.g., die D6, die D7, die D8, die D9, and die D10) is tested. In other words, the first portion of the plurality of dies D of the wafer WF (e.g., die D1, die D2, die D3, die D4, and die D5) is not tested in operation T2 because the first portion of the plurality of dies D of the wafer WF has been tested during the execution of operation T1.

[0062] In some embodiments, the step of testing the second portion of the plurality of dies D on the wafer WF (i.e., step S106) is performed after the step of moving the chuck 120 to the second expected position P2 so that the second portion of the plurality of dies D on the wafer WF abuts against the plurality of probes 112 of the probe card 110 (i.e., step S105). In some embodiments, the step of testing the second portion of the plurality of dies D on the wafer WF (i.e., step S106) is performed after the step of testing the first portion of the plurality of dies D on the wafer WF (i.e., step S104). In some embodiments, the step of testing the first portion of the plurality of dies D on the wafer WF (i.e., step S104) and the step of testing the second portion of the plurality of dies D on the wafer WF (i.e., step S106) are performed when the chuck 120 is at the second expected position P2, as shown in FIG. Figure 6 as well as Figure 8 More specifically, the chuck 120 with the wafer WF placed thereon stays at the second expected position P2 without changing the coordinates during the execution of the operations T1 and T2.

[0063] In one use scenario, the processing unit of the wafer prober 100 performs operation T2 to test the second portion of the plurality of dies D of the wafer WF. More specifically, the plurality of probes 112 of the probe card 110 contact the plurality of test contact pads PD of the plurality of dies D of the wafer WF, but the processing unit only sends the test signal to the second portion of the plurality of dies D of the wafer WF via the plurality of probes 112 of the probe card 110. Figure 8As shown, in some embodiments, after operation T2 is performed, probe marks MK are generated on a plurality of test contact pads PD at a second location of a plurality of dies D on the wafer WF.

[0064] Step S107 : moving the chuck 120 from the second expected position P2 to the first expected position P1 .

[0065] Please refer to Fig. 9 . Fig. 9 FIG. 1 is a cross-sectional view of an intermediate stage of testing a semiconductor device according to an embodiment of the present invention. Fig. 9 As shown, in this embodiment, the chuck 120 is moved from the second expected position P2 to the first expected position P1 through operation C. Specifically, operation C is performed so that the chuck 120 with the wafer WF placed thereon is moved from the second expected position P2 to the first expected position P1, so that the plurality of dies D of the wafer WF are away from the plurality of probes 112 of the probe card 110. In some embodiments, the chuck 120 is moved downward to the first expected position P1. Fig. 9 As shown, the chuck 120 moves relative to the probe card 110. In other words, the probe card 110 is relatively stationary. When the chuck 120 is at the first expected position P1, the plurality of dies D of the wafer WF do not contact the plurality of probes 112 of the probe card 110. In other words, the plurality of dies D of the wafer WF leave the plurality of probes 112 of the probe card 110. In some embodiments, performing operation C causes the plurality of dies D of the wafer WF to not abut against the plurality of probes 112 of the probe card 110. After performing operation C, the processing unit controls another device to perform a probe mark inspection (PMI) process on the plurality of dies D of the wafer WF.

[0066] In some embodiments, the step of moving the chuck 120 from the second expected position P2 to the first expected position P1 (ie, step S107 ) is performed after the step of testing the second portion of the plurality of dies D of the wafer WF (ie, step S106 ).

[0067] In one use scenario, the processing unit of the wafer prober 100 performs operation C to move the chuck 120 from the second expected position P2 to the first expected position P1. More specifically, the processing unit moves the chuck 120 downward to the first expected position P1, so that the plurality of dies D of the wafer WF are away from the plurality of probes 112 of the probe card 110.

[0068] By implementing the present invention Figure 1 In the method M shown, the wafer probe machine 100 can perform a complete test without the plurality of probes 112 leaving the plurality of dies D of the wafer WF, thereby reducing the probe marks MK generated on the test contact pads PD.

[0069] From the above detailed description of the specific embodiments of the present invention, it can be clearly seen that in the test method of the semiconductor element of the present invention, since the step of moving the chuck to the second expected position so that the multiple grains of the wafer abut against the multiple probes of the probe card is essentially to keep the chuck at the second expected position, and since the step of testing the first part of the multiple grains of the wafer and the step of testing the second part of the multiple grains of the wafer are performed when the chuck is at the second expected position, the probe card can be tested without leaving the multiple grains of the wafer, thereby achieving the effect of reducing the appearance of needle marks on the multiple grains of the wafer. In the test method of the semiconductor element of the present invention, since the step of testing the first part of the multiple grains of the wafer and the step of testing the second part of the multiple grains of the wafer are performed separately, the probe card can perform multiple tests at the same coordinate without moving the chuck, thereby achieving the effect of avoiding the problem of excessive temperature or insufficient voltage during the test process. Overall, the test method of the semiconductor element of the present invention can not only improve the yield of the multiple grains of the wafer, but also avoid the problem of too many needle marks.

[0070] Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0071] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present case. Those skilled in the art should understand that the above content can be easily used as a basis for designing or modifying other changes without departing from the spirit and scope of the present case to implement the same purpose and / or achieve the same advantages of the embodiments described herein. The above content should be understood as an example of the present invention, and its scope of protection should be based on the claims.

[0072]

Explanation of symbols

[0073] 100: Wafer probe tester

[0074] 110:Probe Card

[0075] 112: Probe

[0076] 120: Chuck

[0077] B,C,T1,T2,Z1,Z2: Operation

[0078] D,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10: Grain

[0079] M: Method

[0080] MK: Needle Mark

[0081] P1: First expected position

[0082] P2: Second expected position

[0083] PD: Test contact pad

[0084] S101, S102, S103, S104, S105, S106, S107: Steps

[0085] SCR: Display device

[0086] WF: Wafer.

Claims

1. A method for testing a semiconductor device, characterized in that: Include: providing a wafer on a chuck; moving the chuck to a first desired position below the probe card; Moving the chuck from the first expected position to a second expected position so that a plurality of dies on the wafer contact a plurality of probes on the probe card; testing a first portion of the plurality of dies on the wafer; moving the chuck to the second expected position so that the plurality of dies of the wafer abut against the plurality of probes of the probe card; and A second portion of the plurality of dies of the wafer is tested.

2. The method according to claim 1, characterized in that The moving the chuck to the first expected position below the probe card causes the plurality of dies of the wafer to not contact the plurality of probes of the probe card.

3. The method according to claim 1, characterized in that When the chuck is in the second expected position, the wafer contacts the plurality of probes of the probe card.

4. The method according to claim 1, characterized in that: The moving the chuck from the first expected position to the second expected position is substantially moving the chuck upward.

5. The method according to claim 1, characterized in that The step of testing the second portion of the plurality of dies on the wafer is performed after the step of testing the first portion of the plurality of dies on the wafer.

6. The method according to claim 1, characterized in that The step of testing the second portion of the plurality of dies on the wafer and the step of testing the first portion of the plurality of dies on the wafer are performed when the chuck is at the second expected position.

7. The method according to claim 1, characterized in that The step of moving the chuck to the second expected position so that the plurality of dies of the wafer abut against the plurality of probes of the probe card is performed after the step of testing the first portions of the plurality of dies of the wafer.

8. The method according to claim 1, characterized in that The moving the chuck to the second desired position causes the plurality of dies of the wafer to abut against the plurality of probes of the probe card to substantially maintain the chuck at the second desired position.

9. The method according to claim 1, characterized in that: The step of testing the second portion of the plurality of dies on the wafer is performed after the step of moving the chuck to the second expected position so that the plurality of dies on the wafer abut against the plurality of probes of the probe card.

10. The method according to claim 1, characterized in that Further comprising moving the chuck from the second expected position to the first expected position after testing the second portion of the plurality of dies on the wafer.

11. A method for testing a semiconductor device, characterized in that: Include: moving a chuck to a first desired position below the probe card, wherein the wafer is disposed on the chuck; Moving the chuck from the first expected position to a second expected position so that a plurality of dies on the wafer contact a plurality of probes on the probe card; testing a first portion of the plurality of dies on the wafer; moving the chuck to the second expected position so that the plurality of dies of the wafer abut against the plurality of probes of the probe card; and A second portion of the plurality of dies on the wafer is tested, wherein the second portion of the plurality of dies on the wafer is different from the first portion of the plurality of dies on the wafer.

12. The method according to claim 11, characterized in that The moving the chuck to the first expected position below the probe card causes the plurality of dies of the wafer to not contact the plurality of probes of the probe card.

13. The method according to claim 11, characterized in that When the chuck is in the second expected position, the wafer contacts the plurality of probes of the probe card.

14. The method according to claim 11, characterized in that The moving the chuck from the first expected position to the second expected position is substantially moving the chuck upward.

15. The method according to claim 11, characterized in that The step of testing the second portion of the plurality of dies on the wafer is performed after the step of testing the first portion of the plurality of dies on the wafer.

16. The method according to claim 11, characterized in that The step of testing the second portion of the plurality of dies on the wafer and the step of testing the first portion of the plurality of dies on the wafer are performed when the chuck is at the second expected position.

17. The method according to claim 11, characterized in that The step of moving the chuck to the second expected position so that the plurality of dies of the wafer abut against the plurality of probes of the probe card is performed after the step of testing the first portions of the plurality of dies of the wafer.

18. The method according to claim 11, characterized in that The moving the chuck to the second desired position causes the plurality of dies of the wafer to abut against the plurality of probes of the probe card to substantially maintain the chuck at the second desired position.

19. The method according to claim 11, characterized in that The step of testing the second portion of the plurality of dies on the wafer is performed after the step of moving the chuck to the second expected position so that the plurality of dies on the wafer abut against the plurality of probes of the probe card.

20. The method according to claim 11, characterized in that Further comprising moving the chuck from the second expected position to the first expected position after testing the second portion of the plurality of dies on the wafer.

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