Chip testing method and chip testing system

Abstract

The present invention relates to the field of chip testing technology, and in particular to a chip testing method and chip testing system. The method comprises the following steps: obtaining a thermal imaging image of a chip in its operating state; performing global color temperature offset optimization on the thermal imaging image of the chip in its operating state and performing spatial heat distribution mining to construct a chip heat distribution map; performing multi-time heat distribution tracking processing on the chip heat distribution map and performing dynamic heat distribution evolution fitting to construct a dynamic heat distribution trend evolution map; obtaining a high-definition image of the chip to be tested; performing chip component visual monitoring on the high-definition image of the chip to be tested, performing heat distribution trend rendering based on the dynamic heat distribution trend evolution map, and constructing a chip component heat distribution trend rendering model. The present invention improves the efficiency and accuracy of chip performance assessment through extreme operating condition testing and analysis.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip testing method and a chip testing system. Background Art

[0002] In the design and application of modern electronic products, chips, as core components, perform crucial functions. With the continuous advancement of technology, chip performance requirements are becoming increasingly stringent, especially in terms of stability and reliability under extreme operating conditions. Extreme operating conditions refer to the chip's operation in harsh environments such as extremely high or low temperatures, high humidity, high voltage, and strong electromagnetic interference. In such environments, the chip's performance is affected by a variety of external factors, such as temperature fluctuations, current fluctuations, and environmental noise. These factors can cause chip malfunctions, performance degradation, and even system failures. Therefore, testing and evaluating chips under extreme operating conditions has become key to ensuring their stable operation in real-world applications.

[0003] Traditional chip testing methods mostly focus on evaluating performance under standard operating conditions, often overlooking the chip's actual performance under extreme operating conditions. Manual testing and simple environmental simulations often fail to fully reflect a chip's capabilities and potential issues under real-world extreme conditions. Therefore, to meet the chip performance and reliability requirements of high-end electronic products, particularly in aerospace, automotive electronics, and industrial control, a testing method that can simulate and accurately evaluate chip performance under extreme operating conditions is urgently needed. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention proposes a chip testing method and a chip testing system to solve at least one of the above technical problems.

[0005] To achieve the above object, the present invention provides a chip testing method, comprising the following steps:

[0006] Step S1: Acquire a thermal imaging image of the chip working state; perform global color temperature offset optimization on the thermal imaging image of the chip working state, and perform spatial heat distribution mining to construct a chip heat distribution map;

[0007] Step S2: performing multi-time heat distribution tracking processing on the chip heat distribution map, and performing dynamic heat distribution evolution fitting to construct a dynamic heat distribution trend evolution map;

[0008] Step S3: Obtain a high-definition image of the chip to be tested; perform chip component visual monitoring on the high-definition image of the chip to be tested, render the heat distribution trend based on the dynamic heat distribution trend evolution diagram, and construct a chip component heat distribution trend rendering model;

[0009] Step S4: Perform multi-time point thermal situation rolling prediction and extreme operating condition estimation on the heat distribution trend rendering model to generate extreme operating condition parameters of abnormal components;

[0010] Step S5: Based on the extreme operating condition parameters of the abnormal component, the chip component heat distribution trend rendering model is subjected to extreme operating condition test simulation, and then the internal fault diffusion path is deduced to extract multiple internal fault diffusion paths;

[0011] Step S6: Perform extreme operating condition fault diagnosis based on multiple internal fault diffusion paths, and perform comprehensive fault test evaluation to obtain a chip extreme operating condition fault test report.

[0012] The present invention obtains thermal imaging images of the chip's working state and optimizes its color temperature offset to eliminate environmental influences, improve image accuracy, and make thermal imaging images more consistent with actual conditions. At the same time, spatial heat distribution mining can reveal the temperature changes of the chip in different areas, help analyze the heat dissipation characteristics of different parts, accurately identify existing hot spots, and obtain the heat change trend of the chip in different working states by tracking the heat distribution at multiple times. This trend evolution fitting can effectively predict the changes in the chip's heat distribution at different time points, and provide accurate data support for subsequent dynamic thermal analysis and fault warning. Through high-definition images, visual monitoring of chip components is carried out, and the appearance and internal structure of chip components are comprehensively analyzed to assist in heat distribution trend rendering. This process, combined with the dynamic heat distribution trend evolution diagram, makes the heat distribution rendering more accurate and intuitive, providing data basis for thermal management optimization, and helping designers to better identify overheating problems. Rolling predictions at multiple time points and calculations of extreme operating conditions can evaluate the thermal changes of chips under different working conditions, especially their performance under high temperature and extreme conditions, discover the performance bottlenecks of chips in extreme environments, provide a scientific basis for testing extreme working conditions, and identify potential faults and risks in advance. Extreme working condition test simulations help test the heat resistance and reliability of chips under extreme conditions. Combined with the fault diffusion path deduction, the heat propagation process of each chip component when encountering a fault is clarified, and the path of the fault extending from the initial location to other areas is revealed. The source of the fault is effectively located, and the thermal management design is optimized to reduce future failure risks. Through comprehensive fault test evaluation, comprehensive fault diagnosis is performed based on multiple fault diffusion paths, the working status of the chip is comprehensively evaluated under extreme working conditions, the impact of different fault modes on the system is predicted, and a detailed fault diagnosis report is formed through simulation testing, which provides strong support for chip performance improvement, thermal management optimization and fault prevention.

[0013] Preferably, step S1 includes the following steps:

[0014] Step S11: continuously acquiring thermal imaging images of the chip's working status using an infrared thermal imaging camera;

[0015] Step S12: performing global color temperature shift optimization on the thermal imaging image of the chip working state, thereby constructing a global color temperature optimized thermal imaging image;

[0016] Step S13: performing multi-hotspot visual recognition on the global color temperature optimized thermal imaging image, marking multiple temperature hotspots in the image;

[0017] Step S14: performing region division based on multiple temperature hot spots in the image to generate multiple temperature region images;

[0018] Step S15: performing spatial heat distribution mining on multiple temperature region images to construct a chip heat distribution map.

[0019] The present invention continuously obtains thermal imaging images of the chip in the working state and captures the temperature changes of the chip under different working conditions in real time. Infrared thermal imaging technology can intuitively display the temperature distribution of various parts of the chip, providing high-precision data for subsequent thermal analysis, helping engineers to monitor the thermal performance of the chip in real time and promptly discover potential thermal anomalies. Global color temperature offset optimization can effectively reduce errors or noise in thermal imaging images, so that the image more accurately reflects the actual temperature distribution of the chip. By eliminating the influence of environmental factors (such as background temperature changes) on the image, the reliability of the thermal imaging image is improved, and more accurate thermal data is provided for subsequent analysis, thereby ensuring the effectiveness of thermal distribution maps and fault analysis. Multi-hotspot visual recognition can effectively identify multiple temperature hotspot areas in thermal imaging images. These hotspots are often key locations where the chip is overheated or has potential faults. By marking temperature hotspots, analysts can be helped to locate Overheating areas in the chip provide important clues for further thermal management optimization and fault prediction, and identify risk areas that may lead to chip performance degradation or failure in advance. By dividing the temperature hot spots into regions, the thermal imaging image is refined into multiple temperature region images, which facilitates more detailed thermal analysis. Regional division can not only help engineers understand the local thermal conditions of the chip, but also provide basic data for further analysis of the heat distribution and heat dissipation performance of each region. By mining the spatial heat distribution of multiple temperature region images, the detailed heat distribution of each region of the chip is obtained, and then a comprehensive chip heat distribution map is constructed. The heat distribution map can show the temperature differences in different parts of the chip, revealing the heat dissipation of the chip, the heat load distribution and the hot spots. By analyzing these data, we can deeply understand the thermal behavior of the chip under working conditions, identify high-temperature areas and potential failure points, and optimize the thermal management design and performance of the chip.

[0020] Preferably, the specific steps of step S12 are:

[0021] Performing thermocouple noise recognition on the thermal imaging image of the chip in working state, and extracting the noise from the thermal imaging image;

[0022] Adaptively filter and reduce noise points in thermal imaging images to obtain noise-reduced and optimized thermal imaging images;

[0023] Performing camera calibration calculation on the infrared thermal imaging camera to obtain internal parameters and external parameters;

[0024] Performing geometric distortion perspective transformation on the noise reduction optimized thermal imaging image according to internal parameters and external parameters, thereby generating a distortion-corrected thermal imaging image;

[0025] Perform raw pixel offset analysis on the distortion-corrected thermal imaging image to identify each raw pixel offset value;

[0026] Perform bilinear interpolation reconstruction based on each original pixel offset value to obtain a pixel offset reconstructed thermal imaging image;

[0027] Calculate ambient lighting parameters based on infrared thermal imaging camera;

[0028] Performing an ambient light color temperature characteristic analysis on the ambient light parameters to obtain ambient light color temperature characteristic data;

[0029] The global color temperature shift of the pixel-shifted reconstructed thermal imaging image is optimized based on the ambient light color temperature characteristic data, thereby constructing a global color temperature optimized thermal imaging image.

[0030] The present invention uses the fact that infrared thermal imaging images are subject to interference from noise points during the actual acquisition process. These noise points come from thermocouple errors or environmental interference. By identifying and extracting these noise points, unnecessary interference in the image is effectively reduced, providing higher quality raw data for subsequent image optimization and analysis. Adaptive filtering noise reduction is a common method for removing noise points in images. By adjusting the parameters of the filter, the noise points can be automatically filtered out according to their characteristics, obtaining a clearer thermal imaging image, retaining important thermal information in the image and removing unnecessary interference, thereby improving the accuracy of thermal analysis. Camera calibration calculation is the basis for ensuring the geometric accuracy of the image, and the internal parameters of the camera (such as focal length, principal point, distortion coefficient) and external parameters (such as Camera position, orientation, etc.) provide an accurate reference for subsequent geometric transformations. Accurate camera calibration can effectively eliminate image distortion problems caused by camera position changes or lens distortion, providing a reliable basis for subsequent image correction and processing. Geometric distortion perspective transformation corrects image distortion caused by camera lens or shooting angle. By applying the internal and external parameters of the camera, accurate geometric distortion correction can be performed on thermal images to eliminate deformation in the image, making the thermal image more consistent with the actual physical scene. Through original pixel offset analysis, an in-depth understanding of the offset of each pixel in the image is obtained, which is crucial for accurate pixel reconstruction. By identifying the offset value of each pixel, a better understanding of subtle changes in the image can be achieved. Bilinear interpolation is a commonly used image reconstruction method that integrates the offset information of the original pixel value into the new image to obtain a smoother and distortion-free thermal imaging image, which helps to eliminate the image quality degradation caused by pixel offset, making the final image more accurate and reducing the impact of errors on subsequent analysis. The calculation of ambient light parameters helps to understand the impact of ambient light on thermal imaging images during shooting. During the thermal imaging process, factors such as ambient light intensity and color will interfere with the authenticity of the thermal imaging image. By accurately calculating these ambient light parameters, a more accurate basis is provided for subsequent color temperature optimization, further improving the authenticity of the image. And reliability, ambient light color temperature feature analysis helps identify and quantify the color temperature features of ambient light under different conditions, which is crucial for color temperature optimization. By analyzing the color temperature of ambient light, its impact on thermal imaging images can be accurately evaluated, thereby providing effective data support for subsequent image color temperature optimization, ensuring that the temperature distribution in the image is more realistic. Global color temperature offset optimization adjusts the overall color temperature of the image to eliminate the influence of ambient light and equipment factors, thereby making the temperature distribution in the thermal imaging image more accurate. Through optimization based on ambient light color temperature feature data, the interference of external light on the image can be eliminated, making the final image more consistent with the actual thermal distribution, thereby providing more accurate data support for the extreme working condition test analysis of the chip.

[0031] Preferably, the specific steps of step S2 are:

[0032] Step S21: performing multi-time heat distribution tracking processing on the chip heat distribution map to generate heat distribution maps of multiple time periods;

[0033] Step S22: performing dynamic heat distribution trend analysis on the heat distribution graphs of multiple time periods, thereby generating dynamic heat distribution trend features;

[0034] Step S23: performing inter-regional heat gradient identification on the heat distribution graphs of multiple time periods to generate regional heat distribution gradient data;

[0035] Step S24: performing heat propagation law evolution on the regional heat distribution gradient data, thereby generating a chip heat propagation evolution law;

[0036] Step S25: performing dynamic heat distribution evolution fitting on the dynamic heat distribution trend characteristics according to the chip heat propagation evolution law, and constructing a dynamic heat distribution trend evolution graph.

[0037] By generating thermal distribution maps for multiple time periods, the present invention comprehensively tracks the thermal state of a chip at different points in time, capturing temperature changes throughout the chip's operating cycle and avoiding dynamic changes that cannot be captured by single-moment images. Chips experience temporal temperature fluctuations in actual operation. Multi-moment tracking provides more accurate thermal distribution information, helping to understand the chip's thermal behavior under different operating conditions. Dynamic analysis of thermal distribution maps for different time periods can extract the chip's thermal trend characteristics during operation. These trend characteristics reflect the chip's heat accumulation and dispersion patterns under different operating conditions, helping to identify areas of abnormal temperature rise or thermal unevenness. The generation of dynamic trend characteristics provides forward-looking information on the chip's thermal behavior during long-term operation, providing valuable insights for fault diagnosis and design optimization. By identifying thermal gradients between different regions, the heat transfer status of each chip region can be clarified, identifying hotspots with concentrated heat and areas with poor cooling performance. This helps identify uneven heat distribution on the chip surface or within the chip. Identifying thermal gradients helps accurately locate areas of overheating and thermal damage, particularly in complex chips, and can help quickly identify potential fault areas. Regional heat gradient data provides a direct reference for cooling system design, optimizing chip heat dissipation and thermal management solutions and improving overall chip thermal efficiency. By analyzing the evolution of heat propagation patterns, a mathematical model can be established for how heat propagates from one region within the chip to another. This model helps predict heat diffusion within the chip under varying workloads, thereby better understanding the chip's thermal behavior. The evolved heat propagation patterns clearly depict the paths and speeds of heat diffusion from hot spots to other regions, further helping designers identify heat propagation paths that may lead to chip overheating. By combining the heat propagation evolution patterns with dynamic heat distribution trend features, the evolution of heat within the chip can be fitted, resulting in a more accurate heat distribution evolution map. This fitting can depict the dynamic thermal trends of the chip under varying workloads and predict thermal stress areas in advance. The dynamic heat distribution trend evolution map provides an accurate prediction of the chip's actual thermal behavior, enabling engineers to optimize thermal management during the design phase to avoid overheating or insufficient heat dissipation during operation. This image can provide early warning of overheating or temperature unevenness under long-term or extreme operating conditions, providing a reliable basis for fault prevention and maintenance.

[0038] Preferably, the specific steps of step S3 are:

[0039] Step S31: Acquire a high-definition image of the chip to be tested;

[0040] Step S32: Perform chip component visual monitoring on the high-definition image of the chip to be tested, and mark each chip component point;

[0041] Step S33: accurately positioning the spatial position of each chip component point to generate the spatial position coordinates of each component point;

[0042] Step S34: performing chip component point layout analysis based on the spatial position coordinates of each component point, thereby generating chip component point layout features;

[0043] Step S35: performing three-dimensional component topology modeling on the chip component point layout features to construct a chip three-dimensional component topology model;

[0044] Step S36: Rendering the heat distribution trend of the chip three-dimensional component topology model based on the dynamic heat distribution trend evolution diagram to construct a chip component heat distribution trend rendering model.

[0045] The present invention obtains detailed appearance information of the chip to be tested through high-definition images, captures tiny details on the chip surface, including the physical position, size and shape of each component, and provides high-quality basic data for subsequent analysis. The high-definition image can fully display all parts of the chip to ensure that no potential heat accumulation area or structural problem is missed. By visually monitoring the high-definition image, the position and structure of each chip component can be marked, ensuring that the heat distribution, position change and other information of each component are accurately identified and tracked in the subsequent analysis. In the process of marking the chip component points, human errors can be reduced, ensuring that the heat analysis of each component is based on the real position, and improving the accuracy of the subsequent heat distribution analysis. By accurately locating the spatial coordinates of each component point, we can better understand the distribution relationship of each component of the chip in three-dimensional space, and provide accurate spatial reference for subsequent heat distribution analysis, heat transfer model, etc. The spatial position coordinates of the component provide key data support for building a three-dimensional model and conducting three-dimensional heat distribution analysis, so that the heat distribution analysis is not limited to the two-dimensional plane, but can cover the three-dimensional structure of the chip. By performing layout analysis on the spatial position of each component point, we can reveal the arrangement rules of each component inside the chip, the distance between each other, the heat transfer path and other information. The extraction of layout features helps to understand the heat conduction and heat dissipation capabilities of the chip during operation. This step can identify the chip. The bottleneck areas in the component layout that affect heat transfer or heat dissipation, such as overly dense component arrangement, provide a basis for subsequent optimization design. According to the chip component layout characteristics, data support is provided for the chip's heat dissipation design, cooling system design, or component arrangement optimization, thereby improving the chip's overall thermal management capabilities. Through 3D topological modeling, the spatial position, form, and mutual relationship of each chip component are visualized to create a three-dimensional chip model, which helps to more intuitively understand the chip structure, especially in terms of heat conduction, heat dissipation path, etc. The 3D component topology model can provide more dimensional data, making the heat propagation analysis more comprehensive and detailed. The thermal interaction between chip components can be visualized through 3D topology modeling. The model can perform more accurate simulation and prediction. By rendering the heat distribution trend of the three-dimensional topology model based on the dynamic heat distribution trend evolution diagram, the heat evolution process of the chip in different time periods can be visualized, and the heat propagation path and temperature distribution inside the chip can be intuitively displayed. Through heat distribution trend rendering, the thermal state of the chip under different working conditions can be predicted, especially the heat accumulation and diffusion under high load and extreme working conditions, thereby providing a scientific basis for the thermal design and fault prevention of the chip. Through the visualization effect of the rendering model, engineers and designers can more intuitively see how heat propagates in the three-dimensional structure, and then optimize the heat dissipation solution and thermal management strategy to reduce the risk of overheating and failure.

[0046] Preferably, the specific steps of step S4 are:

[0047] Step S41: performing a rolling prediction of the heat situation at multiple time points on the heat distribution trend rendering model to generate heat situation prediction data of chip components at multiple time points;

[0048] Step S42: identifying abnormal component temperatures based on the chip component thermal situation prediction data at multiple time points, and marking abnormal chip component points;

[0049] Step S43: Obtain the chip's historical operation log, perform normalized operation analysis on the abnormal chip component points based on the chip's historical operation log, and extract normalized operation parameters of the abnormal component;

[0050] Step S44: performing extreme operating condition calculation based on the normalized operating parameters of the abnormal component to generate extreme operating condition parameters of the abnormal component.

[0051] By performing a rolling prediction of heat distribution trends, the present invention can comprehensively understand the thermal variations of chip components at different time points. This provides a reliable basis for subsequent temperature management and component load analysis. Thermal data at different time points can help analyze the chip's temperature variation trends during long-term operation, proactively predicting thermal anomalies under different operating conditions, and thus preventing problems such as overheating from impacting chip performance and lifespan. By predicting thermal conditions at multiple time points, thermal stress accumulation issues can be identified early during chip operation, allowing optimization measures to be taken in advance to ensure system safety and stability. By marking abnormal chip component points, the fault location can be accurately diagnosed and the specific source of the temperature anomaly can be quickly located, reducing the time and cost of problem location. By marking abnormal component points, the system provides accurate targets for subsequent fault warnings and preventive maintenance, improving chip component reliability and reducing the risk of unplanned downtime. By acquiring historical chip operation logs and combining them with regular operation analysis of abnormal components, a more comprehensive understanding of the chip's performance under normal operating conditions can be achieved, providing data support for subsequent anomaly analysis. Normalized operating analysis helps analyze the chip's actual performance under various typical operating conditions, eliminating non-abnormal temperature fluctuations and more accurately assessing temperature changes caused by faults. By analyzing historical operating data, the chip's normal operating parameters are extracted and used as baseline data. This provides a reliable reference for subsequent extreme operating condition extrapolation, ensuring the chip operates within reasonable limits. Extreme operating condition extrapolation based on normalized operating parameters predicts the chip's performance under extreme operating conditions, helping chip designers identify potential design flaws and ensure chip stability under various extreme operating conditions. Based on the extrapolated extreme operating condition parameters, the chip can be further optimized and debugged to improve its endurance, load capacity, and overheating resistance, thereby enhancing its adaptability and lifespan. Extreme operating condition extrapolation helps identify chip vulnerabilities in extreme environments in advance, allowing measures to be taken to prevent chip failures under extreme conditions, ensuring system operation and reducing system crashes caused by overheating and overload.

[0052] Preferably, the specific steps of step S5 are:

[0053] Step S51: performing an extreme operating condition test simulation on the chip component heat distribution trend rendering model based on the extreme operating condition parameters of the abnormal component, and collecting extreme operating condition test simulation response data;

[0054] Step S52: performing deep mining of component operating status on the extreme operating condition test simulation response data to generate extreme operating condition component operating status features;

[0055] Step S53: Predicting chip failure probability trends based on extreme operating condition component operating status characteristics, thereby constructing component failure probability heat maps for different regions;

[0056] Step S54: performing fault internal diffusion path deduction on component failure probability heat maps in different areas, and extracting multiple fault internal diffusion paths.

[0057] This invention simulates extreme operating conditions using a chip component heat distribution trend rendering model based on the extreme operating parameters of abnormal components. This model can simulate the actual heat distribution and performance response of the chip under extreme operating conditions. This helps to proactively identify hotspots and overheating risks that may arise during actual operation. By comparing simulated data with actual test results, the accuracy and reliability of the heat distribution trend rendering model can be verified, providing a more reliable model for subsequent chip failure prediction. Deep mining of the simulated response data under extreme operating conditions enables analysis of the chip component's operating state under extreme conditions from multiple dimensions (such as temperature, load, and power). This provides a precise basis for understanding the specific performance of the chip under extreme conditions. Deep mining reveals potential weaknesses in chip components under high load and high temperature conditions, helping engineers identify the factors that most impact chip performance, such as excessive heat accumulation in certain areas, leading to frequency throttling and system instability. By mining the state characteristics under extreme conditions, detailed parameter input is provided for subsequent failure prediction, helping designers optimize product designs and enhance chip stability in extreme environments. By predicting chip failure probability trends based on the operating characteristics of components under extreme conditions, we can predict the probability of chip failure under extreme conditions and generate a component failure probability heat map. This heat map visually displays the failure risk in different areas, providing engineers with valuable reference information. The failure probability heat map helps quickly identify the chip areas or components most prone to failure. This helps preemptively locate risk areas and implement corrective measures to avoid catastrophic failures. The heat map allows engineering teams to clearly identify areas with high failure risk, enabling them to conduct more targeted monitoring, testing, and optimization, effectively allocate testing resources, and improve testing efficiency. By analyzing the component failure probability heat maps for different areas, we can predict the propagation path of failures within the chip system. For example, a failure in one area could trigger failures in adjacent areas or even a complete system crash. Extracting the fault propagation path helps prevent the full spread of the failure. Understanding the fault propagation path helps develop more effective protective measures, such as strengthening the thermal design of high-risk areas, adding redundant backups, and establishing fault alarms, to minimize irreversible system crashes. After deducing the spread path of the fault, it helps enterprises formulate emergency response plans in advance, such as phased repair, isolation of fault areas, and performance evaluation before and after repair, thereby reducing system downtime and fault repair costs.

[0058] Preferably, the specific steps of step S53 are:

[0059] Predict the chip failure probability trend based on the operating status characteristics of the extreme working condition components to obtain chip failure probability trend prediction data;

[0060] Perform fault probability time series fitting on chip failure probability trend prediction data to construct a chip failure probability time series curve;

[0061] Identify the faulty component area based on the operating status characteristics of the extreme working condition components and mark the faulty component area;

[0062] The failure probability trend of the faulty component area is mapped according to the chip failure probability timing curve, thereby constructing a component failure probability heat map in different areas.

[0063] The present invention predicts chip failure probability trends based on component operating status characteristics under extreme working conditions, accurately quantifies the probability of chip failure under different working conditions, and provides a scientific basis for subsequent fault prevention by dynamically capturing potential risks during chip operation. Failure probability trend prediction can analyze chip failure trends in different time periods based on operating data, providing early warning of system crashes or performance degradation, which helps to monitor chip status in real time and take timely repair or replacement measures, thereby reducing system downtime. The curve after time series fitting can reveal potential fluctuations and peaks in failure risks, thereby helping engineers analyze the failure probability of chips at specific times or under specific working conditions, facilitating the timely implementation of necessary countermeasures. By analyzing key time nodes in the timing curve, the test team determines the test phases to focus on, such as strengthening monitoring during high-risk periods or focusing on testing specific areas to improve overall test efficiency and accuracy. By identifying faulty component areas based on the operating status characteristics of components under extreme working conditions, areas or components within the chip with failure risks are accurately marked. This process helps to detect and effectively prevent fault problems early, identify fault areas in advance, and provide maintenance teams with accurate targets. By identifying the faulty component area, the team can analyze the cause of the failure in a targeted manner, optimize the design or function of the area, and improve the chip's reliability under extreme operating conditions. By mapping the failure probability trend of the faulty component area based on the chip's failure probability time series curve, the generated failure probability heat map intuitively displays the failure risk of different areas, helping the team quickly locate high-risk areas. The heat map not only provides information on the spatial distribution of failure probability, but also helps the team identify "failure hotspots" in the chip. These areas are high-frequency areas of chip failure and serve as the focus of subsequent design optimization. The failure probability heat map enables the engineering team to make more data-driven decisions during the design, manufacturing, and maintenance processes. For example, during the chip design phase, the team can strengthen thermal management and heat dissipation design in high-risk areas, or conduct more quality control testing in high-risk areas during production. The heat map provides continuous support for subsequent chip optimization and risk management. As new data is collected and analyzed, the heat map is dynamically updated, helping the team to keep abreast of the latest failure risk information of the chip under extreme operating conditions and formulate long-term maintenance and optimization strategies.

[0064] Preferably, the specific steps of step S6 are:

[0065] Step S61: performing diffusion path intersection component point analysis on multiple fault internal diffusion paths to extract key fault diffusion component points;

[0066] Step S62: Perform extreme operating condition fault diagnosis on the key component points of the fault diffusion to obtain extreme operating condition fault diagnosis data of the component;

[0067] Step S63: performing a quantitative analysis of the fault repairability of the component extreme operating condition fault diagnosis data, thereby obtaining a quantitative value of the repairability of key component points;

[0068] Step S64: Perform comprehensive fault test evaluation based on the quantitative values ​​of the repairability of key component points, thereby obtaining a chip extreme working condition fault test report.

[0069] The present invention can discover the key component points where multiple fault paths intersect by performing cross-component point analysis on multiple internal fault diffusion paths. These component points are usually bottlenecks or key nodes for fault diffusion and play an important role in multiple fault paths. Identifying these key components helps to prioritize the resolution of high-risk components. By cross-analyzing different fault paths, the source and development process of fault diffusion can be accurately tracked, which provides a scientific basis for subsequent fault location and diagnosis, helps to identify which areas or components are most susceptible to faults, and helps the design team improve these areas. By comprehensively analyzing multiple fault paths, the accuracy of fault diffusion prediction is improved, especially in complex systems. This helps to accurately predict the chain reaction that occurs in the system under extreme working conditions, thereby Reduce the risk of system crashes, perform extreme operating condition fault diagnosis on key component points where faults spread, simulate the performance of chips under extreme loads, temperatures or other extreme environmental conditions, and accurately diagnose which components will fail under these conditions. This provides important feedback for chip design optimization. Extreme operating condition fault diagnosis helps engineers not only identify faulty components, but also further locate the specific cause of the fault, such as overheating, insufficient power, electrical failure, etc., thereby avoiding unsolvable problems. The diagnostic results provide a clear direction for subsequent repair solutions, such as heat dissipation design optimization for overheating problems, or circuit improvements for electrical failures, thereby improving the reliability and durability of the chip under extreme working conditions, and repairing the extreme operating condition fault diagnosis data of the components. Quantitative analysis of repairability quantitatively evaluates the difficulty, cost and time of repairing each faulty component. This helps the engineering team determine the priority of fault repair and decide which faults need to be resolved as soon as possible and which ones need to be postponed. By quantifying the repairability of key component points, a more scientific and accurate basis is provided for repair work, and maintenance processes and plans are optimized to avoid excessive repairs or missed repairs. Quantitative analysis can also help the design team selectively adjust the design to reduce the frequency of future failures. Quantitative analysis of repairability can effectively evaluate the resource requirements of repair work, help control maintenance costs, and improve resource utilization efficiency. For large-scale production chips, quantitative analysis of repairability can significantly reduce maintenance and repair costs and improve overall production efficiency. Based on the quantitative value of the repairability of key component points, Comprehensive fault test evaluation comprehensively evaluates the fault performance and repair strategy of the entire chip under extreme working conditions. This not only covers single fault points, but also comprehensively considers the interaction and overall impact of multiple fault paths, providing a comprehensive perspective for chip reliability evaluation. Through comprehensive fault test evaluation, the final generated fault test report can record in detail the chip's performance, fault analysis, repair plan, etc. under extreme working conditions, providing detailed decision-making basis for the engineering team. The report content helps the design and manufacturing team to identify which areas or components have potential performance problems under extreme conditions. The test report can reveal the weak links in the design and production process, provide guidance for subsequent design optimization and quality control, and continuously optimize the quality of the chip through regular comprehensive evaluation.Improve production efficiency and reduce the cost of subsequent maintenance and testing.

[0070] In this specification, a chip testing system is provided, which is used to perform the chip testing method described above, including:

[0071] An image enhancement module is used to obtain a thermal imaging image of the chip's working state; perform global color temperature offset optimization on the thermal imaging image of the chip's working state, and perform spatial heat distribution mining to construct a chip heat distribution map;

[0072] The heat distribution trend module is used to track the heat distribution of the chip at multiple times, perform dynamic heat distribution evolution fitting, and construct a dynamic heat distribution trend evolution diagram;

[0073] The chip component layout module is used to obtain high-definition images of the chip under test; perform chip component visual monitoring on the high-definition images of the chip under test, render the heat distribution trend based on the dynamic heat distribution trend evolution diagram, and build a chip component heat distribution trend rendering model;

[0074] The heat situation prediction module is used to perform multi-time point heat situation rolling prediction and extreme operating condition calculation on the heat distribution trend rendering model to generate extreme operating condition parameters of abnormal components;

[0075] The extreme operating condition test module is used to simulate the extreme operating condition test of the chip component heat distribution trend rendering model based on the extreme operating condition parameters of the abnormal component, and then deduce the internal fault diffusion path to extract multiple internal fault diffusion paths;

[0076] The fault diagnosis module is used to diagnose extreme working condition faults based on multiple internal fault diffusion paths, and perform comprehensive fault test evaluation to obtain a chip extreme working condition fault test report.

[0077] The present invention monitors the working status of the chip in real time by acquiring thermal imaging images, and obtains the heat distribution of each component of the chip, which is very important for discovering potential overheating problems. The global color temperature offset optimization eliminates noise and color difference in the thermal imaging image, making the visualization of the heat distribution more accurate, and improving the accuracy of subsequent analysis. Through heat distribution mining, it is possible to deeply analyze the spatial distribution of the chip surface temperature and reveal the heat accumulation in various areas of the chip, which is very important for identifying high-temperature hot spots and areas with insufficient heat dissipation, and helps to optimize the heat dissipation design of the chip. Through multi-time heat distribution tracking processing, the heat change trend of the chip under different working conditions is observed, which is very important for predicting the performance of the chip after long-term operation, and for dealing with temperature fluctuations and Load changes are very critical. Dynamic heat distribution evolution fitting can generate accurate heat evolution curves and provide engineers with long-term heat evolution trends of chips under extreme working conditions. This helps to analyze the impact of heat accumulation on chip performance and identify potential overheating risks. The heat distribution trend graph can predict the temperature change trajectory of the chip under different working conditions and provide decision support for subsequent fault diagnosis and design optimization. By obtaining the component layout of the chip through high-definition images and performing visual monitoring, the various components inside the chip and their heat distribution can be accurately identified. In this way, the design team can identify which components are susceptible to overheating and which are potential failure points. Combined with the dynamic heat distribution trend evolution graph, heat distribution trend rendering is performed to provide information for each chip component. It provides more accurate temperature change trajectories, which provides specific data support for the heat dissipation design of chip components and the optimization of temperature control systems. Based on the heat distribution rendering model, it can identify which components have performance bottlenecks such as overheating and frequency reduction under specific working conditions, helping designers optimize component layout and heat dissipation solutions. Through the rolling prediction of the heat distribution trend rendering model, it dynamically monitors the heat changes of the chip at different time points, evaluates the heat performance of the chip under different load conditions in real time, effectively predicts the performance of the chip under extreme working conditions, and discovers overheating problems in advance. Through extreme working condition calculations, it simulates the operating status of the chip under the most extreme conditions, predicts the high temperature and failure risks of abnormal components, provides data support for the fault warning system, and reduces the occurrence of failures in actual work. The generation of extreme operating parameters can help the design team conduct risk assessments during the product development phase, avoid problems such as overheating and uneven heat dissipation in the design, and optimize the thermal management design of the chip. Through test simulations based on extreme operating parameters, we can gain an in-depth understanding of the chip's performance under extreme conditions, especially its performance and stability under high load and high temperature conditions. This helps to identify fault sources and weak links in advance. By deducing the internal diffusion path of the fault, we can simulate the diffusion process after the fault occurs and identify which components will be affected. This helps to determine the fault propagation mode within the chip and provide support for fault warning and repair. By extracting multiple fault diffusion paths, we can provide a scientific basis for fault prevention measures and help the design team optimize the chip structure and heat dissipation design.Preventing faults from spreading to other critical components. By analyzing multiple fault diffusion paths, we can accurately diagnose the type, cause, and impact of chip failures under extreme operating conditions, ensuring comprehensive identification of chip failures and proposing targeted solutions. Comprehensive fault testing and evaluation can comprehensively assess chip failure performance under extreme operating conditions and generate detailed test reports, providing data support for subsequent design optimization, production quality control, and maintenance strategies. Extreme condition fault test reports provide important decision-making basis for chip design and production teams, helping to improve chip design, optimize the manufacturing process, and carry out targeted fault repairs and performance improvements. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Figure 1 A schematic flow chart of the steps of a chip testing method of the present invention;

[0079] Figure 2 Detailed implementation flow chart of step S1;

[0080] Figure 3 Detailed implementation flow chart of step S2;

[0081] Figure 4 Schematic diagram of the detailed implementation steps of step S3. DETAILED DESCRIPTION

[0082] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0083] This application provides a chip testing method and chip testing system. The execution entities of the chip testing method and chip testing system include, but are not limited to, the following: mechanical equipment, data processing platforms, cloud server nodes, network upload devices, etc., which can be regarded as general computing nodes of this application. The data processing platform includes, but is not limited to, at least one of an audio and image management system, an information management system, and a cloud data management system.

[0084] See also Figures 1 to 4 The present invention provides a chip testing method, which includes the following steps:

[0085] Step S1: Acquire a thermal imaging image of the chip working state; perform global color temperature offset optimization on the thermal imaging image of the chip working state, and perform spatial heat distribution mining to construct a chip heat distribution map;

[0086] Step S2: performing multi-time heat distribution tracking processing on the chip heat distribution map, and performing dynamic heat distribution evolution fitting to construct a dynamic heat distribution trend evolution map;

[0087] Step S3: Obtain a high-definition image of the chip to be tested; perform chip component visual monitoring on the high-definition image of the chip to be tested, render the heat distribution trend based on the dynamic heat distribution trend evolution diagram, and construct a chip component heat distribution trend rendering model;

[0088] Step S4: Perform multi-time point thermal situation rolling prediction and extreme operating condition estimation on the heat distribution trend rendering model to generate extreme operating condition parameters of abnormal components;

[0089] Step S5: Based on the extreme operating condition parameters of the abnormal component, the chip component heat distribution trend rendering model is subjected to extreme operating condition test simulation, and then the internal fault diffusion path is deduced to extract multiple internal fault diffusion paths;

[0090] Step S6: Perform extreme operating condition fault diagnosis based on multiple internal fault diffusion paths, and perform comprehensive fault test evaluation to obtain a chip extreme operating condition fault test report.

[0091] The present invention obtains thermal imaging images of the chip's working state and optimizes its color temperature offset to eliminate environmental influences, improve image accuracy, and make thermal imaging images more consistent with actual conditions. At the same time, spatial heat distribution mining can reveal the temperature changes of the chip in different areas, help analyze the heat dissipation characteristics of different parts, accurately identify existing hot spots, and obtain the heat change trend of the chip in different working states by tracking the heat distribution at multiple times. This trend evolution fitting can effectively predict the changes in the chip's heat distribution at different time points, and provide accurate data support for subsequent dynamic thermal analysis and fault warning. Through high-definition images, visual monitoring of chip components is carried out, and the appearance and internal structure of chip components are comprehensively analyzed to assist in heat distribution trend rendering. This process, combined with the dynamic heat distribution trend evolution diagram, makes the heat distribution rendering more accurate and intuitive, providing data basis for thermal management optimization, and helping designers to better identify overheating problems. Rolling predictions at multiple time points and calculations of extreme operating conditions can evaluate the thermal changes of chips under different working conditions, especially their performance under high temperature and extreme conditions, discover the performance bottlenecks of chips in extreme environments, provide a scientific basis for testing extreme working conditions, and identify potential faults and risks in advance. Extreme working condition test simulations help test the heat resistance and reliability of chips under extreme conditions. Combined with the deduction of fault diffusion paths, the heat propagation process of each chip component when encountering a fault is clarified, and the path of the fault extending from the initial location to other areas is revealed. The source of the fault is effectively located, and the thermal management design is optimized to reduce future failure risks. Through comprehensive fault test evaluation, comprehensive fault diagnosis is performed based on multiple fault diffusion paths, the working status of the chip is comprehensively evaluated under extreme working conditions, the impact of different fault modes on the system is predicted, and a detailed fault diagnosis report is formed through simulation tests, which provides strong support for chip performance improvement, thermal management optimization and fault prevention.

[0092] In the embodiment of the present invention, see Figure 1 , is a schematic flow chart of the steps of a chip testing method of the present invention. In this example, the steps of the chip testing method include:

[0093] Step S1: Acquire a thermal imaging image of the chip working state; perform global color temperature offset optimization on the thermal imaging image of the chip working state, and perform spatial heat distribution mining to construct a chip heat distribution map;

[0094] In this embodiment, a device with a resolution of ≥320x240 pixels and a temperature measurement accuracy of ±2°C is used. It is ensured that the wavelength band of the thermal imager is suitable (usually 8-14μm) to capture the infrared radiation on the chip surface. The test is carried out in a stable environment. The ideal ambient temperature should be maintained at 20-25°C, and the humidity should be controlled between 40% and 60%. The influence of external temperature changes and airflow on the measurement results is avoided. The stability of the test environment is ensured. The chip is placed within the field of view of the thermal imager, the working mode of the chip is started, and its operating voltage (such as 3.3V or 5V) and operating frequency (such as 1GHz) are recorded. The thermal imager captures the heat distribution on the chip surface in real time. The thermal image is generated and the image data of the thermal imager is saved in real time. It is usually transferred to a computer via a USB interface or Wi-Fi for subsequent analysis. The time of each test is recorded (e.g., 10 minutes) for subsequent comparative analysis. The acquired thermal image is imported into the system using image processing software (e.g., MATLAB or Python's OpenCV library). The image is denoised and denoising parameters are set (e.g., a Gaussian blur radius of 2) to eliminate noise caused by environmental interference and improve image quality. The color temperature in the image is analyzed and the average color temperature of the image is calculated, which is usually between 25°C and 100°C. The formula is used. =255 / R×K, where R is the pixel value of the red channel and K is the correction factor. According to the calculated average color temperature value, a target color temperature value (such as 40°C) is set. The original image is subjected to global color temperature shift processing through image processing algorithm, so that the color temperature value of each pixel in the image is close to the target color temperature value. The linear interpolation algorithm is used to achieve color temperature adjustment to ensure a more uniform color temperature distribution. After optimization, the image is analyzed again to ensure that the effect of color temperature shift reaches the expected effect. By comparing the color temperature distribution diagrams before and after optimization, the mean square error (MSE) and other indicators are used for verification to ensure that the optimization effect is significant. The temperature data is extracted from the optimized thermal imaging image using image processing tools. The temperature value of each pixel (such as between 30°C and 90°C) represents the heat distribution information on the chip surface. The extracted temperature The temperature data is organized and analyzed, stored in matrix form for subsequent visualization of heat distribution, and processed using Python's NumPy library. Based on the processed temperature data, a heat distribution map is constructed using data visualization tools (such as MATLAB, Python's Matplotlib library, etc.). The discrete temperature data is converted into a continuous heat distribution map through interpolation algorithms (such as bilinear interpolation or Kriging interpolation). The color mapping range (for example, 30°C-90°C) is set to intuitively display temperature changes. The constructed heat distribution map is analyzed to identify areas of heat concentration and areas with insufficient heat dissipation. Combined with the design and working principle of the chip, optimization suggestions are proposed, such as improving the heat dissipation design or adjusting the power distribution to improve the thermal management efficiency of the chip.

[0095] Step S2: performing multi-time heat distribution tracking processing on the chip heat distribution map, and performing dynamic heat distribution evolution fitting to construct a dynamic heat distribution trend evolution map;

[0096] In this embodiment, when the chip is in working state, thermal imaging images are collected at preset time intervals (for example, every 1 minute), the time tag of each collection is recorded, and the test environment is ensured to be stable for each collection. The experiment duration is set to 10 minutes to 30 minutes to ensure that sufficient heat distribution images are collected. The thermal imaging data obtained at each time point are sorted and stored as a time series data set. Each data contains a timestamp and a corresponding heat distribution matrix (for example, 320x240 pixels). A structured data format (such as CSV or HDF5) is used to facilitate subsequent analysis. The heat distribution image at each time point is processed to extract core data information. By setting a threshold (for example, 35°C), the heat distribution map is converted into a binary image, and areas with higher heat are identified. Image processing technology (such as region growing algorithm) is used to track changes in the heat peak area and record its value. Changes in position and temperature values, compare the heat distribution data at each time point, analyze the heat change trend between different time points, use statistical analysis methods (such as mean, variance) to calculate the changes in each high-temperature area at different time points, identify the evolution trajectory of the heat concentration area, and select an appropriate mathematical model (such as linear regression, nonlinear regression or polynomial fitting) based on the tracked heat distribution data to describe the change of heat distribution over time. The choice of model should be based on the characteristics and change trend of the data. For example, if the heat distribution shows an exponential growth or decay feature, an exponential fitting model can be selected. Use data analysis software (such as Python's SciPy or MATLAB) to fit the tracked heat distribution data, estimate the model parameters through algorithms such as the least squares method, and obtain the functional relationship of the heat distribution over time. For example, the temperature T(t)=a⋅ is fitted. +c, where abc are the parameters to be fitted and t is time. Use visualization methods (such as a scatter plot and an overlay of the fitted curve) to verify the fitting effect and calculate the goodness of fit (such as the R² value) to ensure that the model can better describe the dynamic changes in heat distribution. If the fitting effect is not good, adjust the model or choose a different fitting method to construct a dynamic heat distribution trend evolution graph: Combine the fitting results with the original data to construct a dynamic heat distribution trend evolution graph. The graph can display the heat distribution at different time points and the fitted curve to help more intuitively understand the trend of heat evolution. Use color gradients and legends to identify different temperature ranges for easy analysis.

[0097] Step S3: Obtain a high-definition image of the chip to be tested; perform chip component visual monitoring on the high-definition image of the chip to be tested, render the heat distribution trend based on the dynamic heat distribution trend evolution diagram, and construct a chip component heat distribution trend rendering model;

[0098] In this example, a suitable high-definition camera (e.g., one with a resolution of 12MP or higher) with excellent macro photography capabilities is selected to clearly capture chip details. The camera should be equipped with an appropriate lens (e.g., a macro lens) to ensure close-range imaging. HD images should be acquired in a stable experimental environment. The ideal ambient temperature should be maintained at 20-25°C. Avoid strong direct sunlight and reflections to prevent image quality degradation. Ensure uniform lighting in the acquisition environment, using a soft light for auxiliary illumination. After ensuring the camera is focused and the exposure parameters are set, capture HD images of the chip under test. Each image should cover a different portion of the chip to capture the entire chip and details of its key components (e.g., power supply, heat sink, connectors, etc.). It is recommended to capture at least three images of each component to facilitate subsequent selection of the best image. The captured HD images should be stored in a computer using a lossless format (e.g., TIFF or PNG) for subsequent image processing and analysis. Perform preliminary image processing using image processing software (e.g., MATLAB or OpenCV) to ensure image clarity and remove background noise. Computer vision algorithms (such as edge detection and contour extraction) are used to analyze chip components in high-definition images. First, edge detection algorithms (such as Canny edge detection) are used to identify chip edges and major components. Components are then further processed using morphological operations (such as dilation and erosion) to extract clear outlines. The previously generated dynamic thermal distribution trend evolution graph is used as thermal distribution data input. Interpolation methods (such as bilinear interpolation) are used to map the thermal data to the chip components. Ensure that the thermal data matches the component locations to facilitate subsequent rendering. Data visualization tools (such as Matplotlib, Plotly, or MATLAB) are used to render the thermal distribution trend. By combining thermal values ​​with color mapping, gradient colors (e.g., from blue to red) are used to represent different temperature ranges. A thermal threshold is set to highlight high-temperature areas, enhancing the visual quality of the image. The rendered results are integrated into a complete thermal distribution trend model, creating an interactive interface that allows users to view thermal distribution at different points in time. Use graphical user interface (GUI) tools (such as PyQt or Tkinter) to build a visualization interface, allowing users to select different time points to dynamically display changes in heat distribution.

[0099] Step S4: Perform multi-time point thermal situation rolling prediction and extreme operating condition estimation on the heat distribution trend rendering model to generate extreme operating condition parameters of abnormal components;

[0100] In this embodiment, existing heat distribution data and corresponding time tags are collected to construct a complete data set. In order to perform rolling prediction, a suitable regression model (such as linear regression, support vector regression or long short-term memory network (LSTM)) is selected to predict the heat distribution at future time points. LSTM is particularly suitable for processing time series data. Therefore, it is given priority when there is obvious time dependence. The historical heat distribution data is divided into a training set and a test set. The training set is used to train the selected regression model, and the model parameters are optimized to improve the prediction accuracy. During the training process, the mean square error (MSE) is used as the loss function to evaluate the model's prediction The model is trained to achieve the desired effect and ensure the generalization ability of the model through cross-validation. After model training is completed, the model is used to make rolling predictions of future heat distribution. A rolling window is set (for example, a prediction is made every 1 minute). The heat distribution at the next moment is predicted based on the heat distribution at the previous moment and environmental factors (such as temperature, load, etc.). Through continuous iteration, the heat distribution trend at several future time points is generated. After the heat situation prediction is performed, the abnormal heat distribution that occurs during the prediction process is identified, and a threshold is set (for example, the temperature of a component exceeds 85°C) to determine whether it is abnormal. For the identified abnormal components, the extreme working condition calculation method is applied to consider different working conditions. The load changes, heat dissipation conditions and other factors under certain conditions are used to deduce the extreme operating parameters of the component (such as maximum operating temperature, maximum power consumption, etc.). Monte Carlo simulation and other methods are used to consider the randomness of different variables to evaluate the performance of the component under extreme conditions. The extreme operating parameters that need to be calculated are clearly defined, including maximum operating temperature, maximum current, maximum power consumption, etc. Through literature review or historical data analysis, the specifications and limit values ​​of each component are understood to provide a basis for subsequent calculations. Based on the predicted heat distribution trend, key operating factors are selected for simulation, including load changes, power supply voltage fluctuations, etc. Thermal simulation software (such as ANSYS or COMSOL) is used to simulate the load changes and power supply voltage fluctuations. Multiphysics) is used to simulate heat distribution under different operating conditions and obtain the thermal response of each component under extreme conditions. During the simulation process, temperature data for each component under different operating conditions is collected and statistically analyzed. Data mining techniques (such as cluster analysis) are used to classify the results and identify components that perform poorly under extreme conditions. Finally, the calculated extreme operating parameters of abnormal components are compiled into a report, and corresponding optimization suggestions are provided. For example, for a component with overheating issues, it is recommended to improve the heat dissipation design or reduce the workload. This information is fed back to the engineering team to enable necessary adjustments during the product design and testing phases.

[0101] Step S5: Based on the extreme operating condition parameters of the abnormal component, the chip component heat distribution trend rendering model is subjected to extreme operating condition test simulation, and then the internal fault diffusion path is deduced to extract multiple internal fault diffusion paths;

[0102] In this embodiment, the workload of the chip is set at its limit value (such as 100% CPU usage) to simulate high-intensity working conditions, and the ambient temperature is adjusted to the limit value (such as 40°C) to evaluate the performance in a high-temperature environment. The power supply fluctuation is simulated, and the voltage is set slightly higher than the normal working voltage (such as 5%) to increase the breadth of the stress test. A three-dimensional model of the chip is constructed in the simulation software to ensure that the model details can reflect the actual structure of the chip. According to the set extreme working conditions, the boundary conditions of the model are set, including heat flow, convection and radiation, etc., and the simulation is started to observe the temperature distribution and heat concentration of each component under extreme working conditions, and key data such as the temperature, power consumption and heat conduction path of each component are recorded. Failure modes are defined, such as short circuit, overheating or material aging, etc. For each failure mode, its potential impact on the chip is analyzed, and the heat distribution data and material characteristics are used to analyze the heat distribution data and material characteristics. The fault diffusion path is deduced. Finite element analysis (FEA) methods are used to simulate how heat propagates within the chip after a fault occurs. By observing temperature changes, the area where heat diffuses after the fault occurs is identified. Combined with heat conduction formulas (such as Fourier's law), the heat transfer efficiency between components is calculated, and multiple fault diffusion paths are deduced. The deduced fault diffusion paths are visualized and a fault propagation path diagram is drawn using graphics software (such as MATLAB or Python's Matplotlib). Areas with significant temperature changes are identified. The characteristics of different fault paths are analyzed to identify high-risk components. For example, if the temperature of a component rises rapidly after a fault occurs, the component is considered high-risk. The analysis results are compiled into a report, including failure mode, diffusion path, affected components, and potential risk assessment, to provide a basis for subsequent design optimization and fault prevention.

[0103] Step S6: Perform extreme operating condition fault diagnosis based on multiple internal fault diffusion paths, and perform comprehensive fault test evaluation to obtain a chip extreme operating condition fault test report.

[0104] In this embodiment, the multiple fault diffusion paths extracted previously are classified, and different types of failure modes (such as overheating, short circuit, material aging, etc.) are identified and associated with the corresponding heat distribution data. The impact of each diffusion path on the chip function and performance is evaluated. Thermal simulation software is used to simulate the chip response under different failure modes, and the key impact areas of each path are identified and their importance is determined. For each failure mode, its typical thermal characteristics are defined. For example, an overheating failure causes the temperature of certain components to rise rapidly, while a short circuit failure causes a sharp increase in local temperature. The heat distribution map under extreme working conditions is compared with the heat distribution map under normal working conditions to identify areas with abnormal temperatures. A threshold value (such as a temperature exceeding 85°C) is set to indicate the occurrence of a fault. Machine learning algorithms (such as decision trees and random forests) are applied to classify and diagnose the fault modes. By training the model, the fault mode in the current state is automatically identified based on historical failure data. A comprehensive fault test plan is formulated based on the diagnosis results. Determine the test items, test environment and test methods. The test items should cover all identified failure modes to ensure that there are no omissions. Perform actual tests on the chip under specified extreme environments (such as high temperature, high load, etc.), observe the performance of each component, and record key data such as temperature, power consumption and response time of each component under different working conditions. Analyze the data collected during the test, use statistical tools (such as MATLAB, Python's NumPy and Pandas libraries) for data processing, identify key performance indicators and failure points, describe the purpose, methods and environment settings of the test in detail, ensure that readers understand the background of the test, summarize the results of the fault diagnosis, list the main identified failure modes and their corresponding diffusion paths, attach relevant heat distribution diagrams, and provide the results of the comprehensive fault test, including the performance of each component under extreme conditions and comparison with the normal state. Based on the test results, make targeted rectification suggestions to help the design team optimize the chip design and improve its reliability under extreme working conditions.

[0105] In this embodiment, refer to Figure 2 , is a flowchart of the detailed implementation steps of step S1. In this embodiment, the detailed implementation steps of step S1 include:

[0106] Step S11: continuously acquiring thermal imaging images of the chip's working status using an infrared thermal imaging camera;

[0107] Step S12: performing global color temperature shift optimization on the thermal imaging image of the chip working state, thereby constructing a global color temperature optimized thermal imaging image;

[0108] Step S13: performing multi-hotspot visual recognition on the global color temperature optimized thermal imaging image, marking multiple temperature hotspots in the image;

[0109] Step S14: performing region division based on multiple temperature hot spots in the image to generate multiple temperature region images;

[0110] Step S15: performing spatial heat distribution mining on multiple temperature region images to construct a chip heat distribution map.

[0111] In this embodiment, a suitable infrared thermal imaging camera (such as the FLIR series) is selected to ensure that its resolution and sensitivity can meet the requirements of chip monitoring. The focal length and field of view of the camera are configured so that the thermal radiation of the chip can be clearly captured. The camera is fixed in a suitable position to ensure that its viewing angle can cover the entire chip surface. It is connected to the control system and can transmit image data in real time. The camera acquisition parameters, including frame rate, exposure time, and gain settings, are configured to adapt to different working environments and lighting conditions to ensure that the thermal imaging image of the chip can be accurately captured under different working conditions. The infrared thermal imaging camera is started and the automatic shooting mode is set to continuously obtain thermal imaging images of the chip in the working state, and the timestamp and related parameters of each image are recorded. , transfer the acquired thermal imaging images to the data storage system in real time, use local hard disk or cloud storage to ensure data security and accessibility, design a data management system, classify and store images according to time and image characteristics to facilitate subsequent retrieval and analysis, determine the standard value of color temperature in thermal imaging images, use a standard blackbody radiation source for calibration measurement, so as to facilitate subsequent color temperature offset optimization, by analyzing the color distribution in thermal imaging images, identify the color temperature offset phenomenon in the image, such as color cast caused by ambient light, design an optimization algorithm, calculate the difference between the color temperature value of each pixel in the image and the standard color temperature value, use image processing libraries (such as OpenCV) to implement this process, and use linear or nonlinear transformation methods to transform the image Adjust the color temperature to eliminate the influence of ambient light on the image, ensure that the color temperature distribution of the thermal imaging image is more realistic, remap the optimized color temperature data to the thermal imaging image, generate a global color temperature optimized thermal imaging image, ensure that the temperature information in the image is clearer and easier to understand, and visualize the optimized image so that the operator can intuitively understand the working status of the chip, select a suitable image processing algorithm for hotspot identification, use a threshold-based method, region growing algorithm or machine learning method (such as convolutional neural network) to identify temperature hotspots, determine the identification threshold of temperature hotspots, set a suitable temperature range according to the actual situation, so as to accurately capture the hotspot area, process the optimized thermal imaging image, and use The selected algorithm detects temperature hotspots, marks the hotspot areas and records their temperature values, adds markers (such as rectangular boxes or circles) to the image so that the hotspot areas are easy to identify in subsequent analysis, checks the accuracy of the recognition results to ensure that the marked hotspot areas truly reflect the temperature distribution in the image, and if the recognition effect is not ideal, adjusts the parameters of the recognition algorithm (such as temperature threshold and algorithm type) and performs re-recognition, selects a suitable region partitioning algorithm, such as K-means clustering or DBSCAN algorithm, to identify and partition the temperature areas in the image, determines the parameters required for region partitioning, such as the number of clusters or minimum neighbor distance, and runs the selected region partitioning algorithm based on the marked hotspot areas to identify different temperature areas and group them.The boundaries of each temperature zone should be determined based on the distance between the temperature distribution and hot spots. A separate image should be generated for each divided temperature zone to ensure that the temperature range and distribution of each zone are clearly displayed. A temperature range label should be added to each zone image to facilitate subsequent analysis. For each temperature zone, its average temperature and total heat are calculated. Total heat = ∑ (temperature of each point in the zone × area of ​​the point). The temperature value of each pixel in the image is used in combination with the pixel area to estimate the total heat. The calculated heat distribution data is visualized to generate a heat distribution map. Different colors represent different temperatures and heat distribution conditions, which is easy for users to understand intuitively. The generated heat distribution map is presented in the form of a heat map, with red representing high temperature areas and blue representing low temperature areas. The generated heat distribution map is analyzed to identify overheating areas and potential failure points. Based on the analysis results, a detailed report is generated, including temperature distribution, hot spot analysis, and recommended measures, which are provided to the technical team for subsequent processing.

[0112] In this embodiment, the specific steps of step S12 are:

[0113] Performing thermocouple noise recognition on the thermal imaging image of the chip in working state, and extracting the noise from the thermal imaging image;

[0114] Adaptively filter and reduce noise points in thermal imaging images to obtain noise-reduced and optimized thermal imaging images;

[0115] Performing camera calibration calculation on the infrared thermal imaging camera to obtain internal parameters and external parameters;

[0116] Performing geometric distortion perspective transformation on the noise reduction optimized thermal imaging image according to internal parameters and external parameters, thereby generating a distortion-corrected thermal imaging image;

[0117] Perform raw pixel offset analysis on the distortion-corrected thermal imaging image to identify each raw pixel offset value;

[0118] Perform bilinear interpolation reconstruction based on each original pixel offset value to obtain a pixel offset reconstructed thermal imaging image;

[0119] Calculate ambient lighting parameters based on infrared thermal imaging camera;

[0120] Performing an ambient light color temperature characteristic analysis on the ambient light parameters to obtain ambient light color temperature characteristic data;

[0121] Based on the ambient light color temperature characteristic data, the global color temperature shift of the pixel shift reconstructed thermal imaging image is optimized to construct a global color temperature optimized thermal imaging image.

[0122] In this embodiment, statistical methods (such as mean and standard deviation) are used to identify outliers in thermal images. Typically, noise points appear as temperatures significantly different from those of surrounding pixels. This process is implemented using functions in image processing libraries (such as OpenCV), with a threshold set to determine whether the temperature is abnormal. The thermal image is traversed, marking all pixels identified as noise points. The coordinates and temperature values ​​of these pixels are recorded. The extracted noise information is stored in a list or array for subsequent noise reduction. The identified noise points are visualized to ensure accurate identification. Noise points are marked with different colors on the original image to verify that they meet expectations. An appropriate filter is selected, such as an adaptive median filter or a Gaussian filter. Adaptive filters can adjust based on the statistical characteristics of local pixels, effectively removing noise while preserving edge information. The filter window size is set; a larger window size results in a more pronounced filtering effect, but this may result in a loss of detail. Each pixel in the thermal image is traversed and processed using the adaptive filter. A weighted average of each pixel is calculated and used to replace the original pixel value. During the processing process, it is important to consider the location of noise points to ensure that the filtering process does not affect pixels within the normal temperature range. Compare the denoised image with the original image to verify that the noise has been effectively removed while maintaining overall image quality. Record the filtering parameters and results, and save the processed image for later use. Prepare a calibration surface (such as a checkerboard) and capture multiple images at different angles and positions. Ensure that the images from different viewpoints cover the entire camera field of view. Use the Zhang Zhengyou calibration method or other camera calibration algorithms to extract corner points from the calibration images and calculate the camera's intrinsic parameters (focal length, principal point location, distortion coefficients) and extrinsic parameters (camera position and orientation). Use computer vision tools (such as OpenCV) to automatically process the calibration images and calculate the camera's intrinsic and extrinsic parameter matrix. Record the calculated parameters for geometric correction in subsequent image processing. Based on the distortion coefficients obtained from camera calibration, establish a corresponding distortion model. Typically, radial and tangential distortion models are used. Apply a perspective transformation to the optimized denoised thermal image using the camera's intrinsic and extrinsic parameter matrices. Use OpenCV's cv2.undistort method to perform geometric correction and generate the corrected image. Compare the distortion-corrected image with the original image to ensure that the geometric distortion has been effectively corrected. Check whether the straight lines in the image have been restored to straight lines. Compare the images before and after distortion correction and calculate the offset of each pixel. This is achieved by calculating the difference between the corrected position of each pixel and its original position. Record the offset value of each original pixel in an array for subsequent interpolation and reconstruction. The offset value should include horizontal and vertical displacement information. Check the calculated offset value to ensure that it meets the expectations to avoid inaccurate subsequent processing due to calculation errors. Select the bilinear interpolation algorithm and reconstruct based on the pixel offset values ​​of the original image.This algorithm considers the values ​​of four adjacent pixels and calculates a new pixel value based on the offset. It iterates through each pixel and calculates its new position based on its offset value. It uses bilinear interpolation to calculate the temperature value at the new position and assigns it to the corresponding pixel in the reconstructed image. The reconstructed thermal image is compared with the previous image to ensure a good reconstruction and a reasonable temperature distribution. A sensor or camera is used to obtain ambient lighting information, including light source type, intensity, and color temperature. Measurements are taken using a photometer or color thermometer. The intensity and color temperature of the ambient light are recorded for subsequent analysis. Data is collected multiple times at different time periods and environmental conditions to improve accuracy. This ensures that the collected lighting data is accurate and consistent with the actual environment. Any anomalies require retesting and recording. Statistical analysis methods are used to extract features from the ambient lighting parameters. The mean, standard deviation, and distribution of the color temperature are calculated. Based on the collected lighting data, the color temperature characteristics of the ambient light are analyzed. The changes in ambient color temperature over different time periods are determined and their impact on the thermal image is assessed. The ambient light color temperature characteristic data is saved for reference when performing color temperature correction on the thermal image. Based on the ambient lighting characteristics and the color temperature distribution of the thermal image, the required global color temperature offset is calculated. This is achieved by comparing the image's average color temperature with the ambient color temperature. A color temperature adjustment algorithm is then applied to the reconstructed thermal image to optimize the global color temperature offset. This typically involves adjusting the image's RGB channel values ​​to accurately represent temperature regions. The optimized thermal image is then compared with the original reconstructed image to verify the effectiveness of the color temperature offset optimization. Ensure that the different temperature regions are visually distinct and save the optimized image for future use.

[0123] In this embodiment, refer to Figure 3 , is a flowchart of the detailed implementation steps of step S2. In this embodiment, the detailed implementation steps of step S2 include:

[0124] Step S21: performing multi-time heat distribution tracking processing on the chip heat distribution map to generate heat distribution maps of multiple time periods;

[0125] Step S22: performing dynamic heat distribution trend analysis on the heat distribution graphs of multiple time periods, thereby generating dynamic heat distribution trend features;

[0126] Step S23: performing inter-regional heat gradient identification on the heat distribution graphs of multiple time periods to generate regional heat distribution gradient data;

[0127] Step S24: performing heat propagation law evolution on the regional heat distribution gradient data, thereby generating a chip heat propagation evolution law;

[0128] Step S25: performing dynamic heat distribution evolution fitting on the dynamic heat distribution trend characteristics according to the chip heat propagation evolution law, and constructing a dynamic heat distribution trend evolution graph.

[0129] In this embodiment, data of multiple time periods are extracted from the previously generated thermal distribution map. These time periods should cover the working cycle of the chip, including the startup, stable operation and shutdown stages. The data of each time period is ensured to be complete and accurate. The environmental conditions and chip working status at each time point are recorded. The thermal data of each time period is visualized as a thermal distribution map using image processing software (such as Matplotlib in MATLAB or Python). The images of different time periods should be standardized with the same color scale for easy comparison. The images are ensured to be clear and can accurately reflect the temperature distribution and hot spots. Important temperature areas and hot spots are marked on each thermal distribution map, and the timestamp is recorded. Different colors or graphics are used to mark each time period. Data, all generated heat distribution maps are stored in the database for subsequent access and analysis, heat distribution maps of different time periods are compared, and temperature changes in each area are analyzed by calculating the average temperature change and standard deviation of each area, identifying areas with significant heat changes and recording their change trends (such as rising, falling or stable), using data analysis tools (such as the Pandas library in Python) to extract dynamic heat distribution features, calculate the heat change rate and change amplitude, and record them as trend feature data, and use visualization tools to display dynamic features as trend graphs to facilitate observation of heat change patterns, check the accuracy of the extracted dynamic feature data, and ensure that it can truly reflect the changing trend of heat distribution. If necessary, logarithm The data is further smoothed to improve the reliability of the analysis results, the analysis results are recorded, and data support is provided for subsequent steps. The heat distribution map of each time period is processed, the heat difference between adjacent areas is calculated, and the gradient calculation method (such as the Sobel operator) is used to extract the heat gradient information, identify the areas with significant heat changes, and record their temperature gradients. The calculated regional heat gradient data is organized into a table, recording the temperature value of each area and the heat difference between adjacent areas, ensuring a clear data structure for subsequent analysis. The heat gradient data is visualized as a heat map or vector map to intuitively display the heat distribution gradient between different areas. This will help technicians quickly identify the direction and intensity of heat propagation and determine the direction and intensity of heat distribution according to the regional heat distribution. Distribute gradient data, establish a heat propagation model, use physical models (such as heat conduction equations) or data-based models to describe the laws of heat propagation, set model parameters, such as thermal conductivity and thermal diffusivity, to better simulate the heat propagation process, and analyze the heat distribution in different time periods to study the heat propagation trend in different areas, determine the evolution law of heat in time and space, identify the rate and mode of heat propagation through fitting analysis, record it as evolution law data, summarize the heat propagation law, and generate a report to describe the heat propagation characteristics of the chip, ensure the repeatability of the results, and provide a reference for subsequent research, select a suitable fitting algorithm (such as polynomial fitting or exponential fitting) to model the dynamic heat distribution trend characteristics,The selected algorithm should be able to better capture the nonlinear characteristics of heat changes. The dynamic heat distribution trend characteristic data should be input into the fitting algorithm for parameter estimation and model training to ensure that the fitting results can accurately reflect the data trend. The fitting parameters should be recorded and used to generate a trend evolution graph. The fitting results should be visualized as a trend evolution graph to show how the heat distribution changes over time. This graph should clearly show the evolution trend of the heat distribution, making it easier for technicians to understand and analyze. The fitting results should be verified to ensure that they are consistent with the actual data and the reasons for the deviation should be analyzed.

[0130] In this embodiment, refer to Figure 4 , is a flowchart of the detailed implementation steps of step S3. In this embodiment, the detailed implementation steps of step S3 include:

[0131] Step S31: Acquire a high-definition image of the chip to be tested;

[0132] Step S32: Perform chip component visual monitoring on the high-definition image of the chip to be tested, and mark each chip component point;

[0133] Step S33: accurately positioning the spatial position of each chip component point to generate the spatial position coordinates of each component point;

[0134] Step S34: performing chip component point layout analysis based on the spatial position coordinates of each component point, thereby generating chip component point layout features;

[0135] Step S35: performing three-dimensional component topology modeling on the chip component point layout features to construct a chip three-dimensional component topology model;

[0136] Step S36: Rendering the heat distribution trend of the chip three-dimensional component topology model based on the dynamic heat distribution trend evolution diagram to construct a chip component heat distribution trend rendering model.

[0137] In this embodiment, a high-definition camera is prepared, ensuring that it has sufficient resolution (such as 20MP or above) and an appropriate lens (such as a macro lens) to capture the subtle features of the chip components. The stability of the camera is ensured, and a tripod or fixed bracket is used to avoid blurring during shooting. Shooting is performed under good lighting conditions, avoiding strong shadows and reflections. A uniform LED light source is used to ensure uniform light distribution. The camera settings, including exposure time, ISO value, and white balance, are adjusted to obtain the best image quality. The camera is used to shoot multiple angles and different areas of the chip to be tested to ensure that the clarity and details of each component can be fully captured. After shooting, the image is stored in a high-quality image format (such as TIFF or PNG). Retain more image information, check the acquired images, ensure that each image meets the quality standards, and there is no blur or out of focus. If any problems are found, retake the image, use image processing software (such as OpenCV or MATLAB) to pre-process the high-definition image, including denoising, contrast enhancement, etc., to improve the accuracy of component recognition, visualize the edges of different components in the image, help clarify the outline of each component, select appropriate visual monitoring algorithms, such as template matching-based algorithms, edge detection algorithms (such as Canny edge detection) or machine learning algorithms (such as convolutional neural networks) for component recognition, design the recognition process to ensure that all chip components can be accurately identified, and can handle different lighting and background interference situations, for recognition Mark each component identified, record its position in the image, use different symbols or colors to mark different types of components, store the marked information in the form of coordinates in a data structure to facilitate subsequent spatial positioning and analysis, and perform a visual inspection of the marking results to ensure that all components are correctly identified and marked. If omissions or errors are found, adjust the recognition parameters and re-mark, select a suitable coordinate system, usually use a three-dimensional coordinate system (X, Y, Z) to represent the spatial position of each component, ensure that the definition of the coordinate origin is consistent with the actual physical position of the chip, use image processing techniques such as camera calibration and perspective transformation to convert two-dimensional image coordinates into three-dimensional space coordinates, use known reference points or dimensions for correction, and combine internal parameters (such as Focal length, principal point position) and external parameters (such as camera position), calculate the spatial coordinates of each marked component, record the spatial coordinates of each component in the data table, ensure the systematic and queryable information, each component should contain its identifier and corresponding three-dimensional coordinates, check the accuracy of the spatial coordinates, ensure that the coordinate value of each component is consistent with the actual position, if any deviation is found, recalculate and adjust the coordinates, determine the key parameters of the layout characteristics, such as component spacing, relative position, density and distribution, etc. These characteristics will reflect the design rationality and performance of the chip, use cluster analysis, principal component analysis (PCA) or heat map analysis and other techniques to analyze the spatial layout of component points, identify the layout pattern by calculating the distance and angle between components, according to the spatial coordinate data,Calculate the relative position and layout characteristics of each component, such as the center point position, distribution range, density, etc. of each component, organize the output layout feature data for subsequent use, and display the layout characteristics in a graphical way, such as using scatter plots, heat maps or three-dimensional graphics to facilitate intuitive understanding, generate reports, describe the layout characteristics of chip components and their impact on heat distribution and function, select suitable three-dimensional modeling software (such as Blender, SolidWorks or AutoCAD) for component topology modeling. These tools can process complex three-dimensional data and generate high-quality models. Input the extracted component spatial position coordinates into the modeling software, generate three-dimensional objects according to the type and size of the components, define the connection relationship between components, such as welding points, wires, etc., to ensure that the topological structure of the model reflects the actual chip design, optimize the generated three-dimensional model to ensure that it meets the actual design requirements in shape and size, and make detailed adjustments to ensure the spacing between components. Ensure accurate distances and connections, perform surface smoothing and texture mapping to improve the visual effect of the model, collect previously generated dynamic heat distribution trend data and associate it with the 3D model, ensure that the heat information of each component can be mapped to the model, select appropriate rendering software (such as Maya, Blender or Unity) for visual rendering of heat distribution. These tools can handle complex 3D scenes and generate realistic images. Set heat distribution mapping rules and map heat values ​​to the surface of the 3D model. Use color gradients or heat map styles, with red representing high-temperature areas and blue representing low-temperature areas. Adjust the lighting and reflection effects of the model surface through material settings to enhance the realism of the rendering. Render the heat distribution and generate visual images or animations of dynamic heat distribution trends. Ensure that the rendering effect can clearly show the changes in heat distribution. Export the rendering results to an appropriate format (such as video or image sequence) for easy display and analysis.

[0138] In this embodiment, step S4 includes the following steps:

[0139] Step S41: performing a rolling prediction of the heat situation at multiple time points on the heat distribution trend rendering model to generate heat situation prediction data of chip components at multiple time points;

[0140] Step S42: identifying abnormal component temperatures based on the chip component thermal situation prediction data at multiple time points, and marking abnormal chip component points;

[0141] Step S43: Obtain the chip's historical operation log, perform normalized operation analysis on the abnormal chip component points based on the chip's historical operation log, and extract normalized operation parameters of the abnormal component;

[0142] Step S44: performing extreme operating condition calculation based on the normalized operating parameters of the abnormal component to generate extreme operating condition parameters of the abnormal component.

[0143] In this embodiment, previously generated dynamic heat distribution trend data is collected to ensure that the data includes heat distribution information for multiple time periods. An appropriate prediction model is selected. Common methods include time series analysis (such as ARIMA model), machine learning regression model (such as random forest regression) or deep learning model (such as LSTM network). Feature variables related to the heat situation are extracted, such as ambient temperature, chip workload, historical heat distribution, etc. These features will be used as inputs to the model for prediction. The data is preprocessed, including normalization and missing value filling, to improve the training effect of the model. The selected model is trained using historical heat data, and the model parameters are adjusted to optimize the prediction effect. The performance of the model is evaluated using the cross-validation method to ensure Its generalization ability on unseen data is verified by calculating the prediction error (such as root mean square error or mean absolute error) to verify the accuracy of the model, and making necessary adjustments. The trained model is applied to new input data to generate heat prediction data at multiple time points. These data should include the predicted temperature value of each component and the change in heat distribution. The prediction results are visualized to intuitively show the changing trend of the heat situation and help identify potential heat anomalies. Suitable anomaly detection algorithms are selected, such as statistical methods (such as Z-score) or machine learning methods (such as isolation forest or support vector machine) to identify abnormal temperature values. Reasonable anomaly thresholds are set, which are usually determined by analyzing the distribution of historical data. Heat at multiple time points Analyze the situation prediction data, calculate the temperature value of each component, and compare it with the set threshold, identify the components that exceed the threshold, mark them as abnormal components, and record the identified abnormal components in the database, ensuring that the component ID, abnormal temperature value and predicted time point are included. Use visualization tools (such as heat maps or bar charts) to display the location and temperature distribution of abnormal components for rapid identification and evaluation. Check the accuracy of abnormal identification to ensure that the identified abnormal components are consistent with the actual situation. If errors are found, adjust the detection algorithm and threshold, obtain historical operation logs from the chip control system or monitoring system, ensure that the log data contains sufficient time range and relevant information, such as temperature, power, workload and fault records, etc., and select appropriate Format (such as CSV or JSON) for data storage for subsequent analysis, clean the collected historical operation logs, remove duplicate or irrelevant data, fill in missing values ​​to improve data integrity, convert the data into a structured format to facilitate subsequent analysis and processing, extract the operating parameters of abnormal components under normal working conditions, including normal temperature range, workload, environmental conditions, etc., by analyzing the log data during normal operation, identify the characteristics of abnormal components under normal operation, provide data support for subsequent analysis, record the extracted normal operation parameters in the database, ensure the systematic and queryable information, generate a report, summarize the normal operation characteristics and related parameters of abnormal components, and provide a basis for subsequent steps.Determine the extreme operating conditions for analysis, such as maximum operating temperature, maximum power load, and environmental changes (such as high temperature and high humidity), set the calculation model, usually using a thermodynamic model or material strength analysis model to simulate performance under extreme conditions, select an appropriate mathematical model or simulation tool (such as ANSYS, COMSOL, or MATLAB) to deduce the extreme operating parameters, input the normalized operating parameters of the abnormal component into the model for calculation, evaluate the temperature response and heat distribution under extreme conditions, analyze the simulation results, and generate the operating parameters of the abnormal component under extreme conditions, such as maximum temperature, thermal stress, and failure mode. Compare the calculation results with the normalized operating parameters to evaluate the safety and reliability of the abnormal component under extreme conditions. Record the derived extreme operating parameters in a database to ensure the systematic and queryable nature of the information, and generate a report that details the extreme operating condition assessment results of the abnormal component to provide a basis for subsequent risk management and decision-making.

[0144] In this embodiment, the specific steps of step S5 are:

[0145] Step S51: performing an extreme operating condition test simulation on the chip component heat distribution trend rendering model based on the extreme operating condition parameters of the abnormal component, and collecting extreme operating condition test simulation response data;

[0146] Step S52: performing deep mining of component operating status on the extreme operating condition test simulation response data to generate extreme operating condition component operating status features;

[0147] Step S53: Predicting chip failure probability trends based on extreme operating condition component operating status characteristics, thereby constructing component failure probability heat maps for different regions;

[0148] Step S54: performing fault internal diffusion path deduction on component failure probability heat maps in different areas, and extracting multiple fault internal diffusion paths.

[0149] In this embodiment, the heat distribution trend rendering model is updated based on the obtained extreme operating condition parameters of the abnormal component. This ensures that the model can reflect heat changes under extreme conditions. Determine the simulation boundary conditions and initial conditions, such as ambient temperature, power load, and cooling conditions. Select an appropriate simulation tool (such as ANSYS, COMSOL Multiphysics, or Fluent) that can handle complex heat conduction and fluid dynamics problems. Ensure that the simulation software supports multi-physics coupling analysis to simulate the interaction between heat and the environment. Enter the extreme operating condition parameters into the simulation model and start the simulation. Observe the thermal response of the model under extreme operating conditions, recording key data such as temperature distribution, heat flux, and component stress. Run a long simulation to ensure that the dynamic process of heat changes is captured, especially heat propagation under extreme conditions. During the simulation, regularly collect and save thermal response data, including temperature change trends and heat distribution diagrams for each component. Generate a simulation results report that details the simulation conditions, results, and observed abnormal phenomena to provide data support for subsequent analysis. Clean and organize the collected extreme operating condition simulation response data to remove irrelevant information and outliers to ensure data accuracy. Standardize the data to facilitate subsequent analysis and comparison. Use data mining techniques (such as principal component analysis and feature selection algorithms) to extract operating status characteristics and identify key indicators related to component performance, such as maximum temperature, temperature fluctuation, and thermal stress. Combined with thermal distribution maps, analyze the temperature distribution and thermal changes of different components under extreme operating conditions to identify high-risk components. Perform cluster analysis on the extracted status characteristics to identify component behavior patterns under different operating conditions. Use K-means or hierarchical clustering algorithms for classification. Generate an operating status characteristic report summarizing the performance of each component under extreme operating conditions, including normal, abnormal, and potential failure states. Select an appropriate failure probability prediction model, such as logistic regression, Bayesian network, or machine learning model (such as random forest or support vector machine). Determine the required input features for the model, including the operating status characteristics extracted from the previous step and historical failure data. Train the selected model using the historical failure data and operating status characteristics. Optimize the model's predictive performance by adjusting model parameters and using cross-validation. Calculate the model's accuracy and other performance metrics to ensure its reliability and effectiveness. Apply the trained model to new operational status feature data to generate predicted failure probability values ​​for each component. These values ​​should reflect the component's failure risk under extreme operating conditions. Organize the prediction results into a data table for subsequent analysis and visualization. Use data visualization tools (such as Matplotlib or Tableau) to generate a failure probability heat map to visually display the failure probability distribution in different areas. Heat map analysis can identify areas with higher failure risks, providing a basis for subsequent failure prevention and management.Based on the failure probability heat map, a fault diffusion model is established to analyze the fault propagation mechanism between components. Use a network-based model or diffusion equation for analysis. Determine the key factors of the diffusion path, such as thermal coupling, physical connections, and functional dependencies between components. Select an appropriate inference algorithm, such as the shortest path algorithm in graph theory, Monte Carlo simulation, or particle swarm optimization method, to deduce the fault diffusion path. Set the starting point of the inference, usually selecting the area with the highest failure probability as the starting point for fault propagation. Run the fault diffusion simulation to generate multiple fault propagation paths, and record the propagation time, impact range, and final affected components of each path. Analyze the characteristics of the path, such as propagation speed, propagation range, and potential losses, to evaluate the impact of the fault on the overall system. Use visualization tools to display the fault diffusion path to help technicians intuitively understand the fault propagation mechanism and impact range. Generate a report that records the inference process, results, and recommendations in detail to support subsequent fault management and prevention strategies.

[0150] In this embodiment, the specific steps of step S53 are:

[0151] Predict the chip failure probability trend based on the operating status characteristics of the extreme working condition components to obtain chip failure probability trend prediction data;

[0152] Perform fault probability time series fitting on chip failure probability trend prediction data to construct a chip failure probability time series curve;

[0153] Identify the faulty component area based on the operating status characteristics of the extreme working condition components and mark the faulty component area;

[0154] The failure probability trend of the faulty component area is mapped according to the chip failure probability timing curve, thereby constructing a component failure probability heat map in different areas.

[0155] In this embodiment, extreme component operating status characteristic data is collected, ensuring that the data includes parameters such as temperature, pressure, and current. These characteristics should be correlated with historical failure data. Data cleaning is performed to remove outliers and missing values ​​to ensure data integrity and accuracy. An appropriate prediction model is selected, such as logistic regression, support vector machine (SVM), or random forest. These models can handle nonlinear relationships and provide probabilistic outputs. Model input features are determined, such as operating status characteristics, workload, and environmental conditions. The selected model is trained using historical failure data and its accuracy is evaluated using cross-validation. The model's generalization ability on unseen data is ensured. Model parameters are adjusted to optimize performance, and the model's accuracy, sensitivity, and specificity are calculated to ensure reliability. The trained model is applied to new operating status characteristic data to generate failure probability prediction data for each time point. The failure probability of each component is recorded and a data table is generated for subsequent analysis and use. Chip failure probability prediction data is collected and organized, sorted in a time series format to ensure temporal consistency. The data frequency is ensured to be consistent, such as sampling on an hourly, daily, or weekly basis. Select an appropriate time series fitting model. Common models include polynomial regression, exponential smoothing, or the Autoregressive Integrated Moving Average (ARIMA) model. Select an appropriate model based on the data characteristics to ensure it captures dynamic changes in failure probability. Input the organized time series data into the selected fitting model for training and calculate the model's fitting parameters. Evaluate model performance using goodness-of-fit (such as the R² value) to ensure the fitting results effectively reflect the trend of failure probability. Generate a time series curve of failure probability based on the fitting results and plot it using visualization tools such as Matplotlib or Seaborn. Mark key points, such as time points where failure probability increases or decreases, for subsequent analysis. Use the extreme component operating status characteristic data obtained in the previous step to ensure that the data contains all relevant features. Perform data cleaning and standardization to improve identification accuracy. Select an appropriate region identification algorithm, such as cluster analysis (such as K-means), heat map analysis, or a machine learning classification algorithm (such as a decision tree). Set the identification threshold and parameters to ensure accurate identification of fault regions. Run the selected algorithm to analyze the operating status characteristic data and identify outliers or regions with high failure probability. Mark the identified faulty areas and record their characteristics and locations. Verify the identified faulty component areas to ensure they match the actual situation. If any issues are found, adjust the algorithm parameters and rerun the algorithm. Record the faulty area identification results in a database for future use. Collect the fault probability time series curve data and the faulty component area identification results to ensure that they correspond. Organize the data and associate the fault probability with specific areas to form a dataset. Select an appropriate visualization tool, such as Matplotlib, Seaborn, or Tableau, to generate a heat map.Based on the heatmap's requirements, select an appropriate color mapping scheme to clearly display the distribution of failure probabilities. Generate a failure probability heatmap using the collected data, ensuring that the failure probabilities in different areas are clearly visible. Match the colors in the heatmap to the failure probabilities, using gradient colors to represent different levels of failure probability. Analyze the generated failure probability heatmap to identify high-risk areas and provide a basis for subsequent fault management and maintenance strategies. Generate a report detailing the heatmap generation process, results, and application value.

[0156] In this embodiment, the specific steps of step S6 are:

[0157] Step S61: performing diffusion path intersection component point analysis on multiple fault internal diffusion paths to extract key fault diffusion component points;

[0158] Step S62: Perform extreme operating condition fault diagnosis on the key component points of the fault diffusion to obtain extreme operating condition fault diagnosis data of the component;

[0159] Step S63: performing a quantitative analysis of the fault repairability of the component extreme operating condition fault diagnosis data, thereby obtaining a quantitative value of the repairability of key component points;

[0160] Step S64: Perform comprehensive fault test evaluation based on the quantitative values ​​of the repairability of key component points, thereby obtaining a chip extreme working condition fault test report.

[0161] In this embodiment, data on multiple fault internal diffusion paths are collected and organized to ensure that each path contains relevant component point information, fault type, and its propagation order. This path information is stored in a structured database for subsequent analysis. Appropriate analysis methods are selected, such as intersection analysis or network analysis methods in graph theory, to identify intersection component points in the fault propagation path. Cross-analysis criteria are determined, such as the connection strength between components, the speed of fault propagation, and the scope of impact. By calculating and comparing component points in different paths, intersection component points appearing in multiple fault propagation paths are identified. Feature information of these intersection component points, such as the number of fault propagation times, associated fault types, and component importance, is recorded. The identified intersection component points are classified. Analyze and extract the component points that play a key role in the spread of faults, summarize the information of these key component points, provide basic data for subsequent extreme working condition fault diagnosis, select appropriate fault diagnosis models, commonly used are rule-based expert systems, statistical learning methods (such as decision trees) or deep learning methods (such as convolutional neural networks), determine the model input features, including operating status data and historical fault records from key component points, use historical fault data to train the selected fault diagnosis model to ensure that the model can accurately identify different fault modes, evaluate the model performance through cross-validation method to ensure its reliability in practical applications, input the extreme working condition data of key component points into the trained model, perform fault diagnosis, and record each The fault type, cause and severity of each component are analyzed, and component extreme condition fault diagnosis data is generated. The diagnosis results are analyzed, and the main fault characteristics of key components are identified. The data are recorded in the database for subsequent use. A preliminary fault diagnosis report is generated, describing the fault conditions and diagnostic methods of each key component. The standards and indicators for quantitative analysis of repairability are determined. Commonly used indicators include fault recovery time, repair cost, and repairability score (such as a score from 1 to 10). In combination with industry standards and historical data, a reasonable repairability evaluation model is set. The fault diagnosis data of key components, including fault type, historical repair records and repair time, are collected. The data are sorted and cleaned to ensure the accuracy and completeness of the data. The reparability quantification standard is used to evaluate each key component and calculate the repairability quantification value. By comparing the repairability quantification values ​​of different components, the components that are easiest to repair and the most difficult to repair are identified. The repairability quantification values ​​are recorded in the database, and a repairability analysis report is generated, which describes the repairability evaluation results of each key component in detail, providing data support for subsequent fault management and maintenance strategies. Based on the repairability quantification value and fault diagnosis data, a comprehensive fault test evaluation model is established. In combination with factors such as failure probability, repair difficulty and impact range, evaluation indicators such as failure risk index, repair priority and overall reliability score are determined. The fault diagnosis data, repairability quantification values ​​and historical fault records of all key components are integrated to form a complete data set for data analysis.Calculate the comprehensive failure risk of each component, assess the overall chip failure risk level, and compile the test and assessment results into a report that includes the failure status of each key component, repair suggestions, and priority ranking. The report should include comprehensive assessment charts and data to intuitively display the chip failure situation. The generated failure test and assessment report will be shared with the relevant technical team and management to formulate subsequent maintenance and repair strategies. Based on the report's recommendations, the maintenance plan will be optimized, high-risk components will be prioritized, and the reliability and safety of the chip will be ensured.

[0162] In this embodiment, a chip testing system is provided for executing the chip testing method described above, including:

[0163] An image enhancement module is used to obtain a thermal imaging image of the chip's working state; perform global color temperature offset optimization on the thermal imaging image of the chip's working state, and perform spatial heat distribution mining to construct a chip heat distribution map;

[0164] The heat distribution trend module is used to track the heat distribution of the chip at multiple times, perform dynamic heat distribution evolution fitting, and construct a dynamic heat distribution trend evolution diagram;

[0165] The chip component layout module is used to obtain high-definition images of the chip under test; perform chip component visual monitoring on the high-definition images of the chip under test, render the heat distribution trend based on the dynamic heat distribution trend evolution diagram, and build a chip component heat distribution trend rendering model;

[0166] The heat situation prediction module is used to perform multi-time point heat situation rolling prediction and extreme operating condition calculation on the heat distribution trend rendering model to generate extreme operating condition parameters of abnormal components;

[0167] The extreme operating condition test module is used to simulate the extreme operating condition test of the chip component heat distribution trend rendering model based on the extreme operating condition parameters of the abnormal component, and then deduce the internal fault diffusion path to extract multiple internal fault diffusion paths;

[0168] The fault diagnosis module is used to diagnose extreme working condition faults based on multiple internal fault diffusion paths, and perform comprehensive fault test evaluation to obtain a chip extreme working condition fault test report.

[0169] The present invention monitors the working status of the chip in real time by acquiring thermal imaging images, and obtains the heat distribution of each component of the chip, which is very important for discovering potential overheating problems. The global color temperature offset optimization eliminates noise and color difference in the thermal imaging image, making the visualization of the heat distribution more accurate, and improving the accuracy of subsequent analysis. Through heat distribution mining, it is possible to deeply analyze the spatial distribution of the chip surface temperature and reveal the heat accumulation in various areas of the chip, which is very important for identifying high-temperature hot spots and areas with insufficient heat dissipation, and helps to optimize the heat dissipation design of the chip. Through multi-time heat distribution tracking processing, the heat change trend of the chip under different working conditions is observed, which is very important for predicting the performance of the chip after long-term operation, and for dealing with temperature fluctuations and Load changes are very critical. Dynamic heat distribution evolution fitting can generate accurate heat evolution curves and provide engineers with long-term heat evolution trends of chips under extreme working conditions. This helps to analyze the impact of heat accumulation on chip performance and identify potential overheating risks. The heat distribution trend diagram can predict the temperature change trajectory of the chip under different working conditions and provide decision support for subsequent fault diagnosis and design optimization. The component layout of the chip is obtained through high-definition images and visual monitoring is performed to accurately identify the various components inside the chip and their heat distribution. The design team identifies which components are susceptible to overheating and which are potential failure points. Combined with the dynamic heat distribution trend evolution diagram, heat distribution trend rendering is performed to provide more accurate information for each chip component. For the precise temperature change trajectory, this provides specific data support for the heat dissipation design and temperature control system optimization of chip components. Based on the heat distribution rendering model, it can identify which components have performance bottlenecks such as overheating and frequency reduction under specific working conditions, helping designers optimize component layout and heat dissipation solutions. Through the rolling prediction of the heat distribution trend rendering model, it dynamically monitors the heat changes of the chip at different time points, evaluates the heat performance of the chip under different load conditions in real time, effectively predicts the performance of the chip under extreme working conditions, and discovers overheating problems in advance. Through extreme working condition calculations, it simulates the operating status of the chip under the most extreme conditions, predicts the high temperature and failure risks of abnormal components, provides data support for the fault warning system, and reduces the occurrence of failures in actual work. The generation of extreme operating parameters can help the design team conduct risk assessments during the product development phase, avoid problems such as overheating and uneven heat dissipation in the design, and optimize the thermal management design of the chip. Through test simulations based on extreme operating parameters, we can gain an in-depth understanding of the chip's performance under extreme conditions, especially its performance and stability under high loads and high temperatures. This helps to identify fault sources and weak links in advance. By deducing the internal diffusion path of the fault, we can simulate the diffusion process after the fault occurs and identify which components will be affected. This helps to determine the propagation mode of the fault within the chip and provide support for fault warning and repair. By extracting multiple fault diffusion paths, we can provide a scientific basis for fault prevention measures and help the design team optimize the chip structure and heat dissipation design.Preventing faults from spreading to other critical components. By analyzing multiple fault diffusion paths, we can accurately diagnose the type, cause, and impact of chip failures under extreme operating conditions, ensuring comprehensive identification of chip failures and proposing targeted solutions. Comprehensive fault testing and evaluation can comprehensively assess chip failure performance under extreme operating conditions and generate detailed test reports, providing data support for subsequent design optimization, production quality control, and maintenance strategies. Extreme condition fault test reports provide important decision-making basis for chip design and production teams, helping to improve chip design, optimize the manufacturing process, and carry out targeted fault repairs and performance improvements.

[0170] The present invention is therefore intended to be illustrative and non-restrictive in all respects, with the scope of the invention being defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the application documents are intended to be embraced therein.

[0171] The foregoing description is intended only to provide specific embodiments of the present invention, which are intended to enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be construed in the widest manner consistent with the principles and novel features disclosed herein.

Claims

1. A chip testing method, characterized in that: The following steps are involved: Step S1: Acquire a thermal imaging image of the chip working state; perform global color temperature offset optimization on the thermal imaging image of the chip working state, and perform spatial heat distribution mining to construct a chip heat distribution map; Step S2: performing multi-time heat distribution tracking processing on the chip heat distribution map, and performing dynamic heat distribution evolution fitting to construct a dynamic heat distribution trend evolution map; Step S3: Acquire a high-definition image of the chip to be tested; Perform visual monitoring of chip components using high-definition images of the chip under test, render the heat distribution trend based on the dynamic heat distribution trend evolution diagram, and build a chip component heat distribution trend rendering model; Step S4: Perform multi-time point thermal situation rolling prediction and extreme operating condition estimation on the heat distribution trend rendering model to generate extreme operating condition parameters of abnormal components; Step S5: Based on the extreme operating condition parameters of the abnormal component, the chip component heat distribution trend rendering model is subjected to extreme operating condition test simulation, and then the internal fault diffusion path is deduced to extract multiple internal fault diffusion paths; Step S6: Perform extreme operating condition fault diagnosis based on multiple internal fault diffusion paths, and perform comprehensive fault test evaluation to obtain a chip extreme operating condition fault test report.

2. The chip testing method according to claim 1, characterized in that: The specific steps of step S1 are: Step S11: continuously acquiring thermal imaging images of the chip's working status using an infrared thermal imaging camera; Step S12: performing global color temperature shift optimization on the thermal imaging image of the chip working state, thereby constructing a global color temperature optimized thermal imaging image; Step S13: performing multi-hotspot visual recognition on the global color temperature optimized thermal imaging image, marking multiple temperature hotspots in the image; Step S14: performing region division based on multiple temperature hot spots in the image to generate multiple temperature region images; Step S15: performing spatial heat distribution mining on multiple temperature region images to construct a chip heat distribution map.

3. The chip testing method according to claim 2, characterized in that: The specific steps of step S12 are: Performing thermocouple noise recognition on the thermal imaging image of the chip in working state, and extracting the noise from the thermal imaging image; Adaptively filter and reduce noise points in thermal imaging images to obtain noise-reduced and optimized thermal imaging images; Performing camera calibration calculation on the infrared thermal imaging camera to obtain internal parameters and external parameters; Performing geometric distortion perspective transformation on the noise reduction optimized thermal imaging image according to internal parameters and external parameters, thereby generating a distortion-corrected thermal imaging image; Perform raw pixel offset analysis on the distortion-corrected thermal imaging image to identify each raw pixel offset value; Perform bilinear interpolation reconstruction based on each original pixel offset value to obtain a pixel offset reconstructed thermal imaging image; Calculate ambient lighting parameters based on infrared thermal imaging camera; Performing an ambient light color temperature characteristic analysis on the ambient light parameters to obtain ambient light color temperature characteristic data; The global color temperature shift of the pixel-shifted reconstructed thermal imaging image is optimized based on the ambient light color temperature characteristic data, thereby constructing a global color temperature optimized thermal imaging image.

4. The chip testing method according to claim 1, characterized in that: The specific steps of step S2 are: Step S21: performing multi-time heat distribution tracking processing on the chip heat distribution map to generate heat distribution maps of multiple time periods; Step S22: performing dynamic heat distribution trend analysis on the heat distribution graphs of multiple time periods, thereby generating dynamic heat distribution trend features; Step S23: performing inter-regional heat gradient identification on the heat distribution graphs of multiple time periods to generate regional heat distribution gradient data; Step S24: performing heat propagation law evolution on the regional heat distribution gradient data, thereby generating a chip heat propagation evolution law; Step S25: performing dynamic heat distribution evolution fitting on the dynamic heat distribution trend characteristics according to the chip heat propagation evolution law, and constructing a dynamic heat distribution trend evolution graph.

5. The chip testing method according to claim 1, characterized in that: The specific steps of step S3 are: Step S31: Acquire a high-definition image of the chip to be tested; Step S32: Perform chip component visual monitoring on the high-definition image of the chip to be tested, and mark each chip component point; Step S33: accurately positioning the spatial position of each chip component point to generate the spatial position coordinates of each component point; Step S34: performing chip component point layout analysis based on the spatial position coordinates of each component point, thereby generating chip component point layout features; Step S35: performing three-dimensional component topology modeling on the chip component point layout features to construct a chip three-dimensional component topology model; Step S36: Rendering the heat distribution trend of the chip three-dimensional component topology model based on the dynamic heat distribution trend evolution diagram to construct a chip component heat distribution trend rendering model.

6. The chip testing method according to claim 1, characterized in that: The specific steps of step S4 are: Step S41: performing a rolling prediction of the heat situation at multiple time points on the heat distribution trend rendering model to generate heat situation prediction data of chip components at multiple time points; Step S42: identifying abnormal component temperatures based on the chip component thermal situation prediction data at multiple time points, and marking abnormal chip component points; Step S43: Obtain the chip's historical operation log, perform normalized operation analysis on the abnormal chip component points based on the chip's historical operation log, and extract normalized operation parameters of the abnormal component; Step S44: performing extreme operating condition calculation based on the normalized operating parameters of the abnormal component to generate extreme operating condition parameters of the abnormal component.

7. The chip testing method according to claim 1, wherein: The specific steps of step S5 are: Step S51: performing an extreme operating condition test simulation on the chip component heat distribution trend rendering model based on the extreme operating condition parameters of the abnormal component, and collecting extreme operating condition test simulation response data; Step S52: performing deep mining of component operating status on the extreme operating condition test simulation response data to generate extreme operating condition component operating status features; Step S53: Predicting chip failure probability trends based on extreme operating condition component operating status characteristics, thereby constructing component failure probability heat maps for different regions; Step S54: performing fault internal diffusion path deduction on component failure probability heat maps in different areas, and extracting multiple fault internal diffusion paths.

8. The chip testing method according to claim 7, characterized in that: The specific steps of step S53 are: Predict the chip failure probability trend based on the operating status characteristics of the extreme working condition components to obtain chip failure probability trend prediction data; Perform fault probability time series fitting on chip failure probability trend prediction data to construct a chip failure probability time series curve; Identify the faulty component area based on the operating status characteristics of the extreme working condition components and mark the faulty component area; The failure probability trend of the faulty component area is mapped according to the chip failure probability timing curve, thereby constructing a component failure probability heat map in different areas.

9. The chip testing method according to claim 1, characterized in that: The specific steps of step S6 are: Step S61: performing diffusion path intersection component point analysis on multiple fault internal diffusion paths to extract key fault diffusion component points; Step S62: Perform extreme operating condition fault diagnosis on the key component points of the fault diffusion to obtain extreme operating condition fault diagnosis data of the component; Step S63: performing a quantitative analysis of the fault repairability of the component extreme operating condition fault diagnosis data, thereby obtaining a quantitative value of the repairability of key component points; Step S64: Perform comprehensive fault test evaluation based on the quantitative values ​​of the repairability of key component points, thereby obtaining a chip extreme working condition fault test report.

10. A chip testing system, characterized in that: The method for performing the chip testing method according to claim 1 comprises: An image enhancement module is used to obtain a thermal imaging image of the chip's working state; perform global color temperature offset optimization on the thermal imaging image of the chip's working state, and perform spatial heat distribution mining to construct a chip heat distribution map; The heat distribution trend module is used to track the heat distribution of the chip at multiple times, perform dynamic heat distribution evolution fitting, and construct a dynamic heat distribution trend evolution diagram; The chip component layout module is used to obtain high-definition images of the chip under test; perform chip component visual monitoring on the high-definition images of the chip under test, render the heat distribution trend based on the dynamic heat distribution trend evolution diagram, and build a chip component heat distribution trend rendering model; The heat situation prediction module is used to perform multi-time point heat situation rolling prediction and extreme operating condition calculation on the heat distribution trend rendering model to generate extreme operating condition parameters of abnormal components; The extreme operating condition test module is used to simulate the extreme operating condition test of the chip component heat distribution trend rendering model based on the extreme operating condition parameters of the abnormal component, and then deduce the internal fault diffusion path to extract multiple internal fault diffusion paths; The fault diagnosis module is used to diagnose extreme working condition faults based on multiple internal fault diffusion paths, and perform comprehensive fault test evaluation to obtain a chip extreme working condition fault test report.

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