A fold-back current limiting protection circuit and a low dropout linear regulator

Abstract

The present invention provides a foldback current limiting protection circuit and a low dropout linear regulator, belonging to the technical field of integrated circuits, including: a first sampling resistor outputs a first current according to a sampling signal of a load current, a first bias current, and a selected second bias current; a second sampling resistor outputs a second current according to a third bias current and a selected fourth bias current; a current comparison network generates a current comparison signal; a common-source amplification module is connected between an output signal of an error amplifier and a ground terminal, is controlled to be turned on and off by the current comparison signal and a selected low signal, and an output terminal is connected to a gate driving module of a power transistor; an output signal feedback network generates a selection signal according to an input signal, an output signal, and an output signal of the error amplifier. Beneficial effects: By detecting the change of the load current of the power transistor, adjusting the gate voltage of the power transistor, realizing a constant load current output, and using the output voltage feedback to clamp the gate voltage of the power transistor at a safe level, foldback current limiting protection is realized.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a foldback current limiting protection circuit and a low dropout regulator. Background Art

[0002] With the progress of technology and the continuous change of social needs for technology, the technology of electronic products has also developed rapidly. This is not only reflected in the performance improvement of traditional electronic products, but also in the emergence of emerging products such as smart phones, wireless mice, laptop computers and other portable and wearable devices.

[0003] As the main power management chips, low dropout regulators (LDOs) and direct current-direct current (DC-DC) converters are also more and more widely used in various electronic products. LDOs are widely used in application scenarios that require high-precision power supplies due to their low noise, stable output voltage, simple structure and other characteristics. The DC-DC converter is widely used in meeting the power conversion requirements of low power consumption and high efficiency of devices due to its high efficiency, wide input voltage range and adjustable output and other characteristics.

[0004] However, with the increasing complexity and diversification of the functions of electronic products, the application scenarios of power management chips have become more complex and changeable. Customers have also put forward higher and higher requirements. Without increasing the chip cost, how to simplify the circuit design, improve the load capacity of the chip, reduce the static power consumption, and improve the system stability and reliability has become the research focus. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a foldback current limiting protection circuit; on the other hand, a low dropout regulator is also provided.

[0006] The technical problem solved by the present invention can be achieved by the following technical solutions: The first aspect of the present invention is to provide a fold-back current limiting protection circuit, including: a current comparison network for comparing a first current flowing through a first sampling resistor and a second current flowing through a second sampling resistor to generate a current comparison signal; wherein, the first current is the sum of a sampling signal of the load current of the power transistor, a first bias current, and a second bias current gated by a gating signal, the second current is the sum of a third bias current and a fourth bias current gated by the gating signal, and the resistance value of the second sampling resistor is different from that of the first sampling resistor; a common-source amplification module connected between the output signal of the error amplifier and the ground terminal, the control terminal of the common-source amplification module is controlled by the current comparison signal and a low signal gated by a control signal to switch the on-off state, and the output terminal of the common-source amplification module is connected to the gate driving module of the power transistor; an output signal feedback network for generating the gating signal according to the input signal, the output signal, and the output signal of the error amplifier, and generating the control signal according to the output signal of the error amplifier.

[0007] Preferably, the resistance value of the second sampling resistor is greater than that of the first sampling resistor.

[0008] Preferably, the first bias current accounts for one-third of the sum of the first bias current and the second bias current; and / or the second bias current accounts for two-thirds of the sum of the first bias current and the second bias current; and / or the third bias current accounts for one-third of the sum of the third bias current and the fourth bias current; and / or the fourth bias current accounts for two-thirds of the sum of the third bias current and the fourth bias current.

[0009] Preferably, the first bias current is 2 times the reference current; and / or the second bias current is 4 times the reference current; and / or the third bias current is 2 times the reference current; and / or the fourth bias current is 4 times the reference current.

[0010] Preferably, the sampling signal is generated by a current detection circuit, and the current detection circuit includes: a first PMOS transistor, the gate of the first PMOS transistor is connected to the gate of the power transistor, the source of the first PMOS transistor is connected to the input signal through the first sampling resistor, and the drain of the first PMOS transistor is used to output the output signal.

[0011] Preferably, the current comparison network includes: a second PMOS transistor, the source of the second PMOS transistor is connected to the input signal through the first sampling resistor; a first NMOS transistor, the gate of the first NMOS transistor is connected to a second bias voltage, the drain of the first NMOS transistor is connected to the gate and drain of the second PMOS transistor, and the source of the first NMOS transistor is connected to the first bias current; a third PMOS transistor, the gate of the third PMOS transistor is connected to the gate of the second PMOS transistor, the source of the third PMOS transistor is connected to the input signal through the second sampling resistor, and the current comparison signal is output from the drain of the third PMOS transistor; a second NMOS transistor, the gate of the second NMOS transistor is connected to the second bias voltage, the drain of the second NMOS transistor is connected to the drain of the third PMOS transistor, and the source of the second NMOS transistor is connected to the third bias current.

[0012] Preferably, it further includes: a first switching transistor, the control terminal of the first switching transistor is connected to the strobe signal, the input terminal of the first switching transistor is connected to the first sampling resistor, and the output terminal of the first switching transistor is connected to the second bias current through a first resistor; a second switching transistor, the control terminal of the second switching transistor is connected to the strobe signal, the input terminal of the second switching transistor is connected to the second sampling resistor, and the output terminal of the second switching transistor is connected to the fourth bias current through a second resistor.

[0013] Preferably, the common-source amplification module includes: a third NMOS transistor, the gate of the third NMOS transistor is connected to the current comparison signal, the drain of the third NMOS transistor is connected to the error amplifier output signal, and the source of the third NMOS transistor is connected to the ground terminal; a fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the control signal, the drain of the fourth NMOS transistor is connected to the current comparison signal, and the source of the fourth NMOS transistor is connected to the ground terminal.

[0014] Preferably, the output signal feedback network includes: a fourth PMOS transistor, whose gate is connected to a first bias voltage, whose source is connected to the input signal, and whose drain outputs the gating signal; a fifth PMOS transistor, whose gate is connected to the output signal through a third resistor and to the ground terminal through a first capacitor, whose source is connected to the gating signal, and whose drain is connected to the ground terminal through a fourth resistor; a fifth NMOS transistor, whose gate is connected to the output signal of the error amplifier, whose drain is connected to a fifth bias current, and whose source is connected to the ground terminal, and the control signal is output from the drain of the fifth NMOS transistor; a sixth NMOS transistor, whose gate is connected to the control signal, whose source is connected to the ground terminal, and whose drain is connected to the gating signal.

[0015] The second aspect of the present invention is to provide a low dropout linear regulator, which includes the fold-back current limiting protection circuit as described above, and further includes: a power transistor for generating an output signal lower than the input signal; an error amplifier, whose input terminals are respectively connected to a reference signal and a feedback signal of the output signal, and whose output terminal is connected to the output signal of the error amplifier; a gate drive module, whose input terminal is connected to the output terminal of the error amplifier, and whose output terminal is connected to the gate of the power transistor.

[0016] The advantages or beneficial effects of the technical solution of the present invention are as follows: By detecting the change in the load current of the power transistor and adjusting the gate voltage of the power transistor, the present invention realizes the limitation of the output power. Especially when the circuit is no-load or light-load, the static power consumption is reduced. When short-circuited or overloaded, by adjusting the gate voltage of the power transistor, a constant load current output is realized, and the output voltage feedback mechanism is used to gradually reduce the output current, clamp the gate voltage of the power transistor at a safe level, realize the fold-back current limiting protection function, and reduce the power consumption of the chip under heavy load; This circuit has the advantages of simple structure, small chip area, low static power consumption, and low power consumption when the circuit is short-circuited or overloaded, and is suitable for scenarios with a relatively low power supply voltage. Description of the Drawings

[0017] Figure 1 It is a circuit schematic diagram of the current limiting loop in a preferred embodiment of the present invention;

[0018] Figure 2 It is a circuit schematic diagram of the output signal feedback network in a preferred embodiment of the present invention;

[0019] Figure 3In a preferred embodiment of the present invention, it is a schematic diagram of the application of a low dropout linear regulator (LDO).

[0020] Figure 4 In a preferred embodiment of the present invention, it is a schematic diagram of the internal structure of a low dropout linear regulator (LDO). Specific embodiments

[0021] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0022] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0023] Next, the present invention will be further described in conjunction with the accompanying drawings and specific embodiments, but it is not a limitation of the present invention.

[0024] See Figure 1 , Figure 2 , Figure 3 and Figure 4 , in a preferred embodiment of the present invention, based on the above problems existing in the prior art, a fold-back current limiting protection circuit is provided, including: a current comparison network 100 for comparing a first current flowing through a first sampling resistor R1 and a second current flowing through a second sampling resistor R2 to generate a current comparison signal VCP; wherein, the first current is the sum of a sampling signal I1 of the load current sampled from a power transistor MP, a first bias current I2, and a second bias current I3 gated by a gating signal PM4_D, and the second current is the sum of a third bias current I4 and a fourth bias current I5 gated by the gating signal PM4_D, and the resistance value of the second sampling resistor R2 is different from that of the first sampling resistor R1; a common-source amplification module 200 connected between the output signal C33_MIN of an error amplifier and the ground terminal, and the control terminal of the common-source amplification module 200 is controlled by the current comparison signal VCP and a low signal gated by a control signal PM11_D to switch the on-off state, and the output terminal of the common-source amplification module 200 is connected to the gate driving module of the power transistor MP; an output signal feedback network 300 for generating the gating signal PM4_D according to an input signal VIN, an output signal VOUT, and the output signal C33_MIN of the error amplifier, and generating the control signal PM11_D according to the output signal C33_MIN of the error amplifier.

[0025] Specifically, the embodiment of the present invention is composed of a first sampling resistor R1, a second sampling resistor R2, a current comparison network 100, a common source amplifier module 200 and an output voltage feedback network 300, wherein the first sampling resistor R1, the second sampling resistor R2, the current comparison network 100 and the common source amplifier module 200 constitute a current limiting loop.

[0026] The first current output by the first sampling resistor R1 is superimposed with the fixed first bias current I2 and the second bias current I3 and the sampling signal I1 of the load current from the power tube MP; the second current output by the second sampling resistor R2 is superimposed with the fixed third bias current I4 and the fourth bias current I5. The second bias current I3 and the fourth bias current I5 are both selected by the selection signal PM4_D. When the selection signal PM4_D is at a high level, the second bias current I3 and the fourth bias current I5 are selected at the same time; when the selection signal PM4_D is at a low level, the second bias current I3 and the fourth bias current I5 are disconnected at the same time.

[0027] In the output signal feedback network 300, it is configured as: outputting a selection signal PM4_D according to an input signal VIN in response to a first bias voltage; changing the size of the selection signal PM4_D in response to an output signal VOUT; outputting a control signal PM11_D in response to an error amplifier output signal C33_MIN; and changing the size of the selection signal PM4_D in response to the control signal PM11_D.

[0028] The current comparison network 100 compares the currents flowing through the two sampling resistors to generate a current comparison signal VCP. The common source amplifier module 200 is connected between the error amplifier output signal C33_MIN and the ground terminal, and switches the on-off state under the control of the current comparison signal VCP. At the same time, when the control signal PM11_D is at a high level, the current comparison signal VCP is pulled down to a low level.

[0029] The principle of the circuit shown in the embodiment of the present invention is that when the load is not loaded, the error amplifier output voltage C33_MIN is small, the control signal PM11_D is at a high level, and the current comparison signal VCP is pulled down to a low level; at the same time, because the control signal PM11_D is at a high level, the selection signal PM4_D is pulled down to a low level, and the second bias current I3 and the fourth bias current I5 in the control current limiting loop are disconnected at the same time. At this time, the fixed bias current is the first bias current I2 and the third bias current I4, that is, twice the reference current, recorded as 2Iref, which can reduce the static power consumption when the load is not loaded.

[0030] When the load is light, the gate voltage of the power transistor MP is relatively large, and the sampling signal I1 of the load current is relatively small. Since the second sampling resistor R2 is greater than the first sampling resistor R1, at this time, the voltage drop across the first sampling resistor R1 is less than the voltage drop across the second sampling resistor R2. The current comparison signal VCP output by the current comparison network 100 is at a low level. The output voltage C33_MIN of the error amplifier increases as the load current increases. The control signal PM11_D is at a low level, and the gating signal PM4_D is at a high level, controlling the second bias current I3 and the fourth bias current I5 in the current limiting loop to be gated simultaneously. At this time, the fixed bias current is the sum of the first bias current I2 and the second bias current I3, and the sum of the third bias current I4 and the fourth bias current I5, that is, six times the reference current, denoted as 6Iref.

[0031] When the load current gradually increases, the voltage drop across the first sampling resistor R1 gradually becomes greater than the voltage drop across the second sampling resistor R2. The current comparison signal VCP output by the current comparison network 100 is at a high level, entering the fixed current limiting state. At this time, the output voltage feedback network 300 starts to function, the output voltage VOUT decreases, pulling the gating signal PM4_D down to a low level, controlling the second bias current I3 and the fourth bias current I5 in the current limiting loop to be disconnected simultaneously. At this time, the magnitude of the bias current changes from 6Iref to 2Iref, and the short-circuit current limiting value becomes 1 / 3 of the fixed current limiting.

[0032] Since the current comparison signal VCP is at a high level, its voltage is raised after passing through the common-source amplification module 200, thereby raising the gate voltage VPG of the power transistor MP. Since the current limiting loop is a closed-loop negative feedback loop, therefore, the gate voltage VPG of the power transistor MP is finally clamped at a fixed potential, so that the power transistor MP outputs a constant load current for fold-back current limiting.

[0033] As a preferred embodiment, the resistance value of the second sampling resistor R2 is greater than the resistance value of the first sampling resistor R1.

[0034] Specifically, in this embodiment, the first sampling resistor R1 is fixedly applied with the first bias current I2 and the sampling signal I1 of the load current, and optionally applied with the second bias current I3.

[0035] Similarly, the third bias current I4 is fixedly applied to the second sampling resistor R2, and the fourth bias current I5 is optionally applied.

[0036] The first sampling resistor R1 and the second sampling resistor R2 convert the current signals in their respective branches into voltage signals, and perform current comparison at the sources of the second PMOS transistor PM2 and the third PMOS transistor PM3 in the current comparison network 100, and output the current comparison signal VCP at the drain of the third PMOS transistor PM3.

[0037] Since R2 > R1, when the circuit is unloaded or lightly loaded, the voltage drop across the first sampling resistor R1 is less than that across the second sampling resistor R2, making the output current comparison signal VCP at a low level; while when the load current gradually increases, the voltage drop across the first sampling resistor R1 gradually becomes greater than that across the second sampling resistor R2, causing the current comparison signal VCP to flip to a high level.

[0038] As a preferred embodiment, the first bias current I2 accounts for one-third of the sum of the first bias current I2 and the second bias current I3; and / or the second bias current I3 accounts for two-thirds of the sum of the first bias current I2 and the second bias current I3; and / or the third bias current I4 accounts for one-third of the sum of the third bias current I4 and the fourth bias current I5; and / or the fourth bias current I5 accounts for two-thirds of the sum of the third bias current I4 and the fourth bias current I5.

[0039] As a preferred embodiment, the first bias current is 2 times the reference current; and / or the second bias current is 4 times the reference current; and / or the third bias current is 2 times the reference current; and / or the fourth bias current is 4 times the reference current.

[0040] Specifically, in this embodiment, the first bias current I2 and the third bias current I4 are of the same magnitude, which is 2 times the reference current, i.e., 2Iref. Similarly, the second bias current I3 and the fourth bias current I5 are of the same magnitude, which is 4 times the reference current, i.e., 4Iref.

[0041] Since the first bias current I2 and the third bias current I4 are fixed bias currents, while the second bias current I3 and the fourth bias current I5 are simultaneously gated on and off.

[0042] If the second bias current I3 and the fourth bias current I5 are simultaneously gated on, the fixed bias current of the circuit is 6Iref.

[0043] If the second bias current I3 and the fourth bias current I5 are simultaneously gated off, the fixed bias current of the circuit is 2Iref.

[0044] Therefore, the fixed bias current of the circuit is realized to switch between 2Iref and 6Iref.

[0045] More specifically, the above-mentioned first bias current I2, second bias current I3, third bias current I4, and fourth bias current I5 are provided by a current mirror module 400, and the current mirror module 400 includes a first transistor NM1, a second transistor NM2, a third transistor NM3, a fourth transistor NM4, a fifth transistor NM5, and a sixth transistor NM6. The first to sixth transistors are all NMOS transistors.

[0046] The gates of the first to sixth transistors are all connected to the second bias voltage VB2. The source of the first transistor NM1 is connected to the ground terminal, the drain of the first transistor NM1 is connected to the source of the second transistor NM2, and the drain of the second transistor NM2 is connected to the reference current I ref , and the reference current I ref is an internal reference current that provides current bias for the circuit. The source of the third transistor NM3 is connected to the ground terminal, and the drain of the third transistor NM3 is used to provide the second bias current I3 mentioned above. The source of the fourth transistor NM4 is connected to the ground terminal, and the drain of the fourth transistor NM4 is used to provide the first bias current I2 mentioned above. The source of the fifth transistor NM5 is connected to the ground terminal, and the drain of the fifth transistor NM5 is used to provide the third bias current I4 mentioned above. The source of the sixth transistor NM6 is connected to the ground terminal, and the drain of the sixth transistor NM6 is used to provide the fourth bias current I5 mentioned above.

[0047] As a preferred embodiment, the sampling signal I1 is generated by a current detection circuit, and the current detection circuit includes: a first PMOS transistor PM1. The gate of the first PMOS transistor PM1 is connected to the gate of the power transistor MP. The source of the first PMOS transistor PM1 is connected to the input signal through a first sampling resistor R1, and the drain of the first PMOS transistor PM1 is used to output the output signal VOUT.

[0048] Specifically, the above sampling signal I1 is the current flowing through the first PMOS transistor PM1.

[0049] As a preferred embodiment, the current comparison network 100 includes: a second PMOS transistor PM2. The source of the second PMOS transistor PM2 is connected to the input signal VIN through a first sampling resistor R1; a first NMOS transistor NM1_LVT. The gate of the first NMOS transistor NM1_LVT is connected to the second bias voltage VB2. The drain of the first NMOS transistor NM1_LVT is connected to the gate and drain of the second PMOS transistor PM2. The source of the first NMOS transistor NM1_LVT is connected to the first bias current I2; a third PMOS transistor PM3. The gate of the third PMOS transistor PM3 is connected to the gate of the second PMOS transistor PM2. The source of the third PMOS transistor PM3 is connected to the input signal VIN through a second sampling resistor R2, and a current comparison signal VCP is output from the drain of the third PMOS transistor PM3; a second NMOS transistor NM2_LVT. The gate of the second NMOS transistor NM2_LVT is connected to the second bias voltage VB. The drain of the second NMOS transistor NM2_LVT is connected to the drain of the third PMOS transistor PM3. The source of the second NMOS transistor NM2_LVT is connected to the third bias current I4.

[0050] Specifically, in this embodiment, the first sampling resistor R1 and the second sampling resistor R2 convert the current into a voltage. By comparing the source voltages of the second PMOS transistor PM2 and the third PMOS transistor PM3, a current comparison signal VCP is output at the drain of the third PMOS transistor PM3.

[0051] The above-mentioned first NMOS transistor NM1_LVT and second NMOS transistor NM2_LVT are NMOS transistors and are both low-threshold devices, that is, devices with a relatively low threshold voltage. When the gate-source voltages of the first NMOS transistor NM1_LVT and the second NMOS transistor NM2_LVT are relatively low, it can ensure that the MOS transistor operates in the saturation region, enabling the entire current comparison network to operate normally at a relatively low supply voltage and being applicable to low-voltage LDOs.

[0052] As a preferred embodiment, it further includes: a first switching transistor NM7. The control terminal (i.e., the gate) of the first switching transistor NM7 is connected to the gating signal PM4_D. The input terminal (i.e., the drain) of the first switching transistor NM7 is connected to the first sampling resistor R1. The output terminal (i.e., the source) of the first switching transistor NM7 is connected to the second bias current I3 through the first resistor R3.

[0053] Specifically, in this embodiment, the second bias current I3 controls the on-off state of the first switching transistor NM7 by the gating signal PM4_D to achieve gating and disconnection.

[0054] If the gating signal PM4_D is at a low level, the first switching transistor NM7 is cut off, and the branch where the second bias current I3 is located is disconnected.

[0055] If the gating signal PM4_D is at a high level, the first switching transistor NM7 is turned on, and the branch where the second bias current I3 is located is gated.

[0056] As a preferred embodiment, it further includes: a second switching transistor NM8. The control terminal (i.e., the gate) of the second switching transistor NM8 is connected to the gating signal PM4_D. The input terminal (i.e., the drain) of the second switching transistor NM8 is connected to the second sampling resistor R2. The output terminal (i.e., the source) of the second switching transistor NM8 is connected to the fourth bias current I5 through the second resistor R4.

[0057] Specifically, in this embodiment, the fourth bias current I5 controls the on-off state of the second switching transistor NM8 by the gating signal PM4_D to achieve gating and disconnection.

[0058] If the gating signal PM4_D is at a low level, the second switching transistor NM8 is cut off, and the branch where the fourth bias current I5 is located is disconnected.

[0059] If the gating signal PM4_D is at a high level, the second switching transistor NM8 is turned on, and the branch where the fourth bias current I5 is located is gated.

[0060] As a preferred embodiment, the common-source amplification module 200 includes: a third NMOS transistor NM9, the gate of the third NMOS transistor NM9 is connected to the current comparison signal VCP, the drain of the third NMOS transistor NM9 is connected to the error amplifier output signal C33_MIN, and the source of the third NMOS transistor NM9 is connected to the ground terminal.

[0061] Specifically, in this embodiment, the third NMOS transistor NM9 serves as the second stage of the error amplifier in the LDO. Its input is connected to the error amplifier output signal C33_MIN of the first stage of the error amplifier, and is controlled by the current comparison signal VCP to amplify the error amplifier output signal C33_MIN, thereby raising the gate voltage of the subsequent power transistor MP. Since the current limiting loop is a closed-loop negative feedback loop, therefore, the gate voltage VPG of the final power transistor MP is clamped at a fixed potential, so that the power transistor MP outputs a constant load current.

[0062] More specifically, the drain of the third NMOS transistor NM9 is connected to the gate driving module of the power transistor MP. This gate driving module can adopt the gate driving circuit in the LDO, which will not be elaborated here.

[0063] As a preferred embodiment, it further includes: a fourth NMOS transistor NM10, the gate of the fourth NMOS transistor NM10 is connected to the control signal PM11_D, the drain of the fourth NMOS transistor NM10 is connected to the current comparison signal VCP, and the source of the fourth NMOS transistor NM10 is connected to the ground terminal.

[0064] Specifically, in this embodiment, the fourth NMOS transistor NM10 is controlled by the control signal PM11_D to switch its on-off state. When the control signal PM11_D is at a low level, the fourth NMOS transistor NM10 is turned off. When the control signal PM11_D is at a high level, the fourth NMOS transistor NM10 is turned on, pulling down the current comparison signal VCP to a low level.

[0065] As a preferred embodiment, the output signal feedback network 300 includes: a fourth PMOS transistor PM4, the gate of the fourth PMOS transistor PM4 is connected to the first bias voltage VB1, the source of the fourth PMOS transistor PM4 is connected to the input signal VIN, and the drain of the fourth PMOS transistor PM4 outputs a gating signal PM4_D.

[0066] Specifically, in this embodiment, since the first bias voltage VB1 is a constant potential, when the LDO is working, the fourth PMOS transistor PM4 is in a normally-on state, and after processing according to the input signal VIN, a gating signal PM4_D is generated at its drain.

[0067] The above VB1 and VB2 are bias voltages, providing voltage reference points for the LDO.

[0068] As a preferred embodiment, the output signal feedback network 300 further includes: a fifth PMOS transistor PM5. The gate of the fifth PMOS transistor PM5 is connected to the output signal VOUT through a third resistor R5 and to the ground terminal through a first capacitor C1. The source of the fifth PMOS transistor PM5 is connected to the gating signal. The drain of the fifth PMOS transistor PM5 is connected to the ground terminal through a fourth resistor R6.

[0069] Specifically, in this embodiment, the third resistor R5, the first capacitor C1, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are used to form an output voltage feedback network, which can respond to changes in the output voltage in a timely manner. Among them, the fourth resistor R6 is a source negative feedback resistor, which can increase the output impedance.

[0070] The fifth PMOS transistor PM5 responds to the control of the output signal VOUT to switch its on-off state, so as to change the magnitude of the gating signal PM4_D.

[0071] When the load current gradually increases until the current comparison signal VCP flips, it enters the fixed current limiting state. At this time, the output signal feedback network 300 starts to act, the output signal VOUT decreases, the gate voltage of the fifth PMOS transistor PM5 also decreases, the pull-down of the path where the fifth PMOS transistor PM5 is located is enhanced, the voltage of the gating signal PM4_D is pulled down, and the branches where the second bias current I3 and the fourth bias current I5 are located are turned off.

[0072] As a preferred embodiment, the output signal feedback network 300 further includes: a fifth NMOS transistor NM11. The gate of the fifth NMOS transistor NM11 is connected to the output signal C33_MIN of the error amplifier. The drain of the fifth NMOS transistor NM11 is connected to the fifth bias current, and the fifth bias current is one-third of the reference current, that is, 1 / 3Iref. The source of the fifth NMOS transistor NM11 is connected to the ground terminal, and a control signal NM11_D is output from the drain of the fifth NMOS transistor NM11.

[0073] Specifically, in this embodiment, the fifth NMOS transistor NM11 responds to the control of the output signal C33_MIN of the error amplifier to switch its on-off state, and a control signal NM11_D is generated at the drain of the fifth NMOS transistor NM11.

[0074] The output signal C33_MIN of the error amplifier increases as the load current increases. When there is no load, the output signal C33_MIN of the error amplifier is small, and the fifth NMOS transistor NM11 is cut off.

[0075] When the load is light or the load current gradually increases, the fifth NMOS transistor NM11 operates in the subthreshold region, enhancing the pull-down effect, and the control signal NM11_D outputs a low level.

[0076] As a preferred embodiment, the output signal feedback network 300 further includes: a sixth NMOS transistor NM12, the gate of the sixth NMOS transistor NM12 is connected to the control signal NM11_D, the source of the sixth NMOS transistor NM12 is connected to the ground terminal, and the drain of the sixth NMOS transistor NM12 is connected to the gating signal PM4_D.

[0077] Specifically, in this embodiment, the sixth NMOS transistor NM12 switches its on / off state in response to the control of the control signal NM11_D to change the magnitude of the gating signal PM4_D. When the control signal NM11_D is at a low level, the sixth NMOS transistor NM12 is turned off. When the control signal NM11_D is at a high level, the sixth NMOS transistor NM12 is turned on, pulling down the gating signal PM4_D to a low level.

[0078] The present invention proposes a foldback current limiting protection circuit applicable to a low-voltage LDO. First, the power transistor MP is a PMOS transistor. When the circuit is unloaded or lightly loaded, the gate voltage VPG of the power transistor MP is relatively high, and the sampling signal I1 of the load current is relatively small, and the current limiting loop is turned off, which can reduce the static power consumption. When the circuit is short-circuited or overloaded, the gate voltage VPG of the power transistor MP is relatively low, and the sampling signal I1 of the load current is relatively large. At this time, the current comparison signal VCP generated by the current comparison in the current limiting loop passes through the common-source amplification module of the second stage of the error amplifier to raise the gate voltage of the power transistor MP, so that the power transistor MP outputs a constant load current.

[0079] Due to the presence of the output voltage feedback network 300 in the circuit, when the output voltage decreases, the output current gradually decreases, and the gate voltage VPG of the power transistor MP is clamped at a relatively small value, achieving short-circuit current limiting and protecting the chip.

[0080] The fixed current limiting value during overload is 6 times the reference current, and the short-circuit current limiting value during short circuit is 2 times the reference current, so as to be able to achieve the foldback function. This circuit has the advantages of simple structure, small chip area, and low power consumption when the circuit is short-circuited or overloaded.

[0081] The present invention also provides a low-dropout linear regulator, including the foldback current limiting protection circuit as described above, such as Figure 3 and Figure 4As shown, it further includes: a power transistor MP for generating an output signal VOUT lower than the input signal VIN; an error amplifier 10, the input terminals of the error amplifier 10 are respectively connected to a reference signal and a feedback signal of the output signal, and the output terminal of the error amplifier 10 is connected to an error amplifier output signal C33_MIN; wherein, C33_MIN is the error amplifier output voltage of the first stage of the error amplifier, providing a bias voltage for the current limiting protection circuit; a gate drive module 20, the input terminal of the gate drive module 20 is connected to the output terminal of the error amplifier 10, and the output terminal of the gate drive module 20 is connected to the gate of the power transistor MP.

[0082] As Figure 3 shown is a schematic application diagram of a low dropout linear regulator (LDO). The low dropout linear regulator LDO includes four ports, namely an input port, an output port, an enable port, and a ground port. The input port is used to receive an input signal VIN, the output port is used to output an output signal VOUT, and the enable port is used to receive an enable control signal. Among them, an input capacitor C IN is connected between the input signal VIN and the ground terminal, and an output capacitor C OUT is connected between the output signal VOUT and the ground terminal.

[0083] As Figure 4 shown is a schematic internal structure diagram of a low dropout linear regulator (LDO). The internal of the low dropout linear regulator LDO may include a power transistor MP, an error amplifier 10, a gate drive module 20, a pre-regulator amplifier 30, and a current limiting protection & over-temperature protection 40.

[0084] Among them, the pre-regulator amplifier 30 is an operational amplifier. The non-inverting input terminal of the operational amplifier is connected to a reference signal, and the inverting input terminal of the operational amplifier is connected to a voltage division feedback signal of its own output voltage. This voltage division feedback signal is obtained by voltage division of voltage division resistors R12 and R13.

[0085] The non-inverting input terminal of the error amplifier 10 is connected to the output signal VOUT, the inverting input terminal of the error amplifier 10 is connected to the output terminal of the operational amplifier through a filter resistor R14, a filter capacitor C11 is also connected between the inverting input terminal of the error amplifier 10 and the ground terminal, the output terminal of the error amplifier 10 is connected to the input terminal of the gate drive module 20, the output terminal of the gate drive module 20 is connected to the gate of the power transistor MP, the source of the power transistor MP is connected to the input signal VIN, and the drain of the power transistor MP generates the output signal VOUT.

[0086] The internal of the low dropout linear regulator LDO may further include an inverter INV1, a switching transistor Mn, and a resistor R11. The gate of the switching transistor Mn is connected to the enable control signal through the inverter INV1, the source of the switching transistor Mn is connected to the ground terminal, and the drain of the switching transistor Mn is connected to the above output signal VOUT through the resistor R11.

[0087] The fold-back current-limiting protection circuit of the present invention serves as the current-limiting protection part.

[0088] In the current-limiting loop, the current in the branch where the fourth transistor NM4 and the fifth transistor NM5 are located is 2Iref; the sixth transistor NM6 and the seventh transistor NM7 also form a fixed bias current, and the current in the branch where they are located is 4Iref. The current of the first sampling resistor R1 is superimposed with a fixed first bias current I2, a second bias current I3, and a sampling signal I1 that varies with the load current.

[0089] When no load is present, the output voltage C33_MIN of the error amplifier is small, and the fifth NMOS transistor NM11 operates in the subthreshold region. The output control signal NM11_D is at a high level, controlling the gate voltage of the fourth NMOS transistor NM10, causing the fourth NMOS transistor NM10 to operate in the linear region and pulling down the current comparison signal VCP to a low level.

[0090] At the same time, since the control signal NM11_D is at a high level, the pull-down of the sixth NMOS transistor NM12 is enhanced, causing the sixth NMOS transistor NM12 to operate in the linear region and pulling down the strobe signal PM4_D to a low level, controlling the first switch transistor NM7 and the second switch transistor NM8 in the current-limiting loop to be cut off, so that the second bias current I3 and the fourth bias current I5 are both disconnected. At this time, the fixed bias current is 2Iref, which can reduce the static power consumption when no load is present.

[0091] When lightly loaded, the gate voltage VPG of the power transistor MP is large, and the sampling signal I1 of the load current is small. Since R2 > R1, the voltage drop across the first sampling resistor R1 is less than the voltage drop across the second sampling resistor R2. The source voltage of the second PMOS transistor PM2 is higher than the source voltage of the third PMOS transistor PM3, and the output current comparison signal VCP is at a low level, causing the third NMOS transistor NM9 to be cut off.

[0092] The output voltage C33_MIN of the error amplifier increases as the load current increases. The fifth NMOS transistor NM11 operates in the subthreshold region, and the pull-down is enhanced. The output control signal NM11_D is at a low level, controlling the gate voltage of the fourth NMOS transistor NM10, causing the fourth NMOS transistor NM10 to operate in the cut-off region. At this time, the strobe signal PM4_D is at a high level, controlling the first switch transistor NM7 and the second switch transistor NM8 in the current-limiting loop to be turned on, so that the second bias current I3 and the fourth bias current I5 are both selected. At this time, the fixed bias current is 6Iref.

[0093] When the load current gradually increases, the source voltage of the second PMOS transistor PM2 gradually decreases. When the source voltage of the second PMOS transistor PM2 is lower than the source voltage of the third PMOS transistor PM3, the output current comparison signal VCP flips to a high level and enters the fixed current limiting state. At this time, the output voltage feedback network 300 starts to function, the output signal VOUT decreases, the gate voltage of the fifth PMOS transistor PM5 also decreases, the pull-down of the path where the fifth PMOS transistor PM5 is located is enhanced, and the voltage of the gating signal PM4_D is pulled low, closing the branches where the second bias current I3 and the fourth bias current I5 are located. At this time, the magnitude of the bias current changes from 6Iref to 2Iref, and the short-circuit current limiting value becomes 1 / 3 of the fixed current limit.

[0094] Since the current comparison signal VCP is at a high level, its voltage is raised through the second common-source amplification module 200 of the error amplifier, thereby raising the gate voltage VPG of the power transistor MP. Since the current limiting loop is a closed-loop negative feedback loop, the gate voltage VPG of the power transistor MP is finally clamped at a fixed potential, so that the power transistor MP outputs a constant load current for fold-back current limiting.

[0095] The advantages or beneficial effects of adopting the above technical solution are as follows: The present invention realizes the limitation of the output power by detecting the change of the load current of the power transistor and adjusting the gate voltage of the power transistor. Especially when the circuit is no-load or light-load, the static power consumption is reduced. When short-circuited or overloaded, the gate voltage of the power transistor is adjusted to achieve a constant load current output, and the output current is gradually reduced by using the output voltage feedback mechanism, clamping the gate voltage of the power transistor at a safe level to realize the fold-back current limiting protection function, reducing the power consumption of the chip under heavy load; this circuit has the advantages of simple structure, small chip area, low static power consumption, and low power consumption when the circuit is short-circuited or overloaded, and is suitable for scenarios with a relatively low power supply voltage.

[0096] The above are only the preferred embodiments of the present invention, and do not limit the implementation manners and protection scope of the present invention accordingly. For those skilled in the art, it should be able to realize that all equivalent replacements and obvious changes made by using the content of this specification and the drawings should be included in the protection scope of the present invention.

Claims

1. A foldback current limiting protection circuit, characterized in that: include: A current comparison network, used for comparing a first current flowing through a first sampling resistor and a second current flowing through a second sampling resistor to generate a current comparison signal; wherein the first current is the sum of a sampling signal of a load current sampled from a power tube, a first bias current, and a second bias current of the first switch tube selected by a selection signal, the second current is the sum of a third bias current and a fourth bias current of the second switch tube selected by the selection signal, and the resistance value of the second sampling resistor is different from the resistance value of the first sampling resistor; the first bias current and the third bias current are bias currents of two comparison branches where the current comparison network is located, respectively, the second bias current is the bias current of the branch where the first switch tube is located, and the fourth bias current is the bias current of the branch where the second switch tube is located; A common source amplifier module is connected between the error amplifier output signal and the ground terminal, the control end of the common source amplifier module is controlled by the current comparison signal and the low signal selected by the control signal to switch the on and off state, and the output end of the common source amplifier module is connected to the gate drive module of the power tube; The output signal feedback network is used to generate the selection signal according to the input signal of the power tube, the output signal of the power tube, and the error amplifier output signal, and to generate the control signal according to the error amplifier output signal.

2. The foldback current limiting protection circuit according to claim 1, characterized in that: The resistance of the second sampling resistor is greater than the resistance of the first sampling resistor.

3. The foldback current limiting protection circuit according to claim 1, characterized in that: The first bias current accounts for one third of the sum of the first bias current and the second bias current; and / or The second bias current accounts for two thirds of the sum of the first bias current and the second bias current; and / or The third bias current accounts for one third of the sum of the third bias current and the fourth bias current; and / or The fourth bias current accounts for two thirds of the sum of the third bias current and the fourth bias current.

4. The foldback current limiting protection circuit according to claim 1, characterized in that: The first bias current is twice the reference current; and / or The second bias current is 4 times the reference current; and / or The third bias current is twice the reference current; and / or The fourth bias current is four times the reference current.

5. The foldback current limiting protection circuit according to claim 1, characterized in that: The sampling signal is generated by a current detection circuit, and the current detection circuit includes: A first PMOS tube, wherein the gate of the first PMOS tube is connected to the gate of the power tube, the source of the first PMOS tube is connected to the input signal through the first sampling resistor, and the drain of the first PMOS tube is used to output the output signal.

6. The foldback current limiting protection circuit according to claim 1, characterized in that: The current comparison network comprises: a second PMOS tube, wherein a source of the second PMOS tube is connected to the input signal through the first sampling resistor; a first NMOS transistor, wherein the gate of the first NMOS transistor is connected to the second bias voltage, the drain of the first NMOS transistor is connected to the gate and drain of the second PMOS transistor, and the source of the first NMOS transistor is connected to the first bias current; a third PMOS tube, wherein the gate of the third PMOS tube is connected to the gate of the second PMOS tube, the source of the third PMOS tube is connected to the input signal through the second sampling resistor, and the current comparison signal is output from the drain of the third PMOS tube; A second NMOS tube, wherein the gate of the second NMOS tube is connected to the second bias voltage, the drain of the second NMOS tube is connected to the drain of the third PMOS tube, and the source of the second NMOS tube is connected to the third bias current.

7. The foldback current limiting protection circuit according to claim 1, characterized in that: Also includes: The control end of the first switch tube is connected to the selection signal, the input end of the first switch tube is connected to the first sampling resistor, and the output end of the first switch tube is connected to the second bias current through the first resistor; The control end of the second switch tube is connected to the selection signal, the input end of the second switch tube is connected to the second sampling resistor, and the output end of the second switch tube is connected to the fourth bias current through the second resistor.

8. The foldback current limiting protection circuit according to claim 1, characterized in that: The common source amplification module comprises: a third NMOS tube, wherein a gate of the third NMOS tube is connected to the current comparison signal, a drain of the third NMOS tube is connected to the error amplifier output signal, and a source of the third NMOS tube is connected to the ground terminal; A fourth NMOS tube, wherein a gate of the fourth NMOS tube is connected to the control signal, a drain of the fourth NMOS tube is connected to the current comparison signal, and a source of the fourth NMOS tube is connected to the ground terminal.

9. The foldback current limiting protection circuit according to claim 1, characterized in that: The output signal feedback network comprises: a fourth PMOS tube, wherein a gate of the fourth PMOS tube is connected to a first bias voltage, a source of the fourth PMOS tube is connected to the input signal, and a drain of the fourth PMOS tube outputs the selection signal; a fifth PMOS tube, wherein a gate of the fifth PMOS tube is connected to the output signal through a third resistor and to the ground terminal through a first capacitor, a source of the fifth PMOS tube is connected to the selection signal, and a drain of the fifth PMOS tube is connected to the ground terminal through a fourth resistor; a fifth NMOS tube, wherein the gate of the fifth NMOS tube is connected to the output signal of the error amplifier, the drain of the fifth NMOS tube is connected to the fifth bias current, the source of the fifth NMOS tube is connected to the ground terminal, and the control signal is output from the drain of the fifth NMOS tube; A sixth NMOS tube, wherein a gate of the sixth NMOS tube is connected to the control signal, a source of the sixth NMOS tube is connected to the ground terminal, and a drain of the sixth NMOS tube is connected to the selection signal.

10. A low voltage dropout linear regulator, characterized in that: The foldback current limiting protection circuit according to any one of claims 1 to 9 further comprises: Power tube, used to generate an output signal lower than the input signal; An error amplifier, wherein the input end of the error amplifier is respectively connected to a reference signal and a feedback signal of the output signal, and the output end of the error amplifier is connected to the error amplifier output signal; A gate driving module, wherein the input end of the gate driving module is connected to the output end of the error amplifier, and the output end of the gate driving module is connected to the gate of the power tube.

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