Low dropout linear regulator with wide dropout range

Abstract

The invention discloses a low dropout linear regulator with a wide dropout range, which is characterized in that an error amplifier is supplied with power by output voltage of the low dropout linear regulator, and a common-gate buffer is supplied with power by input voltage of the low dropout linear regulator, so that a direct interference path of the input voltage to the output only exists in a common-gate buffer stage and an output stage; and the power supply rejection ratio is improved. The common-gate buffer solves the problem of margin loss caused by a traditional source follower circuit, a positive feedback loop arranged in the common-gate buffer is used for improving the slew rate of a driving signal VPGATE and providing a certain gain, and therefore the problem of margin under low dropout is solved, and the reliability of the driving circuit is improved. And the compensation circuit can adjust the compensation amount of the low-dropout linear regulator when the input voltage is higher than a preset threshold value, so that the stability of the low-dropout linear regulator under different working conditions is improved.

Description

Technical Field

[0001] The invention relates to the field of electronic power technology, and in particular to a low voltage difference linear regulator with a wide voltage difference range. Background Art

[0002] In modern electronic circuit design, as the external application range of products becomes larger, the requirements for the conversion efficiency of power modules continue to increase. Low-voltage dropout linear converters may not be able to adapt to the ideal characteristics of maintaining a high output voltage under a wide range of input voltages and a wide range of load applications. High voltage dropout means that the power tube works in the saturation region, and only needs to solve the wide application of the load; low voltage dropout makes the power tube in the linear region, which means a large power tube area, not only need to solve the load problem, but also need to solve the interference suppression ability of the power supply and stability under a wide load. When the input application ranges of the two are mixed together, it is difficult to design a circuit to take into account both applications.

[0003] Please refer to Figure 1 , is a traditional LDO schematic diagram, EA is the error amplifier, used for control loop; M P0 It is a power tube, used to transfer energy to the output; R f1 , R f2 is the feedback resistor, used to sample the output voltage; C o It is the output capacitor. When the output voltage performance requirements are high, it is often an off-chip capacitor, and ESR is its parasitic resistance, which is used to stabilize the output voltage.

[0004] When the input and output voltage difference is large, such as V IN =3.3V, V O =1.5V,M p0 Working in the saturation region, its transfer function is R load is the load resistance, g mp0 、r op0 M P0 Transconductance and output impedance, H ea (s) is the EA transmission function. P0 Often larger in size, resulting in H ea (s)There will be a low-frequency pole.

[0005] There are two low-frequency poles in the loop ); ; Among them, C1 is the EA output capacitor, including the parasitic capacitance of EA itself and the power tube M P0 of parasitic capacitance.

[0006] Since p0 only changes with the load and p1 is relatively fixed, when the load changes greatly, the relative positions of p0 and p1 change, and there are certain problems with the stability of the system. Therefore, a buffer is introduced to push the p1 pole outward and p0 becomes the main pole of the system to provide appropriate phase margin and gain margin.

[0007] When the power supply is disturbed, the input power supply disturbance under open loop can be well suppressed. The power supply rejection ratio is as follows: ; The power supply rejection ratio PSR fd V IN To output voltage V o The feedforward gain. When the power tube is in the saturation region, the loop gain H loop_gain (s) is large, so the power supply rejection ratio can be better suppressed.

[0008] When V IN When the voltage continues to decrease, such as 1.8V, the power tube M P0 Entering the linear region, r op0 The load impedance is equivalent to that under heavy load. In order to maintain a large power output under low voltage difference, the power tube M P0 The size will become very large, and the parasitic capacitance of the power tube in the linear region will be more than twice that of the saturation region, and the p0 pole will move away from the far point.

[0009] Please refer to Figure 2 At this time, for the compensation method of the power tube in the saturation region, due to the offset of the main pole, the additional pole generated by inserting the buffer may enter the bandwidth, and the relative position of the main and secondary points may also change, which will deteriorate the loop stability. Loop gain H loop_gain (s) decreases, and the power supply rejection ratio is deteriorated. If the main pole is the EA output terminal and the secondary point is the LDO output at low voltage, the stability at low voltage is improved. However, due to the existence of off-chip capacitors and the change of power tube impedance at high voltage, the output pole p0 will move toward the origin, and the stability at high voltage will be difficult to guarantee. Summary of the invention

[0010] The object of the present invention is to provide a low voltage drop linear regulator with a wide voltage drop range, improve the power supply rejection ratio and circuit stability, and achieve fast transient response.

[0011] The present invention provides a low voltage drop linear regulator, comprising: An error amplifier EA, used for generating a control signal Vea; A common-gate buffer Buffer is powered by an input voltage VIN of a low-dropout linear regulator; the common-gate buffer Buffer includes a positive feedback loop, and the positive feedback loop is used to increase the slew rate of the control signal Vea and then output a drive signal VPGATE; The driving signal VPGATE is used to control the voltage feedback circuit to output the output voltage VO of the low-dropout linear regulator, and the output voltage VO is used to power the error amplifier EA.

[0012] Further, the positive feedback loop includes: a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN5 and a second NMOS tube MN6; The sources of the first PMOS tube MP1 and the second PMOS tube MP2 are both connected to the input voltage VIN; the sources of the first NMOS tube MN5 and the second NMOS tube MN6 are both grounded, the drain of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN5 to form a first connection node, the first connection node outputs the driving signal VPGATE, the drain of the second PMOS tube MP2 is connected to the drain of the second NMOS tube MN6, the gates of the first NMOS tube MN5 and the second NMOS tube MN6 are connected; the gate of the second NMOS tube MN6 is also connected to the drain of the second NMOS tube MN6.

[0013] Furthermore, the common-gate buffer Buffer further includes a first resistor R1; the first resistor R1 is connected in parallel between the drain and the source of the first PMOS transistor MP1.

[0014] Furthermore, the common-gate buffer Buffer also includes a common-gate input tube MN4; The gate of the common-gate input tube MN4 is connected to a bias voltage; the source of the common-gate input tube MN4 is connected to the drain of the first NMOS tube MN5, the output end VEA of the error amplifier EA is connected between the source of the common-gate input tube MN4 and the drain of the first NMOS tube MN5; the drain of the common-gate input tube MN4 is connected between the drain of the first PMOS tube MP1 and the drain of the first NMOS tube MN5.

[0015] Furthermore, the common-gate buffer Buffer also includes a filter circuit, and the filter circuit includes a second resistor R2 and a first capacitor C1; Two ends of the second resistor R2 are connected between the gates of the first NMOS transistor MN5 and the second NMOS transistor MN6, one end of the second resistor R2 connected to the first NMOS transistor MN5 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded.

[0016] Further, the error amplifier EA includes a differential input stage, and the differential input stage includes: a third PMOS tube MP5, a fourth PMOS tube MP6, a third NMOS tube MN7, a fourth NMOS tube MN8 and a fifth PMOS tube MP7; The gates of the third PMOS transistor MP5 and the fourth PMOS transistor MP6 receive the feedback voltage Vfb and the reference voltage Vref respectively, and the sources are connected; The source of the fifth PMOS transistor MP7 is connected to the output voltage VO, the drain is connected to the sources of the third PMOS transistor MP5 and the fourth PMOS transistor MP6, and the gate is connected to the first bias voltage Vbias1; The sources of the third NMOS tube MN7 and the fourth NMOS tube MN8 are both grounded, and the drains of the third NMOS tube MN7 and the fourth NMOS tube MN8 are respectively connected to the drains of the third PMOS tube MP5 and the fourth PMOS tube MP6; wherein, the connection node after the drain of the third NMOS tube MN7 is connected to the drain of the third PMOS tube MP5 serves as the first output end of the differential input stage, the connection node after the drain of the fourth NMOS tube MN8 is connected to the drain of the fourth PMOS tube MP6 serves as the second output end of the differential input stage, and the gates of the third NMOS tube MN7 and the fourth NMOS tube MN8 are respectively connected to the drains of the third NMOS tube MN7 and the fourth NMOS tube MN8.

[0017] Further, the error amplifier EA further includes a common source amplifier stage, and the common source amplifier stage includes: a sixth PMOS tube MP8, a fifth NMOS tube MN9, a seventh PMOS tube MP9 and a sixth NMOS tube MN10; The gates of the fifth NMOS transistor MN9 and the sixth NMOS transistor MN10 are respectively connected to the first output terminal and the second output terminal of the differential input stage, and the sources are both grounded; The sources of the sixth PMOS tube MP8 and the seventh PMOS tube MP9 are both connected to the output voltage VO, and the gates are interconnected. The drain of the sixth PMOS tube MP8 is connected to the drain of the fifth NMOS tube MN9, and the drain of the sixth PMOS tube MP8 is also connected to its gate; the drain of the seventh PMOS tube MP9 is connected to the drain of the sixth NMOS tube MN10.

[0018] Further, the error amplifier EA further includes a low-gain common-source amplifier stage, and the low-gain common-source amplifier stage includes: an eighth PMOS tube MP10 and a seventh NMOS tube MN11; The source of the eighth PMOS tube MP10 is connected to the output voltage VO, and the gate is connected between the drain of the seventh PMOS tube MP9 and the drain of the sixth NMOS tube MN10; the drain of the eighth PMOS tube MP10 is connected to the drain of the seventh NMOS tube MN11 and then outputs the control signal Vea; the source of the seventh NMOS tube MN11 is grounded, and the gate of the seventh NMOS tube MN11 is connected to the second bias voltage Vbias2.

[0019] Further, the voltage feedback circuit includes a power tube MP0; The gate of the power transistor MP0 receives the driving signal VPGATE, the source is connected to the input voltage VIN, and the drain outputs the output voltage VO to the error amplifier EA.

[0020] Further, the voltage feedback circuit includes a feedback network; The feedback network divides the output voltage VO to obtain the feedback voltage Vfb, and the feedback voltage Vfb is input into the non-inverting input terminal of the error amplifier EA, wherein the drain of the power tube MP0 is connected to one end of the feedback network to form a second connection node.

[0021] Furthermore, a compensation circuit is included, and the compensation circuit includes: a first compensation capacitor Cc, a second compensation capacitor Cc' and a voltage-controlled switch S0; One end of the first compensation capacitor Cc is connected to the second connection node, and the other end is connected to the voltage dividing node of the feedback network; One end of the voltage-controlled switch S0 is connected to one end of the first compensation capacitor Cc, and the other end is connected to one end of the second compensation capacitor Cc'; the other end of the second compensation capacitor Cc' is connected to the other end of the first compensation capacitor Cc.

[0022] Furthermore, it also includes a pull-down tube MN0, the gate of the pull-down tube MN0 is connected to the output end of the error amplifier EA, the source is grounded, and the drain inputs the output voltage VO into the error amplifier EA.

[0023] Furthermore, it also includes an off-chip capacitor C0 and a parasitic resistor esr; One end of the parasitic resistor esr is connected to the second connection node, and the other end is connected to one end of the off-chip capacitor C0 , and the other end of the off-chip capacitor C0 is grounded.

[0024] Compared with the prior art, the present invention has at least the following technical effects: The error amplifier disclosed in the present invention is powered by the output voltage of the low-dropout linear regulator, and the common-gate buffer is powered by the input voltage of the low-dropout linear regulator, so that the direct interference path of the input voltage to the output only exists in the common-gate buffer stage and the output stage, thereby improving the power supply rejection ratio. The common-gate buffer not only solves the margin loss caused by the traditional source follower circuit, but also the internally arranged positive feedback loop does not introduce additional poles within the bandwidth, thereby solving the margin problem under low-dropout conditions and improving the stability of the low-dropout linear regulator under different working conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the circuit structure of LDO in the prior art; Figure 2 It is a schematic diagram of the circuit structure of a buffer-level LDO in the prior art; Figure 3 A schematic diagram of the circuit structure of a low voltage dropout linear regulator according to an embodiment of the present invention; Figure 4 Schematic diagram of the circuit structure of a common-gate buffer Buffer in one embodiment of the present invention; Figure 5 FIG. 4 is a schematic diagram of the circuit structure of the error amplifier EA in one embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following is a description of a low-voltage dropout linear regulator with a wide voltage dropout range of the present invention in conjunction with a schematic diagram, wherein a preferred embodiment of the present invention is shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation of the present invention.

[0027] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.

[0028] Please refer to Figure 3-Figure 5 This embodiment discloses a low-voltage dropout linear regulator with a wide voltage dropout range, and the low-voltage dropout linear regulator with a wide voltage dropout range includes: The error amplifier EA is used to generate a control signal Vea; the common-gate buffer Buffer is powered by the input voltage VIN of the low-dropout linear regulator; the common-gate buffer Buffer includes a positive feedback loop, which is used to increase the slew rate of the control signal Vea and then output a drive signal VPGATE. The drive signal VPGATE is used to control the voltage feedback circuit to output the output voltage VO of the low-dropout linear regulator, and the output voltage VO is used to power the error amplifier EA.

[0029] In this embodiment, the error amplifier EA is powered by the output voltage VO of the low-dropout linear regulator, and the common-gate buffer Buffer is powered by the input voltage VIN of the low-dropout linear regulator, so that the direct interference path of the input voltage VIN to the output only exists in the common-gate buffer stage and the output stage. The power supply rejection ratio (PSR) is improved. In addition, the common-gate buffer Buffer not only solves the margin loss caused by the traditional source follower circuit, but also the internal positive feedback loop does not introduce additional poles within the bandwidth, solves the margin problem under low voltage difference, and improves the stability of the low-dropout linear regulator under different working conditions.

[0030] In this embodiment, please refer to Figure 4 The positive feedback loop includes: a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN5 and a second NMOS tube MN6.

[0031] Specifically, the sources of the first PMOS tube MP1 and the second PMOS tube MP2 are both connected to the input voltage VIN; the sources of the first NMOS tube MN5 and the second NMOS tube MN6 are both grounded, the drain of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN5 to form a first connection node, the first connection node outputs the drive signal VPGATE, the drain of the second PMOS tube MP2 is connected to the drain of the second NMOS tube MN6, the gate of the first NMOS tube MN5 is connected to the gate of the second NMOS tube MN6; the gate of the second NMOS tube MN6 is also connected to the drain of the second NMOS tube MN6.

[0032] In this embodiment, the positive feedback formed by the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube MN5 and the second NMOS tube MN6 is highly sensitive to the control signal Vea output by the error amplifier EA, thereby improving the gain from the control signal Vea to the drive signal VPGATE, and effectively compensating for the low gain problem caused by the main pole being located at the output end. At the same time, the buffer is powered by the input voltage VIN and the error amplifier EA is powered by the feedback voltage Vfb, so that the interference path of the input voltage VIN to the output only exists in the common gate buffer stage and the output stage, thereby improving the power supply rejection ratio.

[0033] Preferably, in order to further increase the responsiveness of the loop, in this embodiment, the width-to-length ratio of the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN5, and the second NMOS transistor MN6 is set to 1:1.

[0034] Furthermore, in this embodiment, the common-gate buffer Buffer also includes a common-gate input tube MN4.

[0035] Specifically, the gate of the common-gate input tube MN4 is connected to the bias voltage; the source of the common-gate input tube MN4 is connected to the drain of the first NMOS tube MN5, the output end VEA of the error amplifier EA is connected between the source of the common-gate input tube MN4 and the drain of the first NMOS tube MN5; the drain of the common-gate input tube MN4 is connected between the drain of the first PMOS tube MP1 and the drain of the first NMOS tube MN5.

[0036] In this embodiment, the common-gate input transistor MN4 replaces the traditional source follower bias, thereby reducing margin loss and area.

[0037] In a specific example, the bias voltage is generated by a bias circuit so that the common-gate input transistor MN4 can operate at a suitable operating point. Figure 4 The bias circuit includes a ninth PMOS tube MP3, a tenth PMOS tube MP4, an eighth NMOS tube MN1, a ninth NMOS tube MN3 and a tenth NMOS tube MN2.

[0038] Specifically, the gate of the ninth PMOS tube MP3 is connected to the gate of the tenth PMOS tube MP4, the source of the ninth PMOS tube MP3 and the source of the tenth PMOS tube MP4 are connected to the output voltage VO, the gate of the ninth NMOS tube MN3 is also connected to its drain, the drain of the ninth NMOS tube MN3 is also connected to the drain of the eighth NMOS tube MN1, the source of the eighth NMOS is grounded, the gate of the eighth NMOS tube MN1 is connected to the third bias voltage Vbias0, the drain of the tenth PMOS tube MP4 is cascaded with the ninth NMOS tube MN3 and the tenth NMOS tube MN2 in sequence, the gate and drain of the ninth NMOS tube MN3 are connected to the gate of the common-gate input tube MN4, and the drain of the tenth NMOS tube MN2 is grounded.

[0039] Furthermore, in this embodiment, a filter circuit is also provided in the common-gate buffer Buffer, and the filter circuit includes a second resistor R2 and a first capacitor C1.

[0040] Specifically, both ends of the second resistor R2 are connected between the gates of the first NMOS transistor MN5 and the second NMOS transistor MN6, one end of the second resistor R2 connected to the first NMOS transistor MN5 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded.

[0041] The above filtering circuit reduces the high-frequency oscillation problem caused by the positive feedback loop, and makes the pole p2 have load adaptive characteristics, which can automatically adjust its position as the load changes and always remain outside the bandwidth. This adaptive characteristic ensures that the system can maintain good stability under different load conditions, and will not affect the signal transmission within the normal working frequency band, thereby maintaining a high response speed while ensuring system stability.

[0042] Please continue to refer to Figure 3 The voltage feedback circuit includes a power tube MP0 and a feedback network, wherein the gate of the power tube MP0 receives the driving signal VPGATE, the source is connected to the input voltage VIN, and the drain outputs the output voltage VO to the error amplifier EA; the feedback network divides the output voltage VO to obtain the feedback voltage Vfb, and the feedback voltage Vfb is input to the non-inverting input terminal of the error amplifier EA, wherein the drain of the power tube MP0 is connected to the feedback network to form a second connection node.

[0043] In a specific example, the feedback network includes a first feedback resistor Rf1 and a second feedback resistor Rf2. The connection point between the first feedback resistor Rf1 and the second feedback resistor Rf2 is the voltage dividing node, one end of the first feedback resistor Rf1 is connected to the drain of the power transistor MP0, and one end of the second feedback resistor Rf2 is grounded.

[0044] In this embodiment, an accurate voltage feedback path is established through the reasonable configuration of the power tube MP0 and the feedback network. The feedback network uses the first feedback resistor Rf1 and the second feedback resistor Rf2 to form a voltage divider structure, forming a stable voltage sampling system. The appropriate load effect can be provided through reasonable resistance configuration, which helps to improve the stability of the system.

[0045] For further information, please continue to refer to Figure 3 This embodiment further provides a compensation circuit, which includes: a first compensation capacitor Cc, a second compensation capacitor Cc' and a voltage-controlled switch S0.

[0046] Specifically, one end of the first compensation capacitor Cc is connected to the second connection node, and the other end is connected to the voltage divider node of the feedback network; one end of the voltage-controlled switch S0 is connected to one end of the first compensation capacitor Cc, and the other end is connected to one end of the second compensation capacitor Cc'; the other end of the second compensation capacitor Cc' is connected to the other end of the first compensation capacitor Cc.

[0047] In this embodiment, for the output stage, the feedback system composed of the first feedback resistor Rf1, the second feedback resistor Rf2, the first compensation capacitor Cc and the second compensation capacitor Cc' can generate a pair of zero poles z0 and p3 while obtaining the output voltage division, and the zero point leads the pole, which can provide a certain degree of compensation for the loop. Further, the compensation switch S0 is closed when the input voltage VIN is at a high level and is opened when it is at a low level, such as VIN=3.3 / 1.8V, which compensates for the problem of stability deterioration caused by the power supply switching between high and low.

[0048] In this embodiment, the low voltage drop linear regulator further includes a pull-down tube MN0, the gate of the pull-down tube MN0 is connected to the output end of the error amplifier EA, the source is grounded, and the drain inputs the output voltage VO into the error amplifier EA.

[0049] In this embodiment, the pull-down tube MN0 provides an additional pull-down path for the output stage, which solves the output overshoot problem when the load changes from heavy load to light load, and greatly improves the response speed of the circuit.

[0050] Furthermore, in the present embodiment, the tenth NMOS tube MN2 and the output pull-down tube MN0 are of the same type, so that the influence caused by different process angles and mismatch is greatly reduced, and the problem of excessive static current of the pull-down tube MN0 is solved.

[0051] Furthermore, in this embodiment, the low voltage dropout linear regulator further includes: an off-chip capacitor C0 and a parasitic resistor esr.

[0052] Specifically, one end of the parasitic resistor esr is connected to the second connection node, and the other end is connected to one end of the off-chip capacitor C0, and the other end of the off-chip capacitor C0 is grounded.

[0053] Furthermore, in this embodiment, the common-gate buffer Buffer further includes a first resistor R1 ; the first resistor R1 is connected in parallel between the drain and the source of the first PMOS transistor MP1 .

[0054] In this embodiment, the impedance formed by the parallel connection of the first resistor R1 and the first PMOS tube MP1 is relatively low compared to the common-source common-gate circuit composed of the common-gate input tube MN4, the first NMOS tube MN5 and the error amplifier EA output stage impedance. The gain of the input voltage VIN transmitted to the drive signal VPGATE is approximately 1, which offsets the disturbance of the input voltage VIN at the source end of the power tube MP0, thereby improving the power supply rejection ratio of the output stage where the power tube MP0 is located; and the error amplifier EA of the previous stage is internally powered, which can greatly improve the power supply rejection ratio from the input voltage VIN to the output voltage VO. In addition, under low-voltage operation, the power tube MP0 operates in the linear region, so that its gate terminal parasitic capacitance also increases, and the first resistor R1 can ensure the minimum value of the p2 pole generated at the VPGATE node.

[0055] It can be understood that the common-gate buffer stage disclosed in this embodiment is formed by connecting a positive feedback loop, a common-gate input tube MN4, a resistor R1 and a filter circuit. The output stage disclosed in this embodiment is formed by connecting a voltage feedback circuit, a compensation circuit, a pull-down tube MN0, an off-chip capacitor C0 and a parasitic resistor esr. It can be understood by those skilled in the art that the above-mentioned common-gate buffer stage and output stage can be designed according to actual conditions to meet the technical effects that can be achieved by this embodiment.

[0056] Furthermore, in the present embodiment, the error amplifier adopts a three-stage amplification structure: the differential input stage receives the feedback voltage Vfb and the reference voltage Vref, and realizes low-gain amplification and good common-mode suppression capability through the MOS diode; the second-stage common-source amplifier stage realizes the conversion from differential to single-ended and further improves the gain, and suppresses the common-mode interference such as the power supply of the differential input stage; the last-stage low-gain common-source amplifier stage realizes a lower gain to reduce the node impedance, so that the introduced pole is a high-frequency pole, which does not affect the loop stability.

[0057] In a specific embodiment, the differential input stage includes: a third PMOS transistor MP5, a fourth PMOS transistor MP6, a third NMOS transistor MN7, a fourth NMOS transistor MN8 and a fifth PMOS transistor MP7.

[0058] Specifically, the gates of the third PMOS tube MP5 and the fourth PMOS tube MP6 receive the feedback voltage Vfb and the reference voltage Vref respectively, and the sources are connected; the source of the fifth PMOS tube MP7 is connected to the output voltage VO, the drain is connected to the source of the third PMOS tube MP5 and the fourth PMOS tube MP6, and the gate is connected to the first bias voltage Vbias1; the sources of the third NMOS tube MN7 and the fourth NMOS tube MN8 are both grounded, and the drains of the third NMOS tube MN7 and the fourth NMOS tube MN8 are respectively connected to the third The drain of the PMOS tube MP5 is connected to the drain of the fourth PMOS tube MP6; wherein, the connection node after the drain of the third NMOS tube MN7 is connected to the drain of the third PMOS tube MP5 serves as the first output end of the differential input stage, the connection node after the drain of the fourth NMOS tube MN8 is connected to the drain of the fourth PMOS tube MP6 serves as the second output end of the differential input stage, and the gates of the third NMOS tube MN7 and the fourth NMOS tube MN8 are connected to the drains of the third NMOS tube MN7 and the fourth NMOS tube MN8, respectively.

[0059] In another specific embodiment, the error amplifier EA further includes a common source amplifier stage, and the common source amplifier stage includes: a sixth PMOS tube MP8, a fifth NMOS tube MN9, a seventh PMOS tube MP9 and a sixth NMOS tube MN10; The gates of the fifth NMOS transistor MN9 and the sixth NMOS transistor MN10 are respectively connected to the first output terminal and the second output terminal of the differential input stage, and the sources are both grounded; The sources of the sixth PMOS tube MP8 and the seventh PMOS tube MP9 are both connected to the output voltage VO, and the gates are interconnected. The drain of the sixth PMOS tube MP8 is connected to the drain of the fifth NMOS tube MN9, and the drain of the sixth PMOS tube MP8 is also connected to its gate; the drain of the seventh PMOS tube MP9 is connected to the drain of the sixth NMOS tube MN10.

[0060] In another specific embodiment, the low-gain common-source amplifier stage includes: an eighth PMOS transistor MP10 and a seventh NMOS transistor MN11.

[0061] The source of the eighth PMOS tube MP10 is connected to the output voltage VO, and the gate is connected between the drain of the seventh PMOS tube MP9 and the drain of the sixth NMOS tube MN10; the drain of the eighth PMOS tube MP10 is connected to the drain of the seventh NMOS tube MN11 and then outputs the control signal Vea; the source of the seventh NMOS tube MN11 is grounded, and the gate of the seventh NMOS tube MN11 is connected to the second bias voltage Vbias2.

[0062] In this embodiment, the design of the error amplifier EA achieves excellent power supply rejection characteristics. First, the error amplifier EA allows a lower input voltage VIN to be passed, thereby enhancing the compensation effect of the first compensation capacitor Cc and the second compensation capacitor Cc'. Secondly, a multi-stage offset mechanism is adopted to suppress the output voltage VO disturbance: in the differential input stage, the disturbance of the output voltage VO is converted into common-mode interference and offset in the common source amplifier stage; in the common source amplifier stage, the disturbance of the output voltage VO is directly offset by the disturbance at the source end of the eighth PMOS tube MP10 in the low-gain common source amplifier stage. In addition, due to the design of the internally powered error amplifier EA, not only the power supply rejection ratio of the output voltage VO to this stage is close to zero, but also because the output voltage VO itself has the ability to resist the interference of the external input voltage VIN, the immunity of the entire system to power supply disturbances is further enhanced.

[0063] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A low-dropout linear regulator with a wide voltage dropout range, characterized in that: include: An error amplifier EA, used for generating a control signal Vea; The common-gate buffer Buffer is powered by the input voltage VIN of the low-dropout linear regulator; The common-gate buffer Buffer includes a positive feedback loop, and the positive feedback loop is used to increase the slew rate of the control signal Vea and then output a driving signal VPGATE; The driving signal VPGATE is used to control the voltage feedback circuit to output the output voltage VO of the low-dropout linear regulator, and the output voltage VO is used to power the error amplifier EA.

2. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 1, characterized in that: The positive feedback loop includes: a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN5 and a second NMOS tube MN6; The sources of the first PMOS tube MP1 and the second PMOS tube MP2 are both connected to the input voltage VIN; the sources of the first NMOS tube MN5 and the second NMOS tube MN6 are both grounded, the drain of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN5 to form a first connection node, the first connection node outputs the driving signal VPGATE, the drain of the second PMOS tube MP2 is connected to the drain of the second NMOS tube MN6, the gates of the first NMOS tube MN5 and the second NMOS tube MN6 are connected; the gate of the second NMOS tube MN6 is also connected to the drain of the second NMOS tube MN6.

3. The low-voltage dropout linear regulator with a wide voltage dropout range as claimed in claim 2, characterized in that: The common-gate buffer Buffer also includes a first resistor R1; The first resistor R1 is connected in parallel between the drain and the source of the first PMOS transistor MP1.

4. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 2, characterized in that: The common-gate buffer Buffer also includes a common-gate input tube MN4; The gate of the common-gate input tube MN4 is connected to a bias voltage; the source of the common-gate input tube MN4 is connected to the drain of the first NMOS tube MN5, the output end VEA of the error amplifier EA is connected between the source of the common-gate input tube MN4 and the drain of the first NMOS tube MN5; the drain of the common-gate input tube MN4 is connected between the drain of the first PMOS tube MP1 and the drain of the first NMOS tube MN5.

5. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 2, characterized in that: The common-gate buffer Buffer further includes a filter circuit, and the filter circuit includes a second resistor R2 and a first capacitor C1; Two ends of the second resistor R2 are connected between the gates of the first NMOS transistor MN5 and the second NMOS transistor MN6, one end of the second resistor R2 connected to the first NMOS transistor MN5 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded.

6. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 1, characterized in that: The error amplifier EA includes a differential input stage, and the differential input stage includes: a third PMOS tube MP5, a fourth PMOS tube MP6, a third NMOS tube MN7, a fourth NMOS tube MN8 and a fifth PMOS tube MP7; The gates of the third PMOS transistor MP5 and the fourth PMOS transistor MP6 receive the feedback voltage Vfb and the reference voltage Vref respectively, and the sources are connected; The source of the fifth PMOS transistor MP7 is connected to the output voltage VO, the drain is connected to the sources of the third PMOS transistor MP5 and the fourth PMOS transistor MP6, and the gate is connected to the first bias voltage Vbias1; The sources of the third NMOS tube MN7 and the fourth NMOS tube MN8 are both grounded, and the drains of the third NMOS tube MN7 and the fourth NMOS tube MN8 are respectively connected to the drains of the third PMOS tube MP5 and the fourth PMOS tube MP6; wherein, the connection node after the drain of the third NMOS tube MN7 is connected to the drain of the third PMOS tube MP5 serves as the first output end of the differential input stage, the connection node after the drain of the fourth NMOS tube MN8 is connected to the drain of the fourth PMOS tube MP6 serves as the second output end of the differential input stage, and the gates of the third NMOS tube MN7 and the fourth NMOS tube MN8 are respectively connected to the drains of the third NMOS tube MN7 and the fourth NMOS tube MN8.

7. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 6, characterized in that: The error amplifier EA further includes a common source amplifier stage, which includes: a sixth PMOS tube MP8, a fifth NMOS tube MN9, a seventh PMOS tube MP9 and a sixth NMOS tube MN10; The gates of the fifth NMOS transistor MN9 and the sixth NMOS transistor MN10 are respectively connected to the first output terminal and the second output terminal of the differential input stage, and the sources are both grounded; The sources of the sixth PMOS tube MP8 and the seventh PMOS tube MP9 are both connected to the output voltage VO, and the gates are interconnected. The drain of the sixth PMOS tube MP8 is connected to the drain of the fifth NMOS tube MN9, and the drain of the sixth PMOS tube MP8 is also connected to its gate; the drain of the seventh PMOS tube MP9 is connected to the drain of the sixth NMOS tube MN10.

8. The low-dropout linear regulator with a wide voltage dropout range as claimed in claim 7, characterized in that: The error amplifier EA further includes a low-gain common-source amplifier stage, and the low-gain common-source amplifier stage includes: an eighth PMOS tube MP10 and a seventh NMOS tube MN11; The source of the eighth PMOS tube MP10 is connected to the output voltage VO, and the gate is connected between the drain of the seventh PMOS tube MP9 and the drain of the sixth NMOS tube MN10; the drain of the eighth PMOS tube MP10 is connected to the drain of the seventh NMOS tube MN11 and then outputs the control signal Vea; the source of the seventh NMOS tube MN11 is grounded, and the gate of the seventh NMOS tube MN11 is connected to the second bias voltage Vbias2.

9. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 6, characterized in that: The voltage feedback circuit includes a power tube MP0; The gate of the power transistor MP0 receives the driving signal VPGATE, the source is connected to the input voltage VIN, and the drain outputs the output voltage VO to the error amplifier EA.

10. The low-dropout linear regulator with a wide voltage dropout range as claimed in claim 9, characterized in that: The voltage feedback circuit also includes a feedback network; The feedback network divides the output voltage VO to obtain the feedback voltage Vfb, and the feedback voltage Vfb is input into the non-inverting input terminal of the error amplifier EA, wherein the drain of the power tube MP0 is connected to one end of the feedback network to form a second connection node.

11. The low-dropout linear regulator with a wide voltage dropout range as claimed in claim 10, characterized in that: It also includes a compensation circuit, which includes: a first compensation capacitor Cc, a second compensation capacitor Cc' and a voltage-controlled switch S0; One end of the first compensation capacitor Cc is connected to the second connection node, and the other end is connected to the voltage dividing node of the feedback network; One end of the voltage-controlled switch S0 is connected to one end of the first compensation capacitor Cc, and the other end is connected to one end of the second compensation capacitor Cc'; the other end of the second compensation capacitor Cc' is connected to the other end of the first compensation capacitor Cc.

12. The low-dropout linear regulator with a wide voltage dropout range as claimed in claim 11, characterized in that: It also includes a pull-down tube MN0, the gate of the pull-down tube MN0 is connected to the output end of the error amplifier EA, the source is grounded, and the drain inputs the output voltage VO into the error amplifier EA.

13. The low-dropout linear regulator with a wide voltage dropout range as claimed in claim 10, characterized in that: It also includes off-chip capacitance C0 and parasitic resistance esr; One end of the parasitic resistor esr is connected to the second connection node, and the other end is connected to one end of the off-chip capacitor C0 , and the other end of the off-chip capacitor C0 is grounded.

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