A static current control system for a double data rate linear regulator

Abstract

The application discloses a kind of static current control systems of double data rate linear voltage regulator, including reference generating circuit and by feedback control circuit, error amplifier circuit and power output circuit constitute idle power consumption control circuit, reference voltage VREF generated by reference generating circuit is exported to feedback control circuit, after feedback control circuit compares the control signal output by error amplifier circuit, exports to error amplifier circuit to make the control signal output by error amplifier circuit also change, the control signal in turn controls upper and lower power tube in power output circuit, by adjusting VREF generated by reference generating circuit, to flexibly adjust system idle power consumption, while considering low power consumption and the fast transient response of load switching.

Description

Technical Field

[0001] This invention relates to a double data rate linear regulator (DDR NMOS LDO) with an NMOS power transistor, and more particularly to a static current control system for the double data rate linear regulator. Background Technology

[0002] In recent years, with the rise of memory chips, more and more Double Data Rate (DDR) linear regulators (LDOs) have been widely used, such as DDR1, DDR2, DDR3, and DDR3L LDOs. Besides the difference in output voltage, they also differ in their corresponding output current. DDR LDOs differ from traditional LDOs primarily in their lower output voltage. For example, DDR1 has an output voltage of 1.25V, and other DDR LDOs have even lower voltages. This is because they supply power to digital memory chips, and with increasingly smaller feature sizes in manufacturing processes, the supply voltage is also decreasing; too high a voltage can easily burn out the chip. Secondly, unlike traditional LDOs, DDR LDOs can not only provide current (source current) but also sink current (sink current). As the memory chip continuously sends and receives data, the DDR LDO continuously draws sink and source current, greatly improving the data transfer rate.

[0003] A DDR NMOS LDO is a DDR LDO with NMOS power transistors. Its upper and lower power transistors are both NMOS transistors. In order to ensure the data transmission rate, both power transistors are turned on when there is no load. In this way, there is a normally open path between the drain of the upper transistor and the source of the lower transistor when there is no load. If this is not controlled, the no-load power consumption to ground will be very large. Therefore, how to control the current and balance the response speed and quiescent current is a problem we need to solve. Summary of the Invention

[0004] To address the trade-off between quiescent current and response speed in DDR NMOS LDOs under no-load conditions, this invention provides a quiescent current control system for a double data rate regulator (DDR NMOS LDO) with an NMOS power transistor. This system ensures both transient response speed and excellent control of quiescent current under no-load conditions, meeting the application requirements of high speed, high precision, and low power consumption for DDR LDOs.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is: a static current control system for a double data rate linear regulator, characterized in that: it includes a reference generation circuit and an idle power consumption control circuit;

[0006] The reference generation circuit includes PMOS transistors MP1 and MP2, NMOS transistor MN1, and current sources I1 and I2. The source and substrate of PMOS transistor MP1 and the source and substrate of PMOS transistor MP2 are both connected to VDD. The gate of PMOS transistor MP1 is interconnected with the gate of PMOS transistor MP2 and connected to the drain of PMOS transistor MP1 and the input terminals of current sources I1 and I2. The drain of PMOS transistor MP2 is connected to the drain and gate of NMOS transistor MN1 and generates a reference voltage VREF. The source and substrate of NMOS transistor MN1 and the output terminals of current sources I1 and I2 are all grounded to VSS.

[0007] The no-load power consumption control circuit includes a feedback control circuit, an error amplifier circuit, and a power output circuit connected in sequence:

[0008] The feedback control circuit includes PMOS transistors MP3~MP8 and NMOS transistors MN2 and MN3. The gates of PMOS transistors MP3 and MP6 are connected to a bias voltage VBIAS. The source and substrate of PMOS transistor MP3 are connected to VDD. The drain of PMOS transistor MP3 is connected to the source of PMOS transistors MP4 and MP5. The substrates of PMOS transistors MP4 and MP5 are connected to VDD. The drain of PMOS transistor MP6 is connected to the source of PMOS transistors MP7 and MP8. The substrates of MP7 and MP8 are both connected to VDD. The gate of MP7 is interconnected with the gate of MP5 and connected to the reference voltage VREF output by the reference generation circuit. The drain of MP7 is connected to the drain of MP5, as well as the drain and gate of NMOS MN2. The drain of MP8 is connected to the drain of MP4, as well as the drain and gate of NMOS MN3. The source and substrate of NMOS MN2 and the source and substrate of NMOS MN3 are both grounded to VSS.

[0009] The error amplifier circuit includes PMOS transistors MP9~MP13 and NMOS transistors MN4~MN9. The source and substrate of PMOS transistor MP9, the source and substrate of PMOS transistor MP12, and the source and substrate of PMOS transistor MP13 are all connected to VDD. The gates of PMOS transistors MP9, MP12, and MP13 are each connected to a bias voltage VBIAS. The drain of PMOS transistor MP9 is connected to the source of PMOS transistors MP10 and MP11. The substrates of PMOS transistors MP10 and MP11 are both connected to VDD. The gate of PMOS transistor MP10 is connected to VDD / 2. The drain of PMOS transistor MP10 is connected to the drain of NMOS transistors MN4, MN5, and MN8. The gate of NMOS transistor MN8 is connected to the drain of PMOS transistor MP12. The gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN6 and the drain and gate of NMOS transistor MN3 in the feedback control circuit. The drain of PMOS transistor MP11 is connected to the drain of NMOS transistor MN6, the drain and gate of NMOS transistor MN7, and the gate of NMOS transistor MN9. The drain of NMOS transistor MN9 is connected to the drain of PMOS transistor MP13. The source and substrate of NMOS transistor MN4, the source and substrate of NMOS transistor MN5, the source and substrate of NMOS transistor MN6, the source and substrate of NMOS transistor MN7, the source and substrate of NMOS transistor MN8, and the source and substrate of NMOS transistor MN9 are all grounded to VSS.

[0010] The power output circuit includes an upper-power NMOS transistor MN10 and a lower-power NMOS transistor MN11, as well as resistors R1 and R2. The drain of NMOS transistor MN10 is connected to the power supply VIN. The source and substrate of NMOS transistor MN10 are connected to the drain of NMOS transistor MN11, one end of resistor R1, and the gate of PMOS transistor MP11 in the error amplifier circuit. This connection is also the output terminal VOUT of the power output circuit. The gate of NMOS transistor MN10 is connected to the other end of resistor R1, the gate of PMOS transistor MP4 in the feedback control circuit, and the drain of PMOS transistor MP12 in the error amplifier. The gate of NMOS transistor MN11 is connected to one end of resistor R2, the gate of PMOS transistor MP8 in the feedback control circuit, and the drain of PMOS transistor MP13 in the error amplifier. The source and substrate of NMOS transistor MN10 are connected to the other end of resistor R2 and grounded to VSS.

[0011] In the reference generation circuit, I1 and I2 are current sources flowing through MP1. By mirroring the reference currents with positive and negative temperature coefficients respectively, I1 is obtained as a positive temperature coefficient current source and I2 as a negative temperature coefficient current source. Adjusting the mirroring ratio makes the current flowing through PMOS transistor MP1 after the superposition of I1 and I2 have a zero temperature coefficient. PMOS transistor MP2 mirrors the current of PMOS transistor MP1, and the current flowing through NMOS transistor MN1 is also a zero temperature coefficient current. The generated reference voltage VREF = VTHN + VOV, where VOV is the overdrive voltage of NMOS transistor MN1 and VTHN is the threshold voltage of NMOS transistor MN1. Changing the current magnitude and transistor size of NMOS transistor MN1 changes the magnitude of the reference voltage VREF. When the output voltage VOUT of the power output current is unloaded, the conduction current of the upper and lower power NMOS transistors MN10 and MN11 is effectively controlled, realizing the no-load power consumption of the control system, while also improving the transient response speed during load switching.

[0012] In the feedback control circuit, PMOS transistors MP3 and MP6 are current source loads, and PMOS transistors MP4 and MP5, as well as PMOS transistors MP7 and MP8, are differential pairs.

[0013] In the error amplifier circuit, PMOS transistors MP9, MP12, and MP13 are current source loads, and MP9 and MP10 are a differential pair.

[0014] The present invention has the following advantages and beneficial effects: In the application of DDR NMOS LDO, the no-load power consumption control circuit of the present invention can flexibly adjust the value of VREF, thereby flexibly adjusting the no-load power consumption of the system, taking into account the application characteristics of low power consumption and fast transient response during load switching. Attached Figure Description

[0015] Figure 1 Reference generation circuit;

[0016] Figure 2 This is a static (no-load) power consumption control circuit. Detailed Implementation

[0017] like Figure 1The reference generation circuit includes MP1, MP2, MN1, and current sources I1 and I2. I1 and I2 are current sources flowing through MP1. I1 is set as a positive temperature coefficient current source, and I2 is a negative temperature coefficient current source. These can be obtained by mirroring the current reference part. By adjusting the mirror ratio, the current flowing through the PMOS transistor MP1 after the superposition of I1 and I2 is approximately zero temperature coefficient. The PMOS transistor MP2 mirrors the current of the PMOS transistor MP1, and the current flowing through the NMOS transistor MN1 is also a zero temperature coefficient current. The generated reference voltage VREF = VTHN + VOV, where VOV is the overdrive voltage of the NMOS and VTHN is the threshold voltage of the NMOS. By adjusting the current and transistor size of the NMOS transistor MN1, the magnitude of the reference voltage VREF is changed. When the output voltage VOUT of the power output current is unloaded, the conduction current of the two power transistors MN10 and MN11 is effectively controlled, thereby realizing the no-load power consumption of the control system and improving the transient response speed during load switching.

[0018] like Figure 2 The no-load power consumption control circuit includes a feedback control circuit, an error amplifier circuit, and a power output circuit connected in sequence. The feedback control circuit includes MP3~MP8 and MN2 and MN3. MP3 and MP6 are bias current transistors, MP4, MP5, MP7, and MP8 are differential pairs, and MN2 and MN3 are current mirror loads. The error amplifier circuit includes MP9~MP13 and MN4~MN9. MP9, MP12, and MP13 are bias current transistors, MP10 and MP11 are differential pairs, MN5 and MN7 are current mirror loads, and MN4, MN6, MN8, and MN9 are current source loads. The power output circuit includes the upper power transistor MN10 and the lower power transistor MN11, as well as resistors R1 and R2.

[0019] Figure 2The working process of the no-load power consumption control circuit: The feedback control circuit receives the control signals Gate_top and Gate_bot output from the drain of the error amplifier circuits MP12 and MP13. After comparing them with VREF, the output signal controls the gates of the current source loads MN4 and MN6 of the error amplifier circuit, thereby changing the current flowing through them. MN4 and MN6 are connected in parallel with MN5 and MN7 respectively, thereby achieving the purpose of changing the current flowing through MN5 and MN7. The first stage of the error amplifier consists of the differential pair MP10 and MP11. Its gain is equal to the transconductance gmp of the differential pair MP10 / MP11 divided by the transconductance gmn (MN5 / MN7) of the current mirror load. Since gmn (MN5, MN7) is proportional to the current flowing through it, changes in the currents of MN5 and MN7 alter the gain of the first stage MP10 and MP11 in the error amplifier circuit. MN8 and MP12, and MN9 and MP13 form a common-source stage amplifier, causing changes in the Gate_top and Gate_bot outputs of the error amplifier circuit. These changes control the gates of the upper and lower power transistors MN10 and MN11 in the power output circuit. Ultimately, the LDO's output voltage VOUT stabilizes at VDD / 2. Under no-load conditions, Gate_top stabilizes at approximately one gate-source voltage VGS greater than VOUT, and Gate_bot stabilizes at approximately one VGS greater than VSS. The magnitude of the difference from VGS can be adjusted via VREF; the larger VREF is, the greater the magnitude. The larger the value of VREF, the greater the no-load power consumption, and the faster the transient response speed during the switching between light and heavy loads; the smaller the value of VREF, the smaller the no-load power consumption, and the slower the transient response speed during the switching between light and heavy loads. Therefore, a trade-off needs to be made between power consumption and speed. From the previous formula, we know that VREF = VTHN + VOV(MN1), where VTHN is the threshold voltage of MN1. Under the same process, MN1, MN10, and MN11 are all NMOS transistors. Under the same process and temperature, the threshold voltage of all NMOS transistors is the same, thus canceling out the influence of the threshold voltage. The no-load power consumption is only limited by the overdrive voltage of MN10 and MN11. When the width-to-length ratio of MN10 and MN11 is determined, the current flowing through them under no-load conditions is related to the overdrive voltage VOV of MN1. When the width-to-length ratio of MN1 is determined, the overdrive voltage of MN1 depends on the current flowing through MN1. Therefore, when the current of MN1 has a zero temperature coefficient, the no-load power consumption of the system is also approximately zero temperature coefficient.

Claims

1. A static current control system for a double data rate linear regulator, characterized in that: Includes a reference generation circuit and an idle power consumption control circuit; The reference generation circuit includes PMOS transistors MP1 and MP2, NMOS transistor MN1, and current sources I1 and I2. The source and substrate of PMOS transistor MP1 and the source and substrate of PMOS transistor MP2 are both connected to VDD. The gate of PMOS transistor MP1 is interconnected with the gate of PMOS transistor MP2 and connected to the drain of PMOS transistor MP1 and the input terminals of current sources I1 and I2. The drain of PMOS transistor MP2 is connected to the drain and gate of NMOS transistor MN1 and generates a reference voltage VREF. The source and substrate of NMOS transistor MN1 and the output terminals of current sources I1 and I2 are all grounded to VSS. The no-load power consumption control circuit includes a feedback control circuit, an error amplifier circuit, and a power output circuit connected in sequence: The feedback control circuit includes PMOS transistors MP3~MP8 and NMOS transistors MN2 and MN3. The gates of PMOS transistors MP3 and MP6 are connected to a bias voltage VBIAS. The source and substrate of PMOS transistor MP3 are connected to VDD. The drain of PMOS transistor MP3 is connected to the source of PMOS transistors MP4 and MP5. The substrates of PMOS transistors MP4 and MP5 are connected to VDD. The drain of PMOS transistor MP6 is connected to the source of PMOS transistors MP7 and MP8. The substrates of MP7 and MP8 are both connected to VDD. The gate of MP7 is interconnected with the gate of MP5 and connected to the reference voltage VREF output by the reference generation circuit. The drain of MP7 is connected to the drain of MP5, as well as the drain and gate of NMOS MN2. The drain of MP8 is connected to the drain of MP4, as well as the drain and gate of NMOS MN3. The source and substrate of NMOS MN2 and the source and substrate of NMOS MN3 are both grounded to VSS. The error amplifier circuit includes PMOS transistors MP9~MP13 and NMOS transistors MN4~MN9. The source and substrate of PMOS transistor MP9, the source and substrate of PMOS transistor MP12, and the source and substrate of PMOS transistor MP13 are all connected to VDD. The gates of PMOS transistors MP9, MP12, and MP13 are each connected to a bias voltage VBIAS. The drain of PMOS transistor MP9 is connected to the source of PMOS transistors MP10 and MP11. The substrates of PMOS transistors MP10 and MP11 are both connected to VDD. The gate of PMOS transistor MP10 is connected to VDD / 2. The drain of PMOS transistor MP10 is connected to the drain of NMOS transistors MN4, MN5, and MN8. The gate of NMOS transistor MN8 is connected to the drain of PMOS transistor MP12. The gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN6 and the drain and gate of NMOS transistor MN3 in the feedback control circuit. The drain of PMOS transistor MP11 is connected to the drain of NMOS transistor MN6, the drain and gate of NMOS transistor MN7, and the gate of NMOS transistor MN9. The drain of NMOS transistor MN9 is connected to the drain of PMOS transistor MP13. The source and substrate of NMOS transistor MN4, the source and substrate of NMOS transistor MN5, the source and substrate of NMOS transistor MN6, the source and substrate of NMOS transistor MN7, the source and substrate of NMOS transistor MN8, and the source and substrate of NMOS transistor MN9 are all grounded to VSS. The power output circuit includes an upper-power NMOS transistor MN10 and a lower-power NMOS transistor MN11, as well as resistors R1 and R2. The drain of NMOS transistor MN10 is connected to the power supply VIN. The source and substrate of NMOS transistor MN10 are connected to the drain of NMOS transistor MN11, one end of resistor R1, and the gate of PMOS transistor MP11 in the error amplifier circuit. This connection is also the output terminal VOUT of the power output circuit. The gate of NMOS transistor MN10 is connected to the other end of resistor R1, the gate of PMOS transistor MP4 in the feedback control circuit, and the drain of PMOS transistor MP12 in the error amplifier. The gate of NMOS transistor MN11 is connected to one end of resistor R2, the gate of PMOS transistor MP8 in the feedback control circuit, and the drain of PMOS transistor MP13 in the error amplifier. The source and substrate of NMOS transistor MN10 are connected to the other end of resistor R2 and grounded to VSS.

2. The static current control system for the double data rate linear regulator according to claim 1, characterized in that: In the reference generation circuit, I1 and I2 are current sources flowing through MP1. By mirroring the reference currents with positive and negative temperature coefficients respectively, I1 is obtained as a positive temperature coefficient current source and I2 as a negative temperature coefficient current source. Adjusting the mirroring ratio makes the current flowing through PMOS transistor MP1 after the superposition of I1 and I2 have a zero temperature coefficient. PMOS transistor MP2 mirrors the current of PMOS transistor MP1, and the current flowing through NMOS transistor MN1 is also a zero temperature coefficient current. The generated reference voltage VREF = VTHN + VOV, where VOV is the overdrive voltage of NMOS transistor MN1 and VTHN is the threshold voltage of NMOS transistor MN1. Changing the current magnitude and transistor size of NMOS transistor MN1 changes the magnitude of the reference voltage VREF. When the output voltage VOUT of the power output current is unloaded, the conduction current of the upper and lower power NMOS transistors MN10 and MN11 is effectively controlled, realizing the no-load power consumption of the control system, while also improving the transient response speed during load switching.

3. The static current control system for the double data rate linear regulator according to claim 1, characterized in that: In the feedback control circuit, PMOS transistors MP3 and MP6 are current source loads, and PMOS transistors MP4 and MP5, as well as PMOS transistors MP7 and MP8, are differential pairs.

4. The static current control system for the double data rate linear regulator according to claim 1, characterized in that: In the error amplifier circuit, PMOS transistors MP9, MP12, and MP13 are current source loads, and MP9 and MP10 are a differential pair.

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