Low dropout regulator and battery management system

Abstract

The invention provides a low dropout regulator and a power management system, and relates to the technical field of power management. The low dropout linear regulator comprises a power supply assembly, an operational amplifier module, a reference voltage module, a regulating module and a feedback module, wherein the regulating module at least comprises one NMOS (N-channel Metal Oxide Semiconductor) regulating tube. The power supply assembly is used for providing power supply voltage for the operational amplifier module, and the value of the power supply voltage is larger than the driving voltage value of the NMOS adjusting tube. The reference voltage module is used for providing reference voltage for the operational amplifier module; the feedback module is used for obtaining a first feedback voltage based on the output voltage of the voltage stabilizer; the operational amplifier module is used for generating a control signal according to the reference voltage and the output voltage so as to adjust the conduction degree of the NMOS adjusting tube. Based on this, the problem of balance among the output capability, stability and power consumption of the charge pump in the prior art can be improved, and the transient response speed and the low power consumption performance are considered at the same time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of voltage stabilizer, in particular to a low dropout linear voltage regulator and a battery management system. BACKGROUND

[0002] With the development of wearable devices, Internet of Things nodes and programmable sensors, battery management modules, such as low dropout linear voltage regulators (LDOs), are required to have good transient response capability in the case of low supply voltage and drastic load current changes, in order to ensure stable power supply and reliable system operation.

[0003] Most linear voltage regulator structures in the prior art use P-type metal oxide semiconductor (PMOS) as the adjustment tube. Although the device structure is simple and easy to implement, the response speed is limited when the load current changes rapidly, and it is difficult to meet the transient performance requirements. Although N-type metal oxide semiconductor (NMOS) can be used as a substitute, it can improve the driving speed to a certain extent, and thus has a higher response speed when the load changes suddenly. However, NMOS as an adjustment tube requires a gate drive voltage higher than the output voltage, and cannot directly obtain sufficient driving voltage from a conventional low-voltage system, resulting in that the NMOS type LDO is difficult to work stably, and even cannot be normally turned on.

[0004] Therefore, there is an urgent need for a linear voltage regulation scheme that can improve the balance between the charge pump output capability, stability and power consumption of the existing scheme, while taking into account the transient response speed and low power consumption performance. SUMMARY

[0005] Therefore, the present application aims to provide a low dropout linear voltage regulator and a battery management system that can improve the balance between the charge pump output capability, stability and power consumption of the existing scheme, while taking into account the transient response speed and low power consumption performance.

[0006] To achieve the above-mentioned purpose, the technical solutions adopted by the embodiments of the present application are as follows: In a first aspect, the present application provides a low dropout linear voltage regulator, which comprises a power supply component, an operational amplifier module, a reference voltage module, an adjustment module and a feedback module, wherein the adjustment module comprises at least one NMOS adjustment tube. The power supply component is connected to the power supply terminal of the operational amplifier module; the output terminal of the reference voltage module is connected to the first input terminal of the operational amplifier module; the output terminal of the feedback module is connected to the second input terminal of the operational amplifier module; the output terminal of the operational amplifier module is connected to the control terminal of the NMOS regulator; the first terminal of the NMOS regulator serves as the output terminal of the low dropout linear regulator and is connected to the input terminal of the feedback module. The power supply component is used to provide power supply voltage to the operational amplifier module. The power supply voltage value is greater than the drive voltage value of the NMOS regulating transistor. The reference voltage module is used to provide a reference voltage for the operational amplifier module; The feedback module is used to obtain the first feedback voltage based on the output voltage of the low-dropout linear regulator; The operational amplifier module is used to generate control signals based on the reference voltage and the first feedback voltage to adjust the conduction level of the NMOS regulator.

[0007] In a second aspect, the present invention also provides a battery management system, which includes the low-dropout linear regulator described in the first aspect.

[0008] The low-dropout linear regulator and battery management system provided in this invention have the following advantages: This application discloses a low-dropout linear regulator comprising: a power supply component, an operational amplifier module, a reference voltage module, an adjustment module, and a feedback module. The adjustment module includes at least one NMOS transistor. The power supply component provides a power supply voltage to the operational amplifier module, the power supply voltage being greater than the drive voltage of the NMOS transistor. The reference voltage module provides a reference voltage to the operational amplifier module. The feedback module obtains a first feedback voltage based on the output voltage. The operational amplifier module generates a control signal based on the reference voltage and the first feedback voltage to adjust the conduction level of the NMOS transistor. Based on this, the present invention provides a power supply component to the operational amplifier module, ensuring that the power supply voltage is greater than the input voltage of the NMOS transistor. This allows the NMOS transistor to conduct normally and operate efficiently under low-voltage power supply conditions. Furthermore, by combining the operational amplifier module, the reference voltage module, and the feedback module, a load transient enhancement mechanism is constructed, which effectively improves the circuit's response speed during large current surges while maintaining low static power consumption and high output stability. This makes it suitable for low-power applications with high requirements for power supply transient performance and energy efficiency.

[0009] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This invention provides a schematic diagram of one of the structures of a low-dropout linear regulator. Figure 2 This is a second schematic diagram of the low-dropout linear regulator provided in an embodiment of the present invention; Figure 3 One of the structural schematic diagrams of the power supply component provided in an embodiment of the present invention is shown; Figure 4 One of the structural schematic diagrams of the oscillation module provided in the embodiment of the present invention is shown; Figure 5 One of the circuit schematic diagrams of the oscillation module provided in an embodiment of the present invention is shown; Figure 6 This is a second schematic diagram of the structure of the oscillation module provided in an embodiment of the present invention; Figure 7 The second circuit schematic diagram of the oscillation module provided in the embodiment of the present invention is shown; Figure 8 The third schematic diagram of the oscillation module provided in this embodiment of the invention is shown; Figure 9 A schematic diagram of the structure of the D flip-flop provided in an embodiment of the present invention is shown; Figure 10 A schematic diagram of the charge pump circuit provided in an embodiment of the present invention is shown; Figure 11 A circuit diagram of a charge pump circuit provided in an embodiment of the present invention is shown; Figure 12 A simulation diagram of the capacitor voltage of the charge pump circuit provided in an embodiment of the present invention is shown; Figure 13 A schematic diagram of the voltage regulator circuit provided in an embodiment of the present invention is shown; Figure 14 A schematic diagram of the error amplification unit provided in an embodiment of the present invention is shown; Figure 15 The circuit schematic of the operational amplifier module provided in an embodiment of the present invention is shown; Figure 16 The transient output simulation diagram of the low dropout linear regulator provided in the embodiment of the present invention is shown.

[0012] Icons: 10 - Low dropout linear regulator; 101 - Power supply component; 102 - Operational amplifier module; 103 - Reference voltage module; 104 - Regulation module; 105 - Feedback module; 106 - Compensation module; 107 - Output filter module; 201 - Oscillation module; 202 - Charge pump circuit; 203 - Voltage regulator circuit; 301 - Oscillation start-up circuit; 302 - Feedback network; 303 - Multi-stage inverter; 304 - Adjustment unit; 305 - Error amplification unit; 306 - Feedback unit; 307 - Ring oscillator; 308 - Trigger unit; 401 - First stage amplifier circuit; 402 - Second stage amplifier circuit; 403 - Phase compensation circuit; 404 - Bias circuit; Cout - Output capacitor; Q1 - First switching transistor; Q2 - Second switching transistor; Q3 - Third switching transistor; Q4 - Fourth switching transistor; Q5 - Fifth switching transistor; Q6 - Sixth switching transistor; Q7 - Seventh switching transistor; Q8 - Eighth switching transistor; Q9 - Ninth switching transistor; Q10 - Tenth switching transistor; Q11 - Eleventh switching transistor; Q12 - Twelfth switching transistor; Q13 - Adjustment switching transistor; M1 - First MOSFET; M2 - Second MOSFET; M3 - Third MOSFET; M4 - Fourth MOSFET; M5 - Fifth MOSFET; M6 - Sixth MOSFET; MOSFETs; M7 - Seventh MOSFET; M8 - Eighth MOSFET; M9 - Ninth MOSFET; M10 - Tenth MOSFET; M11 - Eleventh MOSFET; M12 - Twelfth MOSFET; M13 - Thirteenth MOSFET; M14 - Fourteenth MOSFET; M15 - Fifteenth MOSFET; M16 - Sixteenth MOSFET; M17 - Seventeenth MOSFET; M18 - Eighteenth MOSFET; M19 - Nineteenth MOSFET; M20 - Twentieth MOSFET; M21 - Twenty-first MOSFET; M22 - Twenty-second MOSFET S-MOSFET; M23 - 23rd MOSFET; M24 - 24th MOSFET; M25 - 25th MOSFET; M26 - 26th MOSFET; M27 - 27th MOSFET; M28 - 28th MOSFET; M29 - 29th MOSFET; M30 - 30th MOSFET; C1 - 1st capacitor; C2 - 2nd capacitor; C3 - 3rd capacitor; C4 - 4th capacitor; C5 - 5th capacitor; C6 - 6th capacitor; C7 - 7th capacitor; C8 - 8th capacitor; DFF1 - 1st D flip-flop; DFF2 - 1st D flip-flop; Two-stage D flip-flops; TG1 - First transmission gate; TG2 - Second transmission gate; TG3 - Third transmission gate; INV1 - First inverter; INV2 - Second inverter; INV3 - Third inverter; INV4 - Fourth inverter; INV5 - Fifth inverter; INV6 - Sixth inverter; INV7 - Seventh inverter; NAND1 - First memory cell; NAND2 - Second memory cell; NAND3 - Third memory cell; NAND4 - Fourth memory cell; R1 - First resistor; R2 - Second resistor; R3 - Third resistor. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0014] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0015] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0016] The following description, in conjunction with the accompanying drawings, details a low-dropout linear regulator and battery management system provided in this application.

[0017] Please refer to Figure 1 , Figure 1 A schematic diagram of a low dropout linear regulator is shown. The low dropout linear regulator 10 includes: a power supply component 101, an operational amplifier module 102, a reference voltage module 103, an adjustment module 104, and a feedback module 105. The adjustment module 104 includes at least one NMOS regulator transistor.

[0018] In this embodiment, the power supply component 101 is connected to the power supply terminal of the operational amplifier module 102; the output terminal of the reference voltage module 103 is connected to the first input terminal of the operational amplifier module 102; the output terminal of the feedback module 105 is connected to the second input terminal of the operational amplifier module 102; the output terminal of the operational amplifier module 102 is connected to the control terminal of the NMOS regulator; the first terminal of the NMOS regulator serves as the output terminal of the low-dropout linear regulator 10 and is connected to the input terminal of the feedback module 105. The second terminal of the NMOS regulator is also used to receive the input voltage VDD. Simultaneously, the power supply component 101 and the reference voltage module 103 are also used to receive the input voltage VDD.

[0019] The power supply component 101 is used to provide a power supply voltage to the operational amplifier module, and the power supply voltage value is greater than the drive voltage value of the NMOS regulating transistor.

[0020] The reference voltage module 103 is used to provide a reference voltage for the operational amplifier module.

[0021] Feedback module 105 is used to obtain the first feedback voltage based on the output voltage of the low dropout linear regulator.

[0022] Operational amplifier module 102 is used to generate a control signal based on the reference voltage and the first feedback voltage to adjust the conduction level of the NMOS regulator.

[0023] In this embodiment, when the load changes abruptly, that is, when the output voltage VOUT of the low dropout linear regulator changes, the feedback module can feed back the voltage change to the operational amplifier module in real time, so that the operational amplifier module sends a control signal to the NMOS regulator to adjust the conduction degree of the NMOS regulator, thereby changing the output voltage and improving the transient response characteristics of the low dropout linear regulator.

[0024] Based on this, this embodiment provides a power supply component to the operational amplifier module, ensuring that the power supply voltage is greater than the input voltage of the NMOS regulator, enabling the NMOS regulator to conduct normally and operate efficiently under low-voltage power supply conditions. At the same time, a load transient enhancement mechanism is constructed by combining the operational amplifier module, the reference voltage module, and the feedback module, which can effectively improve the response speed of the circuit under large current changes. This is suitable for low-power application scenarios with high requirements for power supply transient performance and energy efficiency.

[0025] Please Figure 1 Based on, refer to Figure 2 , Figure 2 This diagram shows another structural schematic of the low-dropout linear regulator in this embodiment. The low-dropout linear regulator 10 also includes a compensation module 106, which is connected in parallel with the operational amplifier module 102 and is used to cooperate with the operational amplifier module 102 to compensate for the phase margin of the low-dropout linear regulator 10.

[0026] Please continue to refer to this. Figure 2 The low-dropout linear regulator 10 also includes an output filter module 107, which is located at the output terminal of the low-dropout linear regulator 10 and is used to filter the output voltage.

[0027] Based on this, the two-stage operational amplifier structure of the compensation module and the operational amplifier module in this embodiment can synergistically optimize the phase margin of the low-dropout linear regulator, enhance stability, and suppress oscillations. The output filter module 107 is used to filter the output voltage, reduce ripple, and improve response speed. In one possible implementation, the output filter module 107 may include an output capacitor Cout, with the first terminal of the output capacitor Cout connected to the first terminal of the NMOS regulating transistor; the second terminal of the output capacitor Cout is grounded.

[0028] Please Figure 1 Based on, refer to Figure 3 , Figure 3 A schematic diagram of the power supply component in this embodiment is shown. The power supply component 101 includes an oscillation module 201, a charge pump circuit 202, and a voltage regulator circuit 203 connected in sequence.

[0029] Oscillator module 201 is used to provide a clock signal to drive the charge pump.

[0030] The charge pump circuit 202 is used to obtain the initial power supply voltage based on the input voltage of the NMOS regulating transistor when it is in operation.

[0031] The voltage regulator circuit 203 is used to filter the initial power supply voltage to obtain the final power supply voltage to power the operational amplifier module.

[0032] In this embodiment, the oscillator is used to generate a high-frequency clock signal to drive the charge pump. The charge pump then increases the input voltage of the NMOS regulator and outputs a set of high-voltage signals, which are then stabilized and filtered by a voltage regulator circuit to output the power supply voltage to the operational amplifier module.

[0033] It should be noted that since this embodiment uses NMOS as the regulating transistor, a gate drive voltage higher than the input voltage, i.e., the aforementioned power supply voltage, can be provided by the power supply component, thereby enabling the NMOS regulating transistor in the low dropout linear regulator to conduct normally and operate efficiently under low voltage power supply conditions.

[0034] When the clock signal includes a four-phase interleaved signal, please Figure 3 Based on, refer to Figure 4 , Figure 4A schematic diagram of the oscillation module is shown. The oscillation module 201 includes a ring oscillator 307 and a trigger unit 308. The trigger unit 308 includes at least two cascaded D flip-flops. The output terminal of the ring oscillator 307 is connected to the input terminal of the trigger unit 308; the output terminal of the trigger unit 308 is connected to the input terminal of the charge pump circuit 202.

[0035] In this embodiment, the ring oscillator 307 is used to generate a clock signal when it is in operation.

[0036] The trigger unit 308 is used to divide the clock signal to obtain four phase-interleaved clock signals.

[0037] In one possible implementation, the ring oscillator may include an odd number of inverter stages, please refer to... Figure 4 Based on, refer to Figure 5 , Figure 5 The circuit diagram of a ring oscillator is shown, wherein the ring oscillator includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, a fifth switch Q5, and a sixth switch Q6.

[0038] The first terminal of the first switch Q1 is connected to the first terminals of the second switch Q2 and the third switch Q3, and serves as the first terminal of the ring oscillator; the first terminal of the fourth switch Q4 is connected to the first terminals of the fifth switch Q5 and the sixth switch Q6; the second terminal of the first switch Q1 is connected to the second terminal of the fourth switch Q4, the control terminal of the second switch Q2, and the control terminal of the fifth switch Q5; the second terminal of the second switch Q2 is connected to the second terminal of the fifth switch Q5, the control terminal of the third switch Q3, and the control terminal of the sixth switch Q6; the second terminal of the third switch Q3 is connected to the second terminal of the sixth switch Q6, and serves as the output terminal of the ring oscillator; the control terminal of the first switch Q1 is connected to the control terminal of the fourth switch Q4 and the output terminal of the ring oscillator.

[0039] In one possible implementation, in this embodiment, the first switch Q1, the second switch Q2, and the third switch Q3 are all NMOS transistors; the fourth switch Q4, the fifth switch Q5, and the sixth switch Q6 are all PMOS transistors. Based on this, in this embodiment, the odd-numbered stage inverters formed by the first switch Q1 to the sixth switch Q6 are used for self-oscillation to generate a clock signal. Each stage inverts and introduces a delay, enabling the output to form a stable oscillation signal.

[0040] Please Figure 5 Based on, refer to Figure 6 , Figure 6This diagram illustrates another structural schematic of the oscillation module in this embodiment. The oscillation module 201 further includes an oscillation start-up circuit 301, a feedback network 302, and a multi-stage inverter 303. The first terminal of the oscillation start-up circuit 301 is used to receive a first bias current idc, and the second terminal is connected to the first terminal of the feedback network 302. The third terminal of the oscillation start-up circuit 301 is connected to the first terminal of the ring oscillator 307. The second terminal of the feedback network 302 is connected to the second terminal of the ring oscillator 307. The output terminal of the ring oscillator 307 is connected to the input terminal of the multi-stage inverter 303. The output terminal of the multi-stage inverter 303 is connected to the first terminal of the trigger unit 308.

[0041] The oscillation circuit 301 is used to receive the first bias current idc to start the oscillation module; Feedback network 302 is used to send control signals to the ring oscillator and adjust the oscillation frequency of the oscillation module when the oscillation module is in operation. The multi-stage inverter 303 is used to receive and adjust the waveform of the clock signal to obtain the final clock signal. Please Figure 6 Based on, refer to Figure 7 , Figure 7 The circuit diagram of the oscillation module in this embodiment is shown; the oscillation circuit 301 includes a first MOSFET M1, a second MOSFET M2 and a first capacitor C1; the feedback network 302 includes a third MOSFET M3, a fourth MOSFET M4 and a second capacitor C2; the multi-stage inverter 303 includes a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10 and an eleventh MOSFET M11; the oscillation module 201 also includes a fifth MOSFET M5.

[0042] In this embodiment, the second terminal of the first MOSFET M1 is used to receive a constant first bias current idc. The control terminal of the first MOSFET M1 is connected to the first terminal of the first capacitor C1 and the control terminal of the second MOSFET M2. The second terminal of the second MOSFET M2 is connected to the first terminal of the third MOSFET M3 and the control terminal of the third MOSFET M3. The first terminal of the first MOSFET M1, the second terminal of the first capacitor C1, and the first terminal of the second MOSFET M2 are all grounded. Based on this, the oscillator can be started through the charging and discharging process of the first capacitor C1 in this embodiment.

[0043] Please continue to refer to this. Figure 7In this embodiment, the second terminal of the third MOSFET M3, the first terminal of the second capacitor C2, and the first terminal of the fourth MOSFET M4 are all used to receive the input voltage of the low-dropout linear regulator 10. The control terminal of the third MOSFET M3 is also connected to the control terminal of the fourth MOSFET M4 and the second terminal of the second capacitor C2. The second terminal of the fourth MOSFET M4 is also connected to the first terminal of the first switch Q1. Based on this, the third MOSFET M3, the fourth MOSFET M4, and the second capacitor C2 form a feedback network 302, which can maintain the oscillation of the oscillator, and the oscillation frequency of the oscillator can be adjusted through the second capacitor C2.

[0044] Please continue to refer to this. Figure 7 In this embodiment, the second terminal of the fifth MOSFET M5 is connected to the first terminal of the fourth switch Q4; the first terminal of the fifth MOSFET M5 is grounded; the control terminal of the fifth MOSFET M5 is also connected to the first terminal of the first capacitor C1 and is used to receive a constant first bias current idc, so that the oscillation module 201 can work normally when it is turned on, and the oscillation module 201 can stop working when it is turned off.

[0045] Please continue to refer to this. Figure 7 In this embodiment, the first terminals of the sixth MOSFET M6, the eighth MOSFET M8, and the tenth MOSFET M10 are all used to receive the input voltage of the low dropout linear regulator; the first terminals of the seventh MOSFET M7, the ninth MOSFET M9, and the eleventh MOSFET M11 are all grounded; the control terminal of the sixth MOSFET M6 is connected to the control terminal of the seventh MOSFET M7 and the second terminal of the seventh switch Q7; the second terminal of the sixth MOSFET M6 is connected to the second terminal of the seventh MOSFET M7, the control terminal of the eighth MOSFET M8, and the control terminal of the ninth MOSFET M9; the first terminal of the eighth MOSFET M8 is connected to the first terminal of the ninth MOSFET M9, the control terminal of the tenth MOSFET M10, and the control terminal of the eleventh MOSFET M11; the second terminal of the tenth MOSFET M10 is connected to the second terminal of the eleventh MOSFET M11 and the input terminal of the trigger unit 308.

[0046] Based on this, the multi-stage inverter 303 can shape the waveform of the clock signal to make it more square, thereby obtaining the final clock signal. It should be noted that this embodiment does not limit the number of stages of the multi-stage inverter 303, and its number of stages can be adjusted by the user.

[0047] In one possible implementation, a constant first bias current idc can be obtained from the reference voltage module 103, which enables the oscillation module 201 to operate in a stable state.

[0048] In this embodiment, the four-phase interleaved signals include a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4. When the phases of each clock signal are interleaved, please refer to [reference needed]. Figure 8 , Figure 8 This diagram shows another structural schematic of the oscillation module in this embodiment. In this embodiment, the trigger unit 308 includes a first D trigger DFF1 and a second D trigger DFF2, wherein the first D trigger DFF1 and the second D trigger DFF2 are cascaded.

[0049] Please refer to Figure 9 , Figure 9 The diagram shows the structure of the D flip-flop in this embodiment. The D flip-flop in this embodiment can be composed of a transmission gate, an inverter, and a NAND gate, specifically including: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate, a first memory cell NAND1, a second memory cell NAND2, a third memory cell NAND3, and a fourth memory cell NAND4. The specific connection relationships between the above structures can be found in [reference needed]. Figure 9 This will not be elaborated further in this embodiment.

[0050] exist Figure 9 Based on this, this embodiment also provides a principle for obtaining four-phase interleaved signals: Assuming the initial state of the first D flip-flop DFF1 is Q = 0 and Q̅ = 1, on the first rising edge, the first flip-flop transmits D = Q̅ = 1 to Q, resulting in Q = 1, while Q̅ = 0. On the second rising edge, the flip-flop transmits D = Q̅ = 0 to Q, resulting in Q = 0, while Q̅ = 1. After this cycle, the frequency of the signal at the Q input becomes half of the original clock input, i.e., CLK1 = CLK / 2; and Q̅ is complementary to Q, forming: .

[0051] Correspondingly, the clock input of the second D flip-flop DFF2 is the Q output of the first D flip-flop DFF1, i.e., CLK1. Assuming the initial state is Q=0 and Q̅=1, on the first rising edge, the flip-flop transmits D=Q̅=1 to Q, resulting in Q=1, while Q̅=0. On the second rising edge, the flip-flop transmits D=Q̅=0 to Q, resulting in Q=0, while Q̅=1. After this cycle repeats, the frequency of the signal at the Q terminal becomes half of CLK1, satisfying the following condition: Q̅ and Q are complementary, forming: .

[0052] Since the Q and Q̅ signals of the two-stage D flip-flops have a natural phase difference of 90°, after frequency division by two stages of the D flip-flops, four interleaved clock signals are finally obtained, namely the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4.

[0053] Please refer to Figure 10 , Figure 10 The diagram shows the structure of the charge pump circuit provided in this embodiment. In this embodiment, the charge pump circuit 202 includes multiple cascaded adjustment units 304. Each adjustment unit 304 corresponds to a clock signal, and the clock signals are phase-interleaved. Each adjustment unit 304 includes a switching transistor and a capacitor.

[0054] For any level adjustment unit 304, the first terminal of the switching transistor serves as the input terminal of the current level adjustment unit and is connected to the output terminal of the previous level adjustment unit; the first terminal of the switching transistor is also connected to the control terminal of the switching transistor; the second terminal of the switching transistor is connected to the first terminal of the capacitor and serves as the output terminal of the current level adjustment unit and the input terminal of the next level adjustment unit; the second terminal of the capacitor is used to receive the clock signal corresponding to the current level adjustment unit.

[0055] Among them, the charge pump circuit 202 is used to progressively increase the node voltage of each adjustment unit according to the clock signal.

[0056] In this embodiment, the output voltage of the charge pump circuit is expressed as: ; In the formula, This is the output voltage of the charge pump circuit; This is the input voltage of the low-dropout linear regulator; It is a high-level voltage; This is the threshold voltage of the switching transistor; n This refers to the number of stages in the adjustment unit of the charge pump circuit.

[0057] Please Figure 10 Based on, refer to Figure 11 , Figure 11The circuit diagram of the charge pump circuit provided in this embodiment is shown. When the charge pump circuit 202 is driven by four-phase interleaved signals (i.e., the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 mentioned above), the charge pump circuit 202 in this embodiment may include five cascaded adjustment units 304, namely, a twelfth MOSFET M12, a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, and a sixteenth MOSFET M16, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a seventh capacitor C7; wherein, the second terminal of the third capacitor C3 is used to receive the first clock signal CLK1; the second terminal of the fourth capacitor C4 is used to receive the second clock signal CLK2; the second terminal of the fifth capacitor C5 is used to receive the third clock signal CLK3; and the second terminal of the sixth capacitor C6 is used to receive the fourth clock signal CLK4. It should be noted that the seventh capacitor C7 serves as a filter capacitor, with its second terminal grounded; meanwhile, the second terminal of the sixteenth MOSFET M16 serves as the output terminal of the charge pump circuit 202.

[0058] Based on this, the working principle of the charge pump circuit 202 in this embodiment can be described as follows: Taking two interleaved clock signals as an example, when the first clock signal CLK1 is low and the second clock signal CLK2 is high, the gate potential of the twelfth MOSFET M12 is raised, and the drain potential of the twelfth MOSFET M12 is pulled low, making the twelfth MOSFET M12 in the conducting state and the thirteenth MOSFET M13 in the cutoff state. At this time, the input voltage VDD charges the third capacitor C3 through the twelfth MOSFET M12.

[0059] Ideally, the voltage across the third capacitor C3 should reach the input voltage VDD minus the threshold voltage of the NMOS transistor, i.e., the voltage across the third capacitor C3 should satisfy: VDD - Vthn. When the next clock cycle begins, the first clock signal CLK1 transitions from low to high, and the second clock signal CLK2 transitions from high to low. However, the nature of the capacitor dictates that the voltage across it cannot change abruptly. Therefore, the voltage across the third capacitor C3 increases as the first clock signal CLK1 rises. At this time, the twelfth MOS transistor M12 is cut off because its source potential is higher than its gate potential, while the thirteenth MOS transistor M13 is turned on under the influence of the low level of the second clock signal CLK2. This allows the voltage across the third capacitor C3 to charge the fourth capacitor C4 through the thirteenth MOS transistor M13, and the voltage across the fourth capacitor C4 can also reach 2VDD - Vthn. Through the alternating action of the first clock signal CLK1 and the second clock signal CLK2, the charge pump progressively increases the voltage at each node.

[0060] refer to Figure 12 ,Figure 12 The diagram shows a simulation of the capacitor voltage of the charge pump circuit provided in this embodiment. As can be seen, when the charge pump circuit 202 is driven by a four-phase interleaved signal, the voltage changes generated by each pump charge (third capacitor C3, fourth capacitor C4, fifth capacitor C5, and sixth capacitor C6) during the charge pump boosting process exhibit an interleaved rise and fall characteristic. The discharge voltage drops to the lowest value of the input voltage, while the charging voltage is superimposed through the clock signal. When the clock signal rises, the pump capacitor voltage is superimposed with the input voltage, thereby achieving a step-by-step voltage increase.

[0061] refer to Figure 13 , Figure 13 The schematic diagram of the voltage regulator circuit in this embodiment is shown. The voltage regulator circuit 203 includes an error amplification unit 305, an adjustment switch Q13, and a feedback unit 306. The first input terminal of the error amplification unit 305 is connected to the output terminal of the feedback unit 306. The second input terminal of the error amplification unit 305 is also used to receive a reference voltage. The output terminal of the error amplification unit 305 is connected to the control terminal of the adjustment switch Q13. The input terminal of the feedback unit 306 is connected to the second terminal of the adjustment switch Q13. The second terminal of the adjustment switch Q13 is also connected to the power supply terminal of the operational amplifier module 102. The first terminal of the adjustment switch Q13 is connected to the output terminal of the charge pump circuit 202.

[0062] Feedback unit 306 is used to acquire and obtain a second feedback voltage based on the output voltage of the voltage regulator circuit; The error amplification unit 305 is used to change the conduction degree of the regulating switch when the second feedback voltage is greater than or less than the reference voltage, so as to adjust the power supply voltage of the power supply component.

[0063] This embodiment does not limit the structure of the error amplification unit. In one possible implementation, to provide high gain, enhance output accuracy and dynamic response, the error amplification unit may consist of multiple differential pairs.

[0064] Please refer to Figure 14 , Figure 14 The diagram shows the structure of the error amplification unit in this embodiment. In this embodiment, the error amplification unit 305 includes a seventh switch Q7, an eighth switch Q8, a ninth switch Q9, a tenth switch Q10, an eleventh switch Q11, and a twelfth switch Q12.

[0065] The control terminal of the seventh switch Q7 is used to receive the reference voltage; the first terminal of the seventh switch Q7 is connected to the first terminal of the eighth switch Q8 and the second terminal of the eleventh switch Q11; the first terminal of the eleventh switch Q11 and the first terminal of the twelfth switch Q12 are grounded; the second terminal of the seventh switch Q7 is connected to the second terminal of the ninth switch Q9, the control terminal of the ninth switch Q9, and the control terminal of the tenth switch Q10; the first terminals of the ninth switch Q9 and the tenth switch Q10 are also used to receive the input voltage VDD of the low-dropout linear regulator 10; the second terminal of the tenth switch Q10 is connected to the control terminal of the adjustment switch Q13 and the second terminal of the eighth switch Q8; the control terminal of the eighth switch Q8 is connected to the output terminal of the feedback unit 306. The second terminal of the twelfth switch Q12 is used to receive the second bias current I and is connected to the control terminal of the eleventh switch Q11 and its own control terminal.

[0066] In one possible implementation, the second bias current I can be obtained from the reference voltage module 103 to enable the voltage regulator circuit to operate in a stable state.

[0067] Please continue to refer to this. Figure 14 When the feedback unit 306 includes two cascaded resistors, a first resistor R1 and a second resistor R2, the first end of the first resistor R1 is connected to the second end of the adjusting switch Q13, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the control terminal of the eighth switch Q8, and the second end of the second resistor R2 is grounded.

[0068] The error amplification unit 305 may also be equipped with a filter capacitor to filter the output voltage of the charge pump circuit 202, so as to further ensure the output stability of the error amplification unit.

[0069] In this embodiment, the error amplification unit 305 includes a biased five-transistor operational amplifier composed of the seventh switch Q7 to the twelfth switch Q12. The seventh switch Q7 receives a reference voltage and compares it with the voltage divider feedback network composed of the first resistor R1 and the second resistor R2. When the second feedback voltage is greater than or less than the reference voltage, the conduction degree of the adjustment switch Q13 inside the voltage regulator circuit 203 is adjusted until the second feedback voltage equals the reference voltage. Then, the feedback unit 306 adjusts the power supply voltage to obtain a value greater than the drive voltage value of the NMOS adjustment transistor, so as to provide a low-noise and high-stability power supply voltage for the subsequent operational amplifier module 102 and ensure its normal operation.

[0070] The same idea applies as the previous embodiment; please refer to [the previous embodiment]. Figure 15 , Figure 15The circuit schematic of the operational amplifier module in this embodiment is shown; the operational amplifier module 102 can be composed of two cascaded gain stages to achieve high gain, high output swing, and better driving capability. Please continue to refer to... Figure 15 The operational amplifier module 102 includes a first-stage amplifier circuit 401, a second-stage amplifier circuit 402, a phase compensation circuit 403, and a bias circuit 404.

[0071] The first-stage amplifier circuit uses a five-transistor differential pair structure with PMOS as the input transistor, namely, the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, the nineteenth MOS transistor M19, the twentieth MOS transistor M20, and the twenty-first MOS transistor M21. Among them, the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, and the twenty-first MOS transistor M21 are all PMOS transistors; the nineteenth MOS transistor M19 and the twentieth MOS transistor M20 are both NMOS transistors.

[0072] The second-stage amplifier circuit consists of the twenty-second MOSFET M22 and the twenty-third MOSFET M23. The phase compensation circuit consists of the thirtieth MOSFET M30 and the eighth capacitor C8.

[0073] Based on this, the voltage gain of the operational amplifier module 102 in this embodiment It can be represented as: ; In the formula, , These represent the p-channel length modulation coefficient and the n-channel length modulation coefficient, respectively. This is the gate-source voltage; This is the threshold voltage.

[0074] Based on this, the DC gain and overdrive voltage of the two-stage operational amplifier... It is inversely proportional to the channel length modulation coefficient λ. Since increasing the effective channel length L of the MOSFET will decrease the channel length modulation coefficient λ, a lower overdrive voltage and a larger channel length should be selected to achieve high gain.

[0075] In the first-stage amplifier circuit, the control terminal of the seventeenth switch can receive the first feedback voltage V. N The control terminal of the eighteenth switching transistor can receive a reference voltage V. P The comparison and judgment method can be referred to the working principle of the error amplification unit 305 in the above embodiment, which will not be repeated here.

[0076] In this embodiment, the second end of the third resistor R3 is connected to the control end of the operational amplifier module 102 as the output end of the NMOS regulator. That is, the control signal obtained by the operational amplifier module 102 is output to the NMOS regulator through the second end of the third resistor R3 to adjust the conduction degree of the NMOS regulator.

[0077] In this embodiment, the bias circuit is constructed using a common-source, common-gate Widlar current source structure, consisting of the third resistor R3 and MOSFETs M23 through M29. The 24th MOSFET M24 and the 25th MOSFET M25 have the same width-to-length ratio, while the width-to-length ratio of the 28th MOSFET M28 and the 29th MOSFET M29 is typically a multiple of each other. By introducing the third resistor R3, the bias circuit in this embodiment can form a micro-current source to generate a reference current. Meanwhile, the twenty-seventh MOSFET M27 and the twenty-eighth MOSFET M28 form a common source and common gate structure, which can not only reduce the current error caused by the channel length modulation effect, but also provide a bias voltage for the gate of the thirtieth MOSFET M30 to ensure the stable operation of the circuit.

[0078] Among them, the twenty-eighth MOSFET M28 and the twenty-ninth MOSFET M29 are intentionally mismatched transistors; a third resistor R3 is connected in series with the source of the twenty-eighth MOSFET M28 to set the bias current and adjust the transconductance of the twenty-eighth MOSFET M28; in order to reduce the channel length modulation effect of the twenty-eighth MOSFET M28, the twenty-sixth MOSFET M26 in the operational amplifier module 102 in this embodiment adopts a Cascode structure, and provides a stable bias voltage for the twenty-sixth MOSFET M26 and the thirtieth MOSFET M30 through connection M11.

[0079] The 24th MOSFET M24 and the 25th MOSFET M25 form a current mirror source, which replicates the reference current IQ to the 27th MOSFET M27 and the 29th MOSFET M29, while providing bias current to the 21st MOSFET M21 and the 23rd MOSFET M23, ensuring stable circuit operation.

[0080] Based on this, in this embodiment, the reference current The calculation formula can be expressed as: ; in, The aspect ratio of the twenty-eighth MOSFET M28; The aspect ratio of the twenty-ninth MOSFET M29; Let R3 be the resistance value of the third resistor. The carrier mobility; The capacitance per unit area of ​​the gate oxide layer; The connection relationships between the MOSFETs, resistors, and capacitors in this embodiment will not be described in detail here; please refer to [reference needed]. Figure 15 The connection relationship.

[0081] Based on this, in this embodiment, the operational amplifier module 102 can be composed of multiple differential pairs to provide high gain, enhance output accuracy and dynamic response, compare the reference voltage and the first feedback voltage, and generate control signals to adjust the conduction state of the NMOS switch to ensure the voltage regulation performance of the LDO.

[0082] In summary, this embodiment provides a low-dropout linear regulator based on an NMOS regulator. Compared with a PMOS transistor, the NMOS regulator has lower on-resistance and faster switching speed, thus enabling it to quickly provide current during load changes and reduce transient output voltage deviation. Furthermore, a charge pump circuit based on a four-phase interleaved charge pump structure is added to provide a power supply voltage greater than the drive voltage of the NMOS regulator, which further enhances the gate drive capability of the NMOS regulator and ensures that it can provide sufficient on-margin under low input voltage.

[0083] Meanwhile, a voltage regulator circuit is added to the output of the charge pump circuit to pre-regulate the output voltage of the charge pump circuit, further reducing the output ripple in the output voltage of the charge pump circuit and improving the stability of the drive voltage in the NMOS regulator, thereby avoiding the impact of gate voltage fluctuations in the NMOS regulator on the load capacity of the LDO.

[0084] Please refer to Figure 16 , Figure 16 The transient output simulation diagram of the low dropout linear regulator in this embodiment is shown. It can be seen that the low dropout linear regulator in this embodiment can start up within 10µs and stably output a voltage of 1.5V over a long period of time.

[0085] Similar to the previous embodiment, this embodiment also provides a battery management system, which includes the low dropout linear regulator of the first aspect described above. This system can improve the balance between charge pump output capability, stability and power consumption in existing solutions, while also taking into account transient response speed and low power consumption performance.

[0086] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0087] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0088] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0089] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-dropout linear regulator, characterized in that, The low dropout linear regulator includes: a power supply component, an operational amplifier module, a reference voltage module, an adjustment module, and a feedback module, wherein the adjustment module includes at least one NMOS regulating transistor; The power supply component is connected to the power supply terminal of the operational amplifier module; the output terminal of the reference voltage module is connected to the first input terminal of the operational amplifier module; the output terminal of the feedback module is connected to the second input terminal of the operational amplifier module; the output terminal of the operational amplifier module is connected to the control terminal of the NMOS regulating transistor; the first terminal of the NMOS regulating transistor serves as the output terminal of the low dropout linear regulator and is connected to the input terminal of the feedback module. The power supply component is used to provide a power supply voltage to the operational amplifier module, and the power supply voltage value is greater than the drive voltage value of the NMOS regulating transistor. The reference voltage module is used to provide a reference voltage for the operational amplifier module; The feedback module is used to obtain a first feedback voltage based on the output voltage of the low-dropout linear regulator. The operational amplifier module is used to generate a control signal based on the reference voltage and the first feedback voltage to adjust the conduction level of the NMOS regulating transistor.

2. The low-dropout linear regulator according to claim 1, characterized in that, The power supply component includes an oscillation module, a charge pump circuit, and a voltage regulator circuit connected in sequence. The oscillation module is used to provide a clock signal to drive the charge pump to operate; The charge pump circuit is used to obtain an initial power supply voltage based on the input voltage of the NMOS regulating transistor when it is in operation. The voltage regulator circuit is used to filter the initial power supply voltage to obtain the final power supply voltage, which is then used to power the operational amplifier module.

3. The low-dropout linear regulator according to claim 2, characterized in that, When the clock signal includes a four-phase interleaved signal, the oscillation module includes a ring oscillator and a trigger unit; the trigger unit includes at least two cascaded D flip-flops; The output terminal of the ring oscillator is connected to the input terminal of the trigger unit; the output terminal of the trigger unit is connected to the input terminal of the charge pump circuit. The ring oscillator is used to generate a clock signal when it is in operation; The trigger unit is used to divide the clock signal to obtain four phase-interleaved clock signals.

4. The low-dropout linear regulator according to claim 3, characterized in that, When the ring oscillator includes an odd number of inverters, the ring oscillator includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch. The first end of the first switching transistor is connected to the first ends of the second and third switching transistors, and serves as the first end of the ring oscillator; the first end of the fourth switching transistor is connected to the first ends of the fifth and sixth switching transistors; the second end of the first switching transistor is connected to the second end of the fourth switching transistor, the control end of the second switching transistor, and the control end of the fifth switching transistor; the second end of the second switching transistor is connected to the second end of the fifth switching transistor, the control end of the third switching transistor, and the control end of the sixth switching transistor; the second end of the third switching transistor is connected to the second end of the sixth switching transistor, and serves as the output end of the ring oscillator; the control end of the first switching transistor is connected to the control end of the fourth switching transistor and the output end of the ring oscillator.

5. The low-dropout linear regulator according to claim 4, characterized in that, The oscillation module further includes an oscillation start-up circuit, a feedback network, and a multi-stage inverter; the first terminal of the oscillation start-up circuit is used to receive a first bias current, the second terminal of the oscillation start-up circuit is connected to the first terminal of the feedback network, and the third terminal of the oscillation start-up circuit is connected to the first terminal of the ring oscillator; the second terminal of the feedback network is connected to the first terminal of the ring oscillator; the input terminal of the multi-stage inverter is connected to the output terminal of the ring oscillator; and the output terminal of the multi-stage inverter is connected to the first terminal of the trigger unit. The oscillation circuit is used to receive the first bias current and start the oscillation module. The feedback network is used to send control signals to the ring oscillator and adjust the oscillation frequency of the oscillation module when the oscillation module is in working state. The multi-stage inverter is used to receive and adjust the waveform of the clock signal to obtain the final clock signal.

6. The low-dropout linear regulator according to claim 2, characterized in that, The charge pump circuit includes multiple cascaded adjustment units; each adjustment unit corresponds to a clock signal, and the clock signals are phase-interleaved; each adjustment unit includes a switching transistor and a capacitor. For any level adjustment unit, the first terminal of the switching transistor serves as the input terminal of the current level adjustment unit and is connected to the output terminal of the previous level adjustment unit; the first terminal of the switching transistor is also connected to the control terminal of the switching transistor; the second terminal of the switching transistor is connected to the first terminal of the capacitor and serves as the output terminal of the current level adjustment unit and the input terminal of the next level adjustment unit; the second terminal of the capacitor is used to receive the clock signal corresponding to the current level adjustment unit. The charge pump circuit is used to progressively increase the node voltage of each adjustment unit according to the clock signal.

7. The low-dropout linear regulator according to claim 6, characterized in that, The output voltage of the charge pump circuit is expressed as: ； In the formula, This is the output voltage of the charge pump circuit; This is the input voltage of the low-dropout linear regulator; It is a high-level voltage; This is the threshold voltage of the switching transistor; n This refers to the number of stages in the adjustment unit of the charge pump circuit.

8. The low-dropout linear regulator according to claim 2, characterized in that, The voltage regulator circuit includes an error amplifier unit, an adjustment switch transistor, and a feedback unit. The first input terminal of the error amplifier unit is connected to the output terminal of the feedback unit. The second input terminal of the error amplifier unit is also used to receive a reference voltage. The output terminal of the error amplifier unit is connected to the control terminal of the adjustment switch transistor. The input terminal of the feedback unit is connected to the second terminal of the adjustment switch transistor. The second terminal of the adjustment switch transistor is also connected to the power supply terminal of the operational amplifier module. The first terminal of the adjustment switch transistor is connected to the output terminal of the charge pump circuit. The feedback unit is used to acquire and obtain a second feedback voltage based on the output voltage of the voltage regulator circuit; The error amplification unit is used to change the conduction degree of the adjustment switch when the second feedback voltage is greater than or less than the reference voltage, so as to adjust the power supply voltage of the power supply component.

9. The low-dropout linear regulator according to claim 8, characterized in that, The error amplification unit includes a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch. The control terminal of the seventh switch is used to receive a reference voltage; the first terminal of the seventh switch is connected to the first terminal of the eighth switch and the second terminal of the eleventh switch; the first terminal of the eleventh switch and the first terminal of the twelfth switch are grounded; the second terminal of the seventh switch is connected to the second terminal of the ninth switch, the control terminal of the ninth switch, and the control terminal of the tenth switch; the first terminals of the ninth and tenth switches are also used to receive the input voltage of the low-dropout linear regulator; the second terminal of the tenth switch is connected to the control terminal of the adjustment switch and the second terminal of the eighth switch; the control terminal of the eighth switch is connected to the output terminal of the feedback unit; the second terminal of the twelfth switch is used to receive a second bias current and is connected to the control terminal of the eleventh switch and its own control terminal.

10. A battery management system, characterized in that, The battery management system includes a low-dropout linear regulator as described in any one of claims 1 to 9.

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