A low dropout linear regulator with a wide differential pressure range

Abstract

The present invention discloses a low dropout linear regulator with a wide differential pressure range. Among them, the error amplifier is powered by the output voltage of the low dropout linear regulator, and the common-gate buffer is powered by the input voltage of the low dropout linear regulator, so that the direct interference path from the input voltage to the output only exists in the common-gate buffer stage and the output stage, improving the power supply rejection ratio. The common-gate buffer not only solves the margin loss brought by the traditional source follower circuit, but also the internally set positive feedback loop is used to increase the slew rate of the driving signal VPGATE and provide a certain gain, thus solving the margin problem under low dropout. The compensation circuit can also adjust the compensation amount of the low dropout linear regulator when the input voltage is higher than a preset threshold, improving the stability of the low dropout linear regulator under different working conditions.

Description

Technical Field

[0001] The present invention relates to the field of electronic power technology, and particularly to a low dropout linear regulator with a wide differential pressure range. Background Art

[0002] In modern electronic circuit designs, as the external application range of products expands, the requirement for the conversion efficiency of power modules is continuously increasing. A low dropout linear converter may not necessarily be able to maintain the ideal characteristic of a high output voltage under a wide range of input voltages and a wide range of load applications. A high differential pressure means that the power transistor operates in the saturation region, and only the wide application of the load needs to be solved; a low differential pressure makes the power transistor located in the linear region, which means a large power transistor area. Not only the load problem needs to be solved, but also the ability to suppress interference to the power supply and the stability under a wide load need to be addressed simultaneously. When the input application ranges of both are mixed together, it is difficult to design a circuit that can take both into account.

[0003] Please refer to Figure 1 , which is a schematic diagram of a traditional LDO. EA is an error amplifier for controlling the loop; M P0 is a power transistor for transmitting energy to the output; R f1 , R f2 are feedback resistors for sampling the output voltage; C o is the output capacitor. When high performance requirements for the output voltage are needed, it is often an off-chip capacitor, and esr is its parasitic resistance for stabilizing the output voltage.

[0004] When the differential pressure between the input and output is large, such as V IN = 3.3V, V O = 1.5V, M p0 operates in the saturation region. At this time, its transfer function is

[0005]

[0006] R load is the load resistor, g mp0 , r op0 are the transconductance and output impedance of M P0 , and H ea (s) is the transfer function of EA. And because the power transistor M P0 is often large in size, H ea (s) will have a low-frequency pole.

[0007] There are two low-frequency poles in the loop

[0008] );

[0009] ;

[0010] Among them, C1 is the EA output capacitor, including the parasitic capacitance of EA itself and the parasitic capacitance of the power transistor M P0 of the parasitic capacitance.

[0011] Since p0 only varies with the load and p1 is relatively fixed. When the load changes greatly, the relative positions of p0 and p1 change, and there are certain problems with the stability of the system. Therefore, a Buffer is introduced to push the p1 pole outwards, and p0 becomes the main pole of the system to provide appropriate phase margin and gain margin.

[0012] When there is a power supply perturbation, the input power supply perturbation under open loop can be well suppressed. The power supply rejection ratio is as follows

[0013] ;

[0014] Among them, the power supply rejection ratio PSR fd is the feedforward gain from V IN to the output voltage V o . Since the loop gain H loop_gain (s) is relatively large when the power transistor is in the saturation region, the power supply rejection ratio can be well suppressed.

[0015] When V IN continues to decrease, such as 1.8V, the power transistor M P0 enters the linear region, and r op0 behaves similarly to the load impedance under heavy load. Under low dropout voltage, to maintain a large power output, the size of the power transistor M P0 will become very large, and the parasitic capacitance of the power transistor in the linear region will also be more than twice that in the saturation region, and the p0 pole will move away from the origin.

[0016] Please refer to Figure 2 , at this time, for the compensation method when the power transistor is in the saturation region, due to the offset of the main pole, the additional pole generated by inserting the Buffer may enter the bandwidth, and the relative positions of the main and secondary poles may also change, deteriorating the loop stability. The loop gain H loop_gain (s) decreases, and the power supply rejection ratio deteriorates. If the main pole is set at the EA output terminal and the secondary pole is at the LDO output under low voltage, the stability under low voltage is improved. However, due to the existence of the off-chip capacitor and the change of the power transistor impedance under high voltage, the output terminal pole p0 will move towards the origin, and it is difficult to guarantee the stability under high voltage. Summary of the Invention

[0017] The purpose of the present invention is to provide a low dropout linear regulator with a wide voltage difference range, improve the power supply rejection ratio and circuit stability, and achieve fast transient response.

[0018] The present invention provides a low dropout linear regulator, comprising:

[0019] An error amplifier EA for generating a control signal Vea;

[0020] A common-gate buffer Buffer powered by the input voltage VIN of the low dropout linear regulator; the common-gate buffer Buffer includes a positive feedback loop for increasing the slew rate of the control signal Vea and then outputting a driving signal VPGATE;

[0021] The driving signal VPGATE is used to control the voltage feedback circuit to output the output voltage VO of the low dropout linear regulator, and the output voltage VO is used to power the error amplifier EA.

[0022] Further, the positive feedback loop includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN5, and a second NMOS transistor MN6;

[0023] The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the input voltage VIN; the sources of the first NMOS transistor MN5 and the second NMOS transistor MN6 are both grounded. The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN5 to form a first connection node, and the driving signal VPGATE is output from the first connection node. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN6, and the gates of the first NMOS transistor MN5 and the second NMOS transistor MN6 are connected; the gate of the second NMOS transistor MN6 is also connected to the drain of the second NMOS transistor MN6.

[0024] Further, the common-gate buffer Buffer further includes a first resistor R1; the first resistor R1 is connected in parallel between the drain and the source of the first PMOS transistor MP1.

[0025] Further, the common-gate buffer Buffer further includes a common-gate input transistor MN4;

[0026] The gate of the common-gate input transistor MN4 is connected to a bias voltage; the source of the common-gate input transistor MN4 is connected to the drain of the first NMOS transistor MN5, and the output terminal VEA of the error amplifier EA is connected between the source of the common-gate input transistor MN4 and the drain of the first NMOS transistor MN5; the drain of the common-gate input transistor MN4 is connected to the drain of the first PMOS transistor MP1.

[0027] Further, the common-gate buffer Buffer further includes a filtering circuit, and the filtering circuit includes a second resistor R2 and a first capacitor C1;

[0028] Both ends of the second resistor R2 are connected between the gates of the first NMOS transistor MN5 and the second NMOS transistor MN6. One end of the second resistor R2 connected to the first NMOS transistor MN5 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded.

[0029] Further, the error amplifier EA includes a differential input stage, and the differential input stage includes: a third PMOS transistor MP5, a fourth PMOS transistor MP6, a third NMOS transistor MN7, a fourth NMOS transistor MN8, and a fifth PMOS transistor MP7;

[0030] The gates of the third PMOS transistor MP5 and the fourth PMOS transistor MP6 respectively receive the feedback voltage Vfb and the reference voltage Vref, and their sources are connected;

[0031] The source of the fifth PMOS transistor MP7 is connected to the output voltage VO, the drain is connected to the sources of the third PMOS transistor MP5 and the fourth PMOS transistor MP6, and the gate is connected to a first bias voltage Vbias1;

[0032] The sources of the third NMOS transistor MN7 and the fourth NMOS transistor MN8 are both grounded. The drains of the third NMOS transistor MN7 and the fourth NMOS transistor MN8 are respectively connected to the drains of the third PMOS transistor MP5 and the fourth PMOS transistor MP6; wherein, the connection node after the drain of the third NMOS transistor MN7 is connected to the drain of the third PMOS transistor MP5 serves as the first output end of the differential input stage, and the connection node after the drain of the fourth NMOS transistor MN8 is connected to the drain of the fourth PMOS transistor MP6 serves as the second output end of the differential input stage. The gates of the third NMOS transistor MN7 and the fourth NMOS transistor MN8 are respectively connected to the drains of the third NMOS transistor MN7 and the fourth NMOS transistor MN8.

[0033] Further, the error amplifier EA further includes a common-source amplification stage, and the common-source amplification stage includes: a sixth PMOS transistor MP8, a fifth NMOS transistor MN9, a seventh PMOS transistor MP9, and a sixth NMOS transistor MN10;

[0034] The gates of the fifth NMOS transistor MN9 and the sixth NMOS transistor MN10 are respectively connected to the first output end and the second output end of the differential input stage, and their sources are both grounded;

[0035] The sources of the sixth PMOS transistor MP8 and the seventh PMOS transistor MP9 are both connected to the output voltage VO, and their gates are interconnected. The drain of the sixth PMOS transistor MP8 is connected to the drain of the fifth NMOS transistor MN9, and the drain of the sixth PMOS transistor MP8 is also connected to its gate; the drain of the seventh PMOS transistor MP9 is connected to the drain of the sixth NMOS transistor MN10.

[0036] Further, the error amplifier EA further includes a low-gain common-source amplification stage, and the low-gain common-source amplification stage includes: an eighth PMOS transistor MP10 and a seventh NMOS transistor MN11;

[0037] The source of the eighth PMOS transistor MP10 is connected to the output voltage VO, and the gate is connected between the drain of the seventh PMOS transistor MP9 and the drain of the sixth NMOS transistor MN10; the drain of the eighth PMOS transistor MP10 is connected to the drain of the seventh NMOS transistor MN11 and then outputs the control signal Vea; the source of the seventh NMOS transistor MN11 is grounded, and the gate of the seventh NMOS transistor MN11 is connected to the second bias voltage Vbias2.

[0038] Further, the voltage feedback circuit includes a power transistor MP0;

[0039] The gate of the power transistor MP0 receives the driving signal VPGATE, the source is connected to the input voltage VIN, and the drain outputs the output voltage VO to the error amplifier EA;

[0040] Further, the voltage feedback circuit includes a feedback network;

[0041] The feedback network divides the output voltage VO to obtain the feedback voltage Vfb, and the feedback voltage Vfb is input to the non-inverting input terminal of the error amplifier EA. Among them, the drain of the power transistor MP0 is connected to one end of the feedback network to form a second connection node.

[0042] Further, a compensation circuit is further included, and the compensation circuit includes: a first compensation capacitor Cc, a second compensation capacitor Cc', and a voltage-controlled switch S0;

[0043] One end of the first compensation capacitor Cc is connected to the second connection node, and the other end is connected to the voltage-dividing node of the feedback network;

[0044] One end of the voltage-controlled switch S0 is connected to one end of the first compensation capacitor Cc, and the other end is connected to one end of the second compensation capacitor Cc'; the other end of the second compensation capacitor Cc' is connected to the other end of the first compensation capacitor Cc.

[0045] Further, it further includes a pull-down tube MN0. The gate of the pull-down tube MN0 is connected to the output terminal of the error amplifier EA, the source is grounded, and the drain inputs the output voltage VO into the error amplifier EA.

[0046] Further, it further includes an off-chip capacitor C0 and a parasitic resistance esr;

[0047] One end of the parasitic resistance esr is connected to the second connection node, the other end is connected to one end of the off-chip capacitor C0, and the other end of the off-chip capacitor C0 is grounded.

[0048] Compared with the prior art, the present invention has at least the following technical effects:

[0049] The error amplifier disclosed in the present invention is powered by the output voltage of a low dropout linear regulator, and the common-gate buffer is powered by the input voltage of the low dropout linear regulator, so that the direct interference path from the input voltage to the output only exists in the common-gate buffer stage and the output stage, improving the power supply rejection ratio. The common-gate buffer not only solves the margin loss brought by the traditional source follower circuit, but also the internally set positive feedback loop does not introduce additional poles within the bandwidth, solving the margin problem under low dropout, and improving the stability of the low dropout linear regulator under different working conditions. Description of the Drawings

[0050] Figure 1 It is a schematic circuit diagram of an LDO in the prior art;

[0051] Figure 2 It is a schematic circuit diagram of a buffer-stage LDO in the prior art;

[0052] Figure 3 It is a schematic circuit diagram of the low dropout linear regulator disclosed in the present invention;

[0053] Figure 4 It is a schematic circuit diagram of the common-gate buffer Buffer disclosed in the present invention;

[0054] Figure 5 It is a schematic circuit diagram of the error amplifier EA disclosed in the present invention. Detailed Embodiments

[0055] The following will describe a low dropout linear regulator with a wide voltage difference range of the present invention in conjunction with the schematic diagrams, in which the preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as a broad guidance for those skilled in the art and not as a limitation to the present invention.

[0056] The present invention will be described more specifically by way of example with reference to the accompanying drawings in the following paragraphs. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0057] Please refer to Figures 3 - 5 , this embodiment discloses a low dropout linear regulator with a wide voltage difference range. The low dropout linear regulator with a wide voltage difference range includes:

[0058] An error amplifier EA for generating a control signal Vea; a common-gate buffer Buffer powered by the input voltage VIN of the low dropout linear regulator; the common-gate buffer Buffer includes a positive feedback loop for increasing the slew rate of the control signal Vea and then outputting a drive signal VPGATE. The drive signal VPGATE is used to control the voltage feedback circuit to output the output voltage VO of the low dropout linear regulator, and the output voltage VO is used to power the error amplifier EA.

[0059] In this embodiment, the error amplifier EA is powered by the output voltage VO of the low dropout linear regulator, and the common-gate buffer Buffer is powered by the input voltage VIN of the low dropout linear regulator, so that the direct interference path of the input voltage VIN to the output only exists in the common-gate buffer stage and the output stage. The power supply rejection ratio (PSR) is improved. In addition, the common-gate buffer Buffer not only solves the margin loss brought by the traditional source follower circuit, but also does not introduce additional poles within the bandwidth due to the internally set positive feedback loop, solves the margin problem under low dropout, and improves the stability of the low dropout linear regulator under different working conditions.

[0060] In this embodiment, please refer to Figure 4 , the positive feedback loop includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN5, and a second NMOS transistor MN6.

[0061] Specifically, the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the input voltage VIN; the sources of the first NMOS transistor MN5 and the second NMOS transistor MN6 are both grounded. The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN5 to form a first connection node, and the drive signal VPGATE is output from the first connection node. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN6, and the gates of the first NMOS transistor MN5 and the second NMOS transistor MN6 are connected; the gate of the second NMOS transistor MN6 is also connected to the drain of the second NMOS transistor MN6.

[0062] In this embodiment, the positive feedback formed by the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN5, and the second NMOS transistor MN6 has high sensitivity to the control signal Vea output by the error amplifier EA, thereby increasing the gain from the control signal Vea to the drive signal VPGATE and effectively compensating for the low-gain problem caused by the main pole being located at the output. At the same time, the buffer is powered by the input voltage VIN, and the error amplifier EA is powered by the output voltage VO, so that the interference path of the input voltage VIN to the output only exists in the common-gate buffer stage and the output stage, thereby improving the power supply rejection ratio.

[0063] Preferably, in order to further increase the response ability of the loop, this embodiment sets the aspect ratios of the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN5, and the second NMOS transistor MN6 to 1:1.

[0064] Further, in this embodiment, the common-gate buffer Buffer further includes a common-gate input transistor MN4.

[0065] Specifically, the gate of the common-gate input transistor MN4 is connected to a bias voltage; the source of the common-gate input transistor MN4 is connected to the drain of the first NMOS transistor MN5, and the output terminal VEA of the error amplifier EA is connected between the source of the common-gate input transistor MN4 and the drain of the first NMOS transistor MN5; the drain of the common-gate input transistor MN4 is connected to the drain of the first PMOS transistor MP1.

[0066] In this embodiment, the common-gate input transistor MN4 replaces the traditional source-follower bias, reducing the margin loss and the area.

[0067] In a specific example, the bias voltage is generated by a bias circuit so that the common-gate input transistor MN4 can operate at an appropriate operating point. Please continue to refer to Figure 4 , the bias circuit includes a ninth PMOS transistor MP3, a tenth PMOS transistor MP4, an eighth NMOS transistor MN1, a ninth NMOS transistor MN3, and a tenth NMOS transistor MN2.

[0068] Specifically, the gate of the ninth PMOS transistor MP3 is connected to the gate of the tenth PMOS transistor MP4. The sources of the ninth PMOS transistor MP3 and the tenth PMOS transistor MP4 are connected to the output voltage VO. The gate of the ninth PMOS transistor MP3 is also connected to its drain. The drain of the ninth PMOS transistor MP3 is also connected to the drain of the eighth NMOS transistor MN1. The source of the eighth NMOS transistor MN1 is grounded, and the gate of the eighth NMOS transistor MN1 is connected to the third bias voltage Vbias0. The drain of the tenth PMOS transistor MP4 is cascaded with the ninth NMOS transistor MN3 and the tenth NMOS transistor MN2 in sequence. After the gate and drain of the ninth NMOS transistor MN3 are connected, they are connected to the gate of the common-gate input transistor MN4. The drain of the tenth NMOS transistor MN2 is grounded.

[0069] Further, in this embodiment, a filtering circuit is also provided in the common-gate buffer Buffer. The filtering circuit includes a second resistor R2 and a first capacitor C1.

[0070] Specifically, both ends of the second resistor R2 are connected between the gates of the first NMOS transistor MN5 and the second NMOS transistor MN6. One end of the second resistor R2 connected to the first NMOS transistor MN5 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded.

[0071] The above filtering circuit reduces the high-frequency oscillation problem caused by the positive feedback loop, and enables the pole p2 to have a load adaptive characteristic, which can automatically adjust its position with the change of the load and always remain outside the bandwidth. This adaptive characteristic ensures that the system can maintain good stability under different load conditions, and at the same time does not affect the signal transmission in the normal working frequency band, thus maintaining a high response speed while ensuring the stability of the system.

[0072] Please continue to refer to Figure 3 , the voltage feedback circuit includes a power transistor MP0 and a feedback network. The gate of the power transistor MP0 receives the drive signal VPGATE, the source is connected to the input voltage VIN, and the drain outputs the output voltage VO to the error amplifier EA. The feedback network divides the output voltage VO to obtain the feedback voltage Vfb, and the feedback voltage Vfb is input to the non-inverting input terminal of the error amplifier EA. Among them, the drain of the power transistor MP0 is connected to the feedback network to form a second connection node.

[0073] In a specific example, the feedback network includes a first feedback resistor Rf1 and a second feedback resistor Rf2. The connection point of the first feedback resistor Rf1 and the second feedback resistor Rf2 is the voltage division node. One end of the first feedback resistor Rf1 is connected to the drain of the power transistor MP0, and one end of the second feedback resistor Rf2 is grounded.

[0074] In this embodiment, through the reasonable configuration of the power transistor MP0 and the feedback network, an accurate voltage feedback path is established. The feedback network uses the first feedback resistor Rf1 and the second feedback resistor Rf2 to form a voltage division structure, forming a stable voltage sampling system. By reasonable resistance value configuration, appropriate load effects can be provided, which helps to improve the stability of the system.

[0075] Further, please continue to refer to Figure 3 This embodiment also provides a compensation circuit, which includes: a first compensation capacitor Cc, a second compensation capacitor Cc', and a voltage-controlled switch S0.

[0076] Specifically, one end of the first compensation capacitor Cc is connected to the second connection node, and the other end is connected to the voltage division node of the feedback network; one end of the voltage-controlled switch S0 is connected to one end of the first compensation capacitor Cc, and the other end is connected to one end of the second compensation capacitor Cc'; the other end of the second compensation capacitor Cc' is connected to the other end of the first compensation capacitor Cc.

[0077] In this embodiment, for the output stage, the feedback system composed of the first feedback resistor Rf1, the second feedback resistor Rf2, the first compensation capacitor Cc, and the second compensation capacitor Cc' can generate a pair of zero-poles z0, p3 while obtaining the output voltage division, and the zero-point is ahead of the pole-point, which can provide a certain degree of compensation for the loop. Further, the compensation switch S0 is closed when the input voltage VIN is at a high level and opened when it is at a low level. For example, when VIN = 3.3 / 1.8V, it compensates for the problem of deteriorated stability caused by the switching of the power supply between high and low levels.

[0078] In this embodiment, the low-dropout linear regulator further includes a pull-down transistor MN0. The gate of the pull-down transistor MN0 is connected to the output terminal of the error amplifier EA, the source is grounded, and the drain inputs the output voltage VO into the error amplifier EA.

[0079] In this embodiment, the pull-down transistor MN0 provides an additional pull-down path for the output stage, solves the problem of output overshoot when the load jumps from heavy load to light load, and greatly improves the response speed of the circuit.

[0080] Further, in this embodiment, the tenth NMOS transistor MN2 and the output pull-down transistor MN0 are of the same type, greatly reducing the influence caused by different process corners and mismatches, and solving the problem of excessive static current of the pull-down transistor MN0.

[0081] Furthermore, in this embodiment, the low-dropout linear regulator further includes: an off-chip capacitor C0 and a parasitic resistance esr.

[0082] Specifically, one end of the parasitic resistance esr is connected to the second connection node, and the other end is connected to one end of the off-chip capacitor C0, and the other end of the off-chip capacitor C0 is grounded.

[0083] Furthermore, in this embodiment, the common-gate buffer Buffer further includes a first resistor R1; the first resistor R1 is connected in parallel between the drain and the source of the first PMOS transistor MP1.

[0084] In this embodiment, the impedance formed by the parallel connection of the first resistor R1 and the first PMOS transistor MP1 is relatively low compared to the cascode circuit composed of the common-gate input transistor MN4, the first NMOS transistor MN5, and the output-stage impedance of the error amplifier EA. The gain of the input voltage VIN transmitted to the driving signal VPGATE is approximately 1, which cancels out the perturbation of the input voltage VIN at the source end of the power transistor MP0, thereby improving the power supply rejection ratio of the output stage where the power transistor MP0 is located; and the previous-stage error amplifier EA is internally powered, which can greatly improve the power supply rejection ratio from the input voltage VIN to the output voltage VO. In addition, under low-voltage operation, the power transistor MP0 operates in the linear region, making its gate parasitic capacitance also increase, and the first resistor R1 can ensure the minimum value of the p2 pole generated at the VPGATE node.

[0085] It can be understood that the common-gate buffer stage disclosed in this embodiment is connected by a positive feedback loop, a common-gate input transistor MN4, a resistor R1, and a filter circuit. The output stage disclosed in this embodiment is connected by a voltage feedback circuit, a compensation circuit, a pull-down transistor MN0, an off-chip capacitor C0, and a parasitic resistance esr. Those skilled in the art can understand that the above common-gate buffer stage and output stage can be designed according to actual situations to meet the technical effects that can be achieved in this embodiment.

[0086] Furthermore, in this embodiment, the error amplifier adopts a three-stage amplification structure: the differential input stage receives the feedback voltage Vfb and the reference voltage Vref, and realizes low-gain amplification and good common-mode rejection ability through a MOS diode; the second-stage common-source amplification stage realizes the conversion from differential to single-ended and further improves the gain, and suppresses common-mode interferences such as the power supply of the differential input stage; the last-stage low-gain common-source amplification stage realizes a lower gain to reduce the node impedance, so that the introduced pole is a high-frequency pole and does not affect the loop stability.

[0087] In a specific embodiment, the differential input stage includes: a third PMOS transistor MP5, a fourth PMOS transistor MP6, a third NMOS transistor MN7, a fourth NMOS transistor MN8, and a fifth PMOS transistor MP7.

[0088] Specifically, the gates of the third PMOS transistor MP5 and the fourth PMOS transistor MP6 respectively receive the feedback voltage Vfb and the reference voltage Vref, and their sources are connected; the source of the fifth PMOS transistor MP7 is connected to the output voltage VO, the drain is connected to the sources of the third PMOS transistor MP5 and the fourth PMOS transistor MP6, and the gate is connected to the first bias voltage Vbias1; the sources of the third NMOS transistor MN7 and the fourth NMOS transistor MN8 are both grounded, and the drains of the third NMOS transistor MN7 and the fourth NMOS transistor MN8 are respectively connected to the drains of the third PMOS transistor MP5 and the fourth PMOS transistor MP6; wherein, the connection node after connecting the drain of the third NMOS transistor MN7 to the drain of the third PMOS transistor MP5 serves as the first output terminal of the differential input stage, the connection node after connecting the drain of the fourth NMOS transistor MN8 to the drain of the fourth PMOS transistor MP6 serves as the second output terminal of the differential input stage, and the gates of the third NMOS transistor MN7 and the fourth NMOS transistor MN8 are respectively connected to their drains.

[0089] In another specific embodiment, the error amplifier EA further includes a common-source amplification stage, and the common-source amplification stage includes: a sixth PMOS transistor MP8, a fifth NMOS transistor MN9, a seventh PMOS transistor MP9, and a sixth NMOS transistor MN10;

[0090] The gates of the fifth NMOS transistor MN9 and the sixth NMOS transistor MN10 are respectively connected to the first output terminal and the second output terminal of the differential input stage, and their sources are both grounded;

[0091] The sources of the sixth PMOS transistor MP8 and the seventh PMOS transistor MP9 are both connected to the output voltage VO, the gates are interconnected, the drain of the sixth PMOS transistor MP8 is connected to the drain of the fifth NMOS transistor MN9, and the drain of the sixth PMOS transistor MP8 is also connected to its gate; the drain of the seventh PMOS transistor MP9 is connected to the drain of the sixth NMOS transistor MN10.

[0092] In another specific embodiment, the low-gain common-source amplification stage includes: an eighth PMOS transistor MP10 and a seventh NMOS transistor MN11.

[0093] The source of the eighth PMOS transistor MP10 is connected to the output voltage VO, and the gate is connected between the drain of the seventh PMOS transistor MP9 and the drain of the sixth NMOS transistor MN10; the drain of the eighth PMOS transistor MP10 is connected to the drain of the seventh NMOS transistor MN11 to output the control signal Vea; the source of the seventh NMOS transistor MN11 is grounded, and the gate of the seventh NMOS transistor MN11 is connected to the second bias voltage Vbias2.

[0094] In this embodiment, the design of the error amplifier EA achieves excellent power supply rejection characteristics. First, the error amplifier EA allows a lower input voltage VIN to pass through, enhancing the compensation effects of the first compensation capacitor Cc and the second compensation capacitor Cc'. Second, a multi-stage cancellation mechanism is adopted to suppress the disturbance of the output voltage VO: in the differential input stage, the disturbance of the output voltage VO is converted into a common-mode interference and cancelled in the common-source amplification stage; in the common-source amplification stage, the disturbance of the output voltage VO is directly cancelled with the disturbance at the source end of the eighth PMOS transistor MP10 in the low-gain common-source amplification stage. In addition, due to the design of the internally powered error amplifier EA, not only is the power supply rejection ratio of the output voltage VO to this stage close to zero, but also since the output voltage VO itself has the ability to resist the interference of the external input voltage VIN, the immunity of the entire system to power supply disturbances is further enhanced.

[0095] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A low-dropout linear regulator with a wide voltage dropout range, characterized in that: include: An error amplifier EA, used for generating a control signal Vea; The common-gate buffer Buffer is powered by the input voltage VIN of the low-dropout linear regulator; The common-gate buffer Buffer includes a positive feedback loop, and the positive feedback loop is used to increase the slew rate of the control signal Vea and then output a driving signal VPGATE; The driving signal VPGATE is used to control the voltage feedback circuit to output the output voltage VO of the low-dropout linear regulator, and the output voltage VO is used to power the error amplifier EA; The positive feedback loop includes: a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN5 and a second NMOS tube MN6; The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the input voltage VIN; the sources of the first NMOS transistor MN5 and the second NMOS transistor MN6 are both grounded, the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN5 to form a first connection node, the first connection node outputs the driving signal VPGATE, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN6, the gates of the first NMOS transistor MN5 and the second NMOS transistor MN6 are connected; the gate of the second NMOS transistor MN6 is also connected to the drain of the second NMOS transistor MN6; The common-gate buffer Buffer also includes a common-gate input tube MN4; The gate of the common-gate input tube MN4 is connected to the bias voltage; the source of the common-gate input tube MN4 is connected to the drain of the first NMOS tube MN5, the output end VEA of the error amplifier EA is connected between the source of the common-gate input tube MN4 and the drain of the first NMOS tube MN5; the drain of the common-gate input tube MN4 is connected to the drain of the first PMOS tube MP1.

2. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 1, characterized in that: The common-gate buffer Buffer also includes a first resistor R1; The first resistor R1 is connected in parallel between the drain and the source of the first PMOS transistor MP1.

3. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 1, characterized in that: The common-gate buffer Buffer further includes a filter circuit, and the filter circuit includes a second resistor R2 and a first capacitor C1; Two ends of the second resistor R2 are connected between the gates of the first NMOS transistor MN5 and the second NMOS transistor MN6, one end of the second resistor R2 connected to the first NMOS transistor MN5 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded.

4. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 1, characterized in that: The error amplifier EA includes a differential input stage, and the differential input stage includes: a third PMOS tube MP5, a fourth PMOS tube MP6, a third NMOS tube MN7, a fourth NMOS tube MN8 and a fifth PMOS tube MP7; The gates of the third PMOS transistor MP5 and the fourth PMOS transistor MP6 receive the feedback voltage Vfb and the reference voltage Vref respectively, and the sources are connected; The source of the fifth PMOS transistor MP7 is connected to the output voltage VO, the drain is connected to the sources of the third PMOS transistor MP5 and the fourth PMOS transistor MP6, and the gate is connected to the first bias voltage Vbias1; The sources of the third NMOS tube MN7 and the fourth NMOS tube MN8 are both grounded, and the drains of the third NMOS tube MN7 and the fourth NMOS tube MN8 are respectively connected to the drains of the third PMOS tube MP5 and the fourth PMOS tube MP6; wherein, the connection node after the drain of the third NMOS tube MN7 is connected to the drain of the third PMOS tube MP5 serves as the first output end of the differential input stage, the connection node after the drain of the fourth NMOS tube MN8 is connected to the drain of the fourth PMOS tube MP6 serves as the second output end of the differential input stage, and the gates of the third NMOS tube MN7 and the fourth NMOS tube MN8 are respectively connected to the drains of the third NMOS tube MN7 and the fourth NMOS tube MN8.

5. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 4, characterized in that: The error amplifier EA further includes a common source amplifier stage, which includes: a sixth PMOS tube MP8, a fifth NMOS tube MN9, a seventh PMOS tube MP9 and a sixth NMOS tube MN10; The gates of the fifth NMOS transistor MN9 and the sixth NMOS transistor MN10 are respectively connected to the first output terminal and the second output terminal of the differential input stage, and the sources are both grounded; The sources of the sixth PMOS tube MP8 and the seventh PMOS tube MP9 are both connected to the output voltage VO, and the gates are interconnected. The drain of the sixth PMOS tube MP8 is connected to the drain of the fifth NMOS tube MN9, and the drain of the sixth PMOS tube MP8 is also connected to its gate; the drain of the seventh PMOS tube MP9 is connected to the drain of the sixth NMOS tube MN10.

6. The low-voltage dropout linear regulator with a wide voltage dropout range as claimed in claim 5, characterized in that: The error amplifier EA further includes a low-gain common-source amplifier stage, and the low-gain common-source amplifier stage includes: an eighth PMOS tube MP10 and a seventh NMOS tube MN11; The source of the eighth PMOS tube MP10 is connected to the output voltage VO, and the gate is connected between the drain of the seventh PMOS tube MP9 and the drain of the sixth NMOS tube MN10; the drain of the eighth PMOS tube MP10 is connected to the drain of the seventh NMOS tube MN11 and then outputs the control signal Vea; the source of the seventh NMOS tube MN11 is grounded, and the gate of the seventh NMOS tube MN11 is connected to the second bias voltage Vbias2.

7. The low-dropout linear regulator with a wide voltage drop range as claimed in claim 4, characterized in that: The voltage feedback circuit includes a power tube MP0; The gate of the power transistor MP0 receives the driving signal VPGATE, the source is connected to the input voltage VIN, and the drain outputs the output voltage VO to the error amplifier EA.

8. The low-dropout linear regulator with a wide voltage dropout range as claimed in claim 7, characterized in that: The voltage feedback circuit also includes a feedback network; The feedback network divides the output voltage VO to obtain the feedback voltage Vfb, and the feedback voltage Vfb is input into the non-inverting input terminal of the error amplifier EA, wherein the drain of the power tube MP0 is connected to one end of the feedback network to form a second connection node.

9. The low-voltage dropout linear regulator with a wide voltage dropout range as claimed in claim 8, characterized in that: It also includes a compensation circuit, which includes: a first compensation capacitor Cc, a second compensation capacitor Cc' and a voltage-controlled switch S0; One end of the first compensation capacitor Cc is connected to the second connection node, and the other end is connected to the voltage dividing node of the feedback network; One end of the voltage-controlled switch S0 is connected to one end of the first compensation capacitor Cc, and the other end is connected to one end of the second compensation capacitor Cc'; the other end of the second compensation capacitor Cc' is connected to the other end of the first compensation capacitor Cc.

10. The low-dropout linear regulator with a wide voltage dropout range as claimed in claim 9, characterized in that: It also includes a pull-down tube MN0, the gate of the pull-down tube MN0 is connected to the output end of the error amplifier EA, the source is grounded, and the drain inputs the output voltage VO into the error amplifier EA.

11. The low-dropout linear regulator with a wide voltage dropout range as claimed in claim 8, characterized in that: It also includes off-chip capacitance C0 and parasitic resistance esr; One end of the parasitic resistor esr is connected to the second connection node, and the other end is connected to one end of the off-chip capacitor C0 , and the other end of the off-chip capacitor C0 is grounded.

Images