An operating method of a controller, a controller, and a storage system

Abstract

The present disclosure provides a controller operation method, a controller and a storage system, which are applied to the technical field of data storage. The controller operation method comprises: writing, according to a write instruction, a mapping relationship of a first physical address to a first logical address into a first table item. The first physical address is a storage address in a storage; and the first logical address is a storage address recorded in the write instruction. Storage data is written into the first physical address. A second table item is obtained from the storage, and a mapping relationship of the first logical address to the first physical address is written into the second table item. When the product of a first time and a second time is greater than or equal to a first value, the second table item is updated into the storage. The first time is a theoretical time for refreshing the first table item; and the second time is a theoretical time for refreshing the second table item. The present disclosure can guarantee high efficiency, low latency and high reliability of L2P table updating under different write modes.

Description

Technical Field

[0001] This disclosure relates to the field of data storage technology, and in particular to a method for operating a controller, a controller, and a storage system. Background Technology

[0002] Electronic devices typically include a host computer and a storage system. The storage system comprises a controller and a memory. The memory stores data required for the host computer's operation. To ensure data security and reliability, the host computer operates based on logical addresses, while the memory stores data based on physical addresses. When the host computer needs to process data from the memory, it requires the controller to assist in converting between logical and physical addresses and executing the corresponding data processing operations. To ensure the accuracy of each data processing operation and to support the normal operation of the host computer, a logical-to-physical (L2P) mapping table, or L2P table, needs to be established. The size of the L2P table is related to the storage space of the memory. For example, with a storage capacity of 1TB, the L2P table size can reach approximately 1GB. Therefore, storing the complete L2P table in the controller's memory or cache space would affect the controller's operation. Typically, the complete L2P table is stored in the memory.

[0003] In practical applications, different write methods based on the controller lead to different data recording methods in the L2P table. The update time of the L2P table varies significantly under different write methods. Existing technologies use fixed thresholds or conditions to determine the timing of updates. This update method lacks flexibility, and under random write conditions, the L2P table update speed is slow, impacting the data processing performance of the storage system. Summary of the Invention

[0004] The embodiments of this disclosure provide a controller operation method, a controller, and a storage system, which achieve high efficiency, low latency, and high reliability in updating the L2P table under different write methods.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0006] In a first aspect, embodiments of this disclosure provide an operation method for a controller, the method comprising: acquiring a first entry; writing first mapping data into the first entry according to a write instruction; the first mapping data being used to indicate a mapping relationship between a first physical address and a first logical address; the first physical address being a storage address in memory; and the first logical address being a storage address recorded in the write instruction; writing storage data into the first physical address according to the first mapping data; acquiring a second entry and writing second mapping data into the second entry; the second mapping data being used to indicate a mapping relationship between a first logical address and a first physical address; and updating the second entry into memory when the product of a first time and a second time is greater than or equal to a first value; the first time being the theoretical time for refreshing the mapping data in the first entry; and the second time being the theoretical time for refreshing the mapping data in the second entry.

[0007] In the embodiments of this disclosure, the first entry is an entry obtained from the P2L table of the memory. The second entry is an entry obtained from the L2P table of the memory. When the write mode is entirely sequential, the first mapping data in the first entry is also recorded sequentially. At this time, the first mapping data in the first entry is located in one or two merged entries, and the second mapping data that needs to be updated in the second entry is also concentrated in one or two merged entries. The time for updating the L2P table can be regarded as equivalent to the first time required to refresh the first entry. When the write mode is entirely random, the second mapping data that needs to be updated in the second entry is located in multiple different merged entries, and the time for updating the L2P table is the second time for refreshing all merged entries in the second entry. Based on the first and second times, the above dynamic condition is obtained. In different application scenarios, the amount of randomly written storage data and sequentially written storage data are different, so the triggering time of this dynamic condition is also dynamically matched. Based on the above dynamic conditions, the flexibility of triggering L2P table updates can be improved. In the case of completely random writes, completely sequential writes, and a mixture of sequential and random writes, better update efficiency can be achieved. This avoids the situation where updating the L2P table under a single threshold condition or judgment condition cannot guarantee high update efficiency, low update latency, and the security and reliability of updated data under different write methods.

[0008] In some possible implementations, the value of the first time is equal to the product of the first coefficient and the first ratio; the first coefficient is a constant; the first ratio is the ratio between the total number of addresses that need to be refreshed in the first entry and the number of addresses that can be refreshed in a single operation in the first entry. In the embodiments of this application, when sequential writing is used entirely, the mapping relationship between physical addresses and logical addresses is recorded in the first entry according to address order. At this time, the address data in the first entry is concentrated in one or two merged entries. Only one or two merged entries need to be updated. Therefore, in the second entry, the data that needs to be updated is also concentrated in one or two merged entries. Therefore, in the case of completely sequential writing, the update time of the second entry can be approximately regarded as the refresh time of all addresses that need to be updated, that is, the refresh time of the total address recorded in the first entry. The update round speed of the total address of the first entry is the total number of addresses divided by the number of addresses that can be updated in a single operation, that is, the first ratio. The update time of each round is the first coefficient, which is the time determined according to the actual hardware parameters. Therefore, the first time is the first ratio multiplied by the first coefficient of the single-round update time.

[0009] In some possible implementations, the value of the first time interval is equal to the product of the first coefficient and the first sum; the first coefficient is a constant; the first sum is the first ratio plus one; the first ratio is the ratio between the total number of addresses that need to be refreshed in the first entry and the number of addresses that can be refreshed in a single instance in the first entry. In embodiments of this disclosure, by doubling the value of the first coefficient for the first time interval, the controller can avoid processing the decimal point of the first ratio, thus reducing the processing load.

[0010] In some possible implementations, the second time is equal to the product of a second coefficient and a second ratio; the second coefficient is a constant; and the second ratio is the ratio of the total number of merged items that need to be updated in the second entry to the number of merged items that can be refreshed in a single cycle. In embodiments of this disclosure, when entirely random writes are used, there are many merged items in the second entry. L2Ptable updates are performed on a per-merge-item basis; therefore, in this case, the second ratio (i.e., the total number of merged items that need to be refreshed divided by the number of merged items that can be refreshed in a single cycle) represents the required refresh rate, and the second coefficient represents the time required for a single refresh cycle. The product of the second ratio and the second coefficient is the second time.

[0011] In some possible implementations, the value of the second time is equal to the product of the second coefficient and the second sum; the second coefficient is a constant; the second sum is the second ratio plus one; the second ratio is the ratio of the total number of merged items that need to be updated in the second entry to the number of merged items that can be refreshed in a single time. In the embodiments of this disclosure, by doubling the value of the first coefficient for the first time, the controller can avoid processing the decimal point of the first ratio, thus reducing the processing load.

[0012] In some possible implementations, the first entry is larger than 16Kb. In embodiments of this disclosure, increasing the size of the first entry can improve the effectiveness of the solution.

[0013] Secondly, embodiments of this disclosure also provide a controller configured to: acquire a first entry; write first mapping data into the first entry according to a write instruction; the first mapping data is used to indicate a mapping relationship from a first physical address to a first logical address; the first physical address is a storage address in memory; the first logical address is a storage address recorded in the write instruction; write storage data into the first physical address according to the first mapping data; acquire a second entry and write second mapping data into the second entry; the second mapping data is used to indicate a mapping relationship from a first logical address to a first physical address; when the product of a first time and a second time is greater than or equal to a first value, update the second entry into memory, where the first time is the theoretical time to refresh the mapping data in the first entry; and the second time is the theoretical time to refresh the mapping data in the second entry.

[0014] In some possible implementations, the value of the first time is equal to the product of the first coefficient and the first ratio; the first coefficient is a constant; the first ratio is the ratio between the total number of addresses that need to be refreshed in the first entry and the number of addresses that can be refreshed in a single time in the first entry.

[0015] In some possible implementations, the value of the first time is equal to the product of the first coefficient and the first sum; the first coefficient is a constant; the first sum is the first ratio plus one; the first ratio is the ratio between the total number of addresses that need to be refreshed in the first entry and the number of addresses that can be refreshed in a single time in the first entry.

[0016] In some possible implementations, the value of the second time is equal to the product of the second coefficient and the second ratio; the second coefficient is a constant; and the second ratio is the ratio of the total number of merged items that need to be updated in the second entry to the number of merged items that can be refreshed in a single time.

[0017] In some possible implementations, the value of the second time is equal to the product of the second coefficient and the second sum; the second coefficient is a constant; the second sum is the second ratio plus one; the second ratio is the ratio of the total number of merged items that need to be updated in the second entry to the number of merged items that can be refreshed in a single time.

[0018] In some possible implementations, the controller includes a processing unit, an L2P cache, and a P2L cache. The processing unit is configured to: retrieve a first entry and write it to the P2L cache; write first mapping data to the P2L cache according to a write instruction; write storage data to a first physical address according to the first mapping data; retrieve a second entry and write it to the L2P cache; write second mapping data to the L2P cache; and update the second entry from the L2P cache into memory when the product of a first time and a second time is greater than or equal to a first value.

[0019] In some possible implementations, the first entry is greater than 16Kb.

[0020] Thirdly, embodiments of this disclosure also provide a storage system including a memory and a controller. The memory is coupled to the controller; the controller is configured to: retrieve a first entry from the memory; write first mapping data into the first entry according to a write instruction; the first mapping data indicates a mapping relationship from a first physical address to a first logical address; the first physical address is a storage address in the memory; the first logical address is the storage address recorded in the write instruction; write storage data into the first physical address according to the first mapping data; retrieve a second entry from the memory and write second mapping data into the second entry; the second mapping data indicates a mapping relationship from a first logical address to a first physical address; when the product of a first time and a second time is greater than or equal to a first value, update the second entry into the memory; the first time is the theoretical time to refresh the mapping data in the first entry; the second time is the theoretical time to refresh the mapping data in the second entry.

[0021] Fourthly, embodiments of this disclosure also provide an electronic device including a processor and the storage system described in the third aspect above. The processor is coupled to the storage system.

[0022] Fifthly, embodiments of this disclosure also provide a computer-readable storage medium including instructions. When the instructions are executed on a controller as described in the second aspect above, the controller is caused to perform the controller operation method as described in the first aspect above. When the instructions are executed on a storage system as described in the third aspect above, the storage system is caused to perform the controller operation method as described in the first aspect above. When the instructions are executed on an electronic device as described in the fourth aspect above, the electronic device is caused to perform the controller operation method as described in the first aspect above.

[0023] It is understood that the beneficial effects of the controller, storage system, electronic device and computer-readable storage medium provided in the above embodiments of this disclosure can be referred to the beneficial effects of the controller operation method described above, and will not be repeated here. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0025] Figure 1 This is a schematic diagram of the structure of a storage system according to some embodiments. Figure 1 ;

[0026] Figure 2 This is a schematic diagram of the structure of a controller according to some embodiments;

[0027] Figure 3 This is a schematic diagram of a first entry according to some embodiments;

[0028] Figure 4 This is a schematic diagram of sequential writing of a first table entry according to some embodiments;

[0029] Figure 5 This is a schematic diagram of random writing to a first table entry according to some embodiments;

[0030] Figure 6 A flowchart illustrating an operation method of a processor according to some embodiments. Figure 1 ;

[0031] Figure 7 A flowchart illustrating an operation method of a processor according to some embodiments. Figure 2 ;

[0032] Figure 8 This is a schematic diagram of the structure of a storage system according to some embodiments. Figure 2 ;

[0033] Figure 9 This is a schematic diagram of the structure of an electronic device according to some embodiments. Detailed Implementation

[0034] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0035] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0036] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0037] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0038] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0039] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0040] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0041] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0042] First, some basic concepts involved in the embodiments of this disclosure will be explained:

[0043] Sequential read / write, as the name suggests, involves grouping the data to be processed together and sequentially reading and writing it at an optimized speed. Ideal sequential read / write speeds are typically achieved when reading and writing large files. In short, sequential read / write refers to the memory working in the order the data is read and written, exhibiting continuous read / write characteristics. Specifically, this manifests as short and continuous read / write times, and the ability to read and write large and concentrated data. When we use a solid-state drive (SSD) to watch videos or copy video files larger than tens of gigabytes, we are utilizing the sequential read / write performance of the SSD. For flash memory applications such as SSDs, a key parameter is the sequential read / write speed (i.e., sequential read speed and sequential write speed). Higher speed values ​​indicate stronger sequential read / write performance; the unit for sequential read / write speed is MB / s. Sequential read / write performance is crucial for copying large files.

[0044] Random read / write is characterized by its randomness; data is read and written without adhering to the sequential order of files, allowing for arbitrary jumps to any file node for read / write operations. After a solid-state drive (SSD) has been used for a period of time, with continuous data writing and deletion, numerous scattered storage spaces or data addresses no longer concentrated in a contiguous area will naturally accumulate within the SSD's flash memory. At this point, the data read / write method is no longer sequential (continuous read / write), and the read / write speed is typically lower than sequential read / write speeds, sometimes significantly lower. Random read / write is characterized by small, dispersed data, high randomness, and longer read / write times. Random read / write performance is a key metric for SSDs, measured in Input / Output Operations Per Second (IOPS). Higher random read / write performance allows for faster processing of fragmented files (such as startup programs or virus scans). Applications such as small file storage (e.g., images), mail servers, and OLTP databases all involve frequent random read / write operations. For such applications, when choosing a solid-state drive (SSD), the random read / write performance is of paramount importance, with IOPS being the key metric.

[0045] Embodiments of this disclosure provide a storage system, such as Figure 1 As shown, the storage system 1000 includes a memory 100 and a controller 200. Figure 2 As shown, the controller 200 includes a host interface 10, a processor 20, a memory unit 30, and a storage interface 40. An L2P cache 31 and a P2L cache 32 are configured in the memory unit 30. The host interface 10, processor 20, L2P cache 31, P2L cache 32, and storage interface 40 are coupled via a data bus BUS1. The controller 200 is coupled to the memory 100 via the storage interface 40. The memory 100 is used to store data. The controller 200 is used to process data from the memory 100. Specifically, the controller 200 is configured to: receive data processing instructions sent by the host through the host interface 10; and perform data processing operations on the memory 100 according to the data processing instructions.

[0046] In this embodiment, to ensure the security and reliability of data operation, the host operates based on logical block addresses (LBAs), and the memory 100 stores data based on physical block addresses (PBAs). When the host needs to process data in the memory 100, it needs the controller 200 to assist in the conversion between logical and physical addresses and execute the corresponding data processing operations. To ensure the accuracy of each data processing operation and to meet the normal operation of the host, a mapping table for logical to physical (L2P) address conversion, i.e., an L2P table, needs to be established. The size of the L2P table is related to the storage space of the memory 100. Taking a storage capacity of 1TB for the memory 100 as an example, the size of the L2P table can reach approximately 1GB. Therefore, the memory unit 30 of the controller 200 cannot easily store the complete L2P table. Typically, the L2P table is stored in the memory 100. When performing data processing operations such as reading and refreshing the target data in the memory 100, it is necessary to locate the target data based on the address mapping data stored in the L2P table, and then process the target data. Because writing data to memory updates the mapped data in the L2P table, when processing data in a certain storage area of ​​memory, the controller needs to read part or all of the L2P table from memory and modify the mapped data according to the write operation. The modified mapped data is then updated back into the L2P table of memory 100. The timing, frequency, and speed of L2P table updates affect the data processing performance of storage system 1000. If the L2P table updates quickly, there may be frequent writes and writes to the same entry. If the L2P table updates slowly, there may be situations where data is written to a physical address but the L2P table hasn't been updated before the storage area of ​​the data is changed, reducing data security and reliability.

[0047] In some possible implementations, such as Figure 2 As shown, controller 200 is configured as follows:

[0048] The first entry is retrieved from memory 100 and stored in P2L cache 32. The first entry is part or all of the P2L table stored in memory 100. The P2L table is used to store mapping data for physical address to logical address conversion. The P2L table stored in memory 100 can be used to help recover information from the L2P table, etc. A write command is input through host interface 10. The write command is used to instruct data writing to the first logical address to write stored data. A corresponding first physical address is allocated according to the write command. First mapping data is written to the first entry. The first mapping data is used to indicate the mapping relationship for the first physical address to the first logical address conversion. According to the recorded first mapping data, stored data is written to the first physical address, thereby completing the write data processing of the write command. After the write data processing is completed, it means that data has been written to a blank physical address in memory 100, or the physical address of the stored data already written in memory 100 has been modified, etc. At this time, the mapping data in the L2P table has also changed. The L2P table needs to be updated. The specific update method is as follows: based on the first mapping data in the first table entry, second mapping data is written to the second table entry in the P2L cache 31. The second mapping data is used to indicate the mapping relationship between the first logical address and the first physical address. When a certain update timing is reached, the content recorded in the second table entry is updated back to the L2P table stored in the memory 100 to complete the update of the L2P table.

[0049] In some possible implementations, the update timing can be determined based on certain set threshold conditions or judgment conditions, triggering an update operation to update the modified mapping data back into the L2P table of memory. In some examples, the L2P table is updated based on the P2L table when the number of physical addresses that need to be updated reaches a certain number. In some examples, the L2P table is updated based on the P2L table when the currently accessed memory block is full.

[0050] Because write operations can be random, sequential, or a combination of both, the way the first mapped data is written to the first entry of the P2L cache 32 differs depending on the write method. Therefore, the update of the L2P table based on the first mapped data will also differ. For example... Figure 3 As shown, a P2L table can include multiple groups, and each group can include multiple first mapping data. Each first mapping data represents a mapping relationship from a physical address to a logical address. In the case of completely sequential writes, such as... Figure 4 As shown, the controller 200 allocates physical addresses to logical addresses sequentially according to the order in which write instructions are received. At this time, the first mapping data in the P2L table is recorded sequentially; that is, after one merge entry is full, new first mapping data is written to the next merge entry. Therefore, in the case of sequential writing, the first mapping data that needs to be updated is generally recorded in one or two merge entries. However, in the case of completely random writing, such as... Figure 5 As shown, the controller 200 randomly allocates physical addresses to logical addresses based on write instructions, which may result in the random writing of the corresponding first mapping data within different merge entries. In this case, the first mapping data that needs to be updated is generally located within multiple merge entries. L2P table updates are performed on a unit-by-merge-entry basis. When triggering L2P table updates through certain threshold or judgment conditions, if it's under random write conditions, the number of merge entries to be updated is large, resulting in a longer L2P table update time and impacting the performance of the storage system 1000. Conversely, if the judgment condition is based on the number of merge entries to be updated, it will reduce the update performance of the storage system 1000 under sequential write conditions. Furthermore, in practical applications, the storage system 1000 typically combines random and sequential writes, and the amount of data written randomly and sequentially varies depending on the application scenario. Therefore, using fixed threshold or judgment conditions to trigger L2P table updates results in poor processing flexibility, difficulty in achieving optimal performance under different write methods, and an inability to balance update efficiency, update latency, and data security. Figure 3 , Figure 4 and Figure 5 This is a schematic diagram illustrating the processing of the first entry in the P2Ltable. An example of the second entry in the L2P table can be found in the schematic diagram of the first entry.

[0051] In some possible implementations, this disclosure sets a dynamic condition to determine the timing of updating the L2P table. This dynamic condition is: determining whether the product of a first time and a second time is greater than or equal to a first value. Here, the first time is the theoretical time to refresh the mapping data in the first entry; the second time is the theoretical time to refresh the mapping data in the second entry. The controller 200 is configured to: when the dynamic condition is met, i.e., when the product of the first time and the second time is greater than or equal to the first value, retrieve the second entry from the L2P table of the memory 100, write the second mapping data into the second entry, and update the second entry into the L2P table of the memory 100. In this embodiment, when the writing method is entirely sequential, the first mapping data in the first entry is also recorded sequentially. At this time, the first mapping data in the first entry is located in one or two merged entries, and the second mapping data that needs to be updated in the second entry is also concentrated in one or two merged entries. The time for updating the L2P table can be considered equivalent to the first time required to refresh the first entry. When the write method is entirely random, the second mapping data to be updated in the second table entry is located in multiple different merged entries. Therefore, the time to update the L2P table is the second time when all merged entries in the second table entry are refreshed. Based on the first and second times, the dynamic condition described above is obtained. In different application scenarios, the amount of randomly written storage data and sequentially written storage data differs, so the triggering time of this dynamic condition is also dynamically matched. This dynamic condition improves the flexibility of triggering L2P table updates. It provides better update efficiency in both completely random and completely sequential write scenarios, as well as in scenarios where sequential and random writes are used in combination. It avoids the situation where updating the L2P table under a single threshold or judgment condition cannot guarantee high update efficiency, low update latency, and the security and reliability of updated data under different write methods.

[0052] In some examples, the first entry is greater than 16Kb. In some examples, the storage space of the P2L cache 32 is greater than 96Kb. In the embodiments of this application, the larger the first entry and the P2L cache 32 are, the better the implementation effect of the embodiments of this application. Therefore, in the design of the storage system 1000, the space of the P2L cache 32 can be made larger. However, the embodiments of this application should not be regarded as limiting the solution; the solution can also be implemented when the first entry is less than or equal to 16Kb.

[0053] Based on the above Figure 2 The controller of the structure can perform the following: Figure 6As shown, the operation method includes steps S100-S400:

[0054] S100: Retrieve the first entry from memory 100.

[0055] In the embodiments of this application, such as Figure 2 As shown, the controller 200 obtains the relevant entries of the P2Ltable from the memory 100 through the storage interface 40 to obtain the first entry, and stores the first entry in the P2L cache 32. The first entry can be all or part of the entries of the P2L table. In subsequent operations, the controller 200 can perform relevant data processing operations based on the physical address recorded in the first entry.

[0056] S200. Write the first mapping data into the first table entry according to the write instruction.

[0057] In some possible implementations, the first mapping data is used to indicate the mapping relationship from a first physical address to a first logical address; the first physical address is a storage address in memory 100; the first logical address is the storage address recorded in the write instruction. In this embodiment, the host operates based on the logical address. Similarly, the write instruction output by the host is used to instruct the writing of storage data to the first logical address. The controller 200, according to the write instruction, assigns the first physical address recorded in the first entry to the first logical address to obtain the first mapping data. The first mapping data indicates the mapping relationship from the first physical address to the first logical address, and the first mapping data is written into the first entry.

[0058] S300. Write storage data into the first physical address according to the first mapping data.

[0059] In this embodiment, after allocating a first physical address to a first logical address, the controller 200 obtains first mapping data. Then, based on the first mapping data, the controller 200 can write storage data into the allocated first physical address to execute a write instruction.

[0060] In some examples, the controller 200 may receive a write completion acknowledgment signal. In this embodiment, after a write instruction is executed on the first physical address in the memory 100, and the memory 100 completes the write operation, it sends a write completion acknowledgment signal to the controller 200. The controller 200 determines that the write instruction has been completed based on the write completion acknowledgment signal.

[0061] In some possible implementations, the execution interval between steps S200 and S300 in actual applications is relatively short. In some application scenarios, steps S200 and S300 can also be regarded as a single step executed simultaneously.

[0062] S400, Update the L2P table.

[0063] In some possible implementations, such as Figure 7 As shown, step S400 may include the sub-operations of steps S410-S430:

[0064] S410: Retrieve the second entry from memory 100.

[0065] In this embodiment of the application, the second entry corresponding to L2Ptable is obtained from memory 100 according to the first entry corresponding to P2L table.

[0066] S420. Write the second mapping data into the second table entry according to the first table entry.

[0067] In this embodiment, after receiving a write acknowledgment completion signal, it is determined that the write instruction has been completed. Second mapping data can then be written to the second entry based on the first mapping data recorded in the first entry. The second mapping data is used to indicate the mapping relationship between the first logical address and the first physical address.

[0068] S430. Update the second entry into memory 100.

[0069] In some possible implementations, the second entry is updated in the L2Ptable of memory 100 when a dynamic condition is met. This dynamic condition is that the product of a first time and a second time is greater than or equal to a first value. Here, the first time is the theoretical time to refresh the mapped data in the first entry; the second time is the theoretical time to refresh the mapped data in the second entry.

[0070] In some examples, steps S410-S430 can be executed once the dynamic condition is met. In other examples, steps S410 and S420 can be executed before the dynamic condition is met, and step S430 can be executed after the dynamic condition is met.

[0071] In this embodiment, when the write method is entirely sequential, the first mapping data in the first table entry is also recorded sequentially. Since the first mapping data in the first table entry is located in one or two merged entries, the second mapping data that needs to be updated in the second table entry is also concentrated in one or two merged entries. The time for updating the L2P table can be considered equivalent to the first time required to refresh the first table entry. However, when the write method is entirely random, the second mapping data that needs to be updated in the second table entry is located in multiple different merged entries. Therefore, the time for updating the L2P table is the second time required to refresh all merged entries in the second table entry. Based on the first and second times, the above dynamic condition is obtained. In different application scenarios, the amount of randomly written storage data and sequentially written storage data is different, so the triggering time of this dynamic condition is also dynamically matched. Based on the above dynamic conditions, the flexibility of triggering L2P table updates can be improved. In the case of completely random writes, completely sequential writes, and a mixture of sequential and random writes, better update efficiency can be achieved. This avoids the situation where updating L2P table under a single threshold condition or judgment condition cannot guarantee high update efficiency, low update latency, and the security and reliability of updated data under different write methods.

[0072] In some possible implementations, the value of the first time is equal to the product of the first coefficient and the first ratio; the first coefficient is a constant; the first ratio is the ratio between the total number of addresses that need to be refreshed in the first entry and the number of addresses that can be refreshed in a single time in the first entry.

[0073] For example, the first time T1 = k * ([Y / m]), where k is the first coefficient, a constant whose value is related to the device parameters of memory 100, such as a constant set according to FTL and hardware accelerator, representing the time for one round of address operation in a single refresh of the first entry. Y is the size of the first entry, i.e., the size of the total address data of P2L. m is the size of the address data in a single refresh of the first entry. In the embodiments of this application, when sequential writing is used, the mapping relationship between physical addresses and logical addresses is recorded in the first entry according to address order. At this time, the address data in the first entry is concentrated in one or two merged entries. Only one or two merged entries need to be updated. Then, in the second entry, the data to be updated is also concentrated in one or two merged entries. Therefore, in the case of completely sequential writing, the time for updating the second entry can be approximately regarded as the refresh time for all addresses that need to be updated, i.e., the refresh time of the total address recorded in the first entry. The update round speed of the total address of the first entry is the total number of addresses divided by the number of addresses that can be updated in a single refresh, i.e., Y / m. The update time for each round is k, which is determined based on the actual hardware parameters. Therefore, the first time T1 is the total round speed (i.e., the first ratio) multiplied by the single-round update time (i.e., the first coefficient).

[0074] In some possible implementations, the value of the first time is equal to the product of the first coefficient and the first sum; the first coefficient is a constant; the first sum is the first ratio plus one; the first ratio is the ratio between the total number of addresses that need to be refreshed in the first entry and the number of addresses that can be refreshed in a single time in the first entry.

[0075] For example, the first time T1 = k*([Y / m]+1). In this embodiment, because in actual applications, the calculated total wheel speed (i.e., the first ratio) may be a decimal value. During chip processing, the decimal may be rounded (e.g., ignoring the decimal as 0, or rounding it to 1). If the decimal value were calculated for each judgment in actual applications, it would greatly increase the computational load and reduce the processing performance of the storage system. Therefore, when calculating the first ratio, the decimal point can be uniformly canceled, and then the first ratio can be uniformly incremented by one. The resulting total wheel speed is the first ratio plus one wheel, which is then multiplied by the single-wheel refresh time k to obtain the first time T1. This method avoids the calculation of the decimal point.

[0076] In some possible implementations, the value of the second time is equal to the product of the second coefficient and the second ratio; the second coefficient is a constant; and the second ratio is the ratio of the total number of merged items that need to be updated in the second entry to the number of merged items that can be refreshed in a single time.

[0077] For example, the second time T2 = p([X / n]), where p is the second coefficient, a constant whose value is related to the device parameters of memory 100, such as a constant set according to FTL and hardware accelerator, representing the time for one round of merging operations in a single refresh of the second table entry. X is the number of merging entries that need to be updated in the second table entry, and n is the number of merging entries that can be refreshed in a single round. In this embodiment, when random writing is used, there are many merging entries in the second table entry. The L2P table is updated in units of merging entries. Therefore, in this case, the second ratio (i.e., the total number of merging entries that need to be refreshed divided by the number of merging entries that can be refreshed in a single round) represents the required refresh rate, and the second coefficient represents the time required for a single refresh. The product of the second ratio and the second coefficient is the second time T2.

[0078] In some possible implementations, the value of the second time is equal to the product of the second coefficient and the second sum; the second coefficient is a constant; the second sum is the second ratio plus one; the second ratio is the ratio of the total number of merged items that need to be updated in the second entry to the number of merged items that can be refreshed in a single time.

[0079] For example, the second time T2 = p([X / n] + 1). In this embodiment, the number of decimal point operations can be reduced. The technical principles and effects of this embodiment can be found in the description of the first time T1 embodiment described above, and will not be repeated here.

[0080] For example, dynamic conditions can be expressed as:

[0081] T1*T2=k*([Y / m]+1)*p([X / n]+1)≥First value?

[0082] When the above dynamic conditions are met, an update to the L2P table is triggered.

[0083] For example, the above dynamic conditions can be reduced to:

[0084] ([Y / m]+1)([X / n]+1)≥threshold?

[0085] In the formula, threshold = (first value / k * p).

[0086] In some examples, the threshold value can be in the range of [3, 6]. Since threshold = (first value / k * p), the first value can be [3k * p, 6k * p], where k is the time required to refresh the physical address in the first entry in a single operation, and p is the time required to refresh the merged entry in the second entry in a single operation.

[0087] Embodiments of this disclosure also provide a storage system 1000, such as... Figure 1 , Figure 8 As shown, where, Figure 1 This is a block diagram of a storage system 1000 according to the above embodiments. Figure 8 This is a block diagram of a storage system according to some other embodiments. Based on the above... Figure 1 In the illustrated embodiment, both the first and second entries correspond to a memory 100. And... Figure 8 In the illustrated embodiment, different memories 100 store corresponding L2P tables and P2L tables. In practical applications, it is necessary to obtain the first and second entries based on the L2P tables and P2L tables of the corresponding memories 100 in order to update the L2P tables of the corresponding memories 100. Regarding Figure 8 The technical principles and effects of updating the L2P table in the illustrated embodiments can be found in the foregoing description. Figures 1-7 The relevant descriptions will not be repeated here.

[0088] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0089] In some embodiments, see Figure 1 The storage system 1000 includes a controller 200 and a memory 100, and the storage system 1000 can be integrated into a memory card.

[0090] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0091] In other embodiments, see Figure 8 The storage system 1000 includes a controller 200 and multiple storage devices 100, and the storage system 1000 is integrated into a solid state drive (SSD).

[0092] In some embodiments of the storage system 1000, the controller 200 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0093] In other embodiments, the controller 200 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0094] In some embodiments, the controller 200 may be configured to manage data stored in the memory 100 and to communicate with external devices (e.g., a host). In some embodiments, the controller 200 may also be configured to control operations of the memory 100, such as reading, erasing, and other programming operations. In some embodiments, the controller 200 may also be configured to manage various functions relating to data stored or to be stored in the memory 100, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 200 is also configured to process error correction codes relating to data read from or written to the memory 100.

[0095] Of course, controller 200 can also perform any other suitable functions, such as formatting memory 100; for example, controller 200 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0096] It should be noted that the host interface 10 and the storage interface 40 achieve data interaction and communication based on interface protocols. These interface protocols include at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0097] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0098] like Figure 9 As shown, the electronic device 10000 may include the storage system 1000 described above, and may also include at least one of the following: a processor 2000 and a control memory (cache).

[0099] For example, processor 2000 can be the processor of a host.

[0100] For example, the processor 2000 can be a chip, specifically a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0101] Embodiments of this disclosure also provide a computer-readable storage medium including instructions. When the instructions are executed on a controller 200 as described in the above embodiments, the controller 200 is caused to perform the operation method of the controller 200 as described in the above embodiments. When the instructions are executed on a storage system 1000 as described in the above embodiments, the storage system 1000 is caused to perform the operation method of the controller 200 as described in the above embodiments. When the instructions are executed on an electronic device 10000 as described in the above embodiments, the electronic device 10000 is caused to perform the operation method of the controller 200 as described in the above embodiments.

[0102] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for operating a controller, characterized in that, The method includes: Retrieve the first entry from memory; According to the write instruction, first mapping data is written into the first table entry; the first mapping data is used to indicate the mapping relationship between the first physical address and the first logical address; the first physical address is the storage address in the memory; the first logical address is the storage address recorded in the write instruction; Based on the first mapping data, write storage data into the first physical address; The second entry is retrieved from the memory, and second mapping data is written into the second entry according to the first entry; the second mapping data is used to indicate the mapping relationship between the first logical address and the first physical address; when the product of the first time and the second time is greater than or equal to the first value, the second entry is updated into the memory; the first time is the theoretical time to refresh the mapping data in the first entry; the second time is the theoretical time to refresh the mapping data in the second entry.

2. The method of operating the controller according to claim 1, characterized in that, The value of the first time is equal to the product of the first coefficient and the first ratio; the first coefficient is a constant; the first ratio is the ratio between the total number of addresses that need to be refreshed in the first entry and the number of addresses that can be refreshed in a single time in the first entry.

3. The method of operating the controller according to claim 1, characterized in that, The value of the first time is equal to the product of the first coefficient and the first sum; the first coefficient is a constant; the first sum is the first ratio plus one; the first ratio is the ratio between the total number of addresses that need to be refreshed in the first entry and the number of addresses that can be refreshed in a single time in the first entry.

4. The method of operating the controller according to any one of claims 1-3, characterized in that, The value of the second time is equal to the product of the second coefficient and the second ratio; the second coefficient is a constant; the second ratio is the ratio of the total number of merged items that need to be updated in the second table entry to the number of merged items that can be refreshed in a single time.

5. The method of operating the controller according to any one of claims 1-3, characterized in that, The value of the second time is equal to the product of the second coefficient and the second sum; the second coefficient is a constant; the second sum is the second ratio plus one; the second ratio is the ratio of the total number of merged items that need to be updated in the second table entry to the number of merged items that can be refreshed in a single time.

6. The method of operating the controller according to any one of claims 1-3, characterized in that, The first entry is greater than 16Kb.

7. A controller, characterized in that, The controller is configured to: Retrieve the first entry from memory; According to the write instruction, first mapping data is written into the first table entry; the first mapping data is used to indicate the mapping relationship between the first physical address and the first logical address; the first physical address is the storage address in the memory; the first logical address is the storage address recorded in the write instruction; Based on the first mapping data, write storage data into the first physical address; The second entry is retrieved from the memory, and second mapping data is written into the second entry according to the first entry; the second mapping data is used to indicate the mapping relationship between the first logical address and the first physical address; when the product of the first time and the second time is greater than or equal to the first value, the second entry is updated into the memory, and the first time is the theoretical time to refresh the mapping data in the first entry; The second time is the theoretical time to refresh the mapping data in the second table entry.

8. The controller according to claim 7, characterized in that, The value of the first time is equal to the product of the first coefficient and the first ratio; the first coefficient is a constant; the first ratio is the ratio between the total number of addresses that need to be refreshed in the first entry and the number of addresses that can be refreshed in a single time in the first entry.

9. The controller according to claim 7, characterized in that, The value of the first time is equal to the product of the first coefficient and the first sum; the first coefficient is a constant; the first sum is the first ratio plus one; the first ratio is the ratio between the total number of addresses that need to be refreshed in the first entry and the number of addresses that can be refreshed in a single time in the first entry.

10. The controller according to claim 7, characterized in that, The value of the second time is equal to the product of the second coefficient and the second ratio; the second coefficient is a constant; the second ratio is the ratio of the total number of merged items that need to be updated in the second table entry to the number of merged items that can be refreshed in a single time.

11. The controller according to claim 7, characterized in that, The value of the second time is equal to the product of the second coefficient and the second sum; the second coefficient is a constant; the second sum is the second ratio plus one; the second ratio is the ratio of the total number of merged items that need to be updated in the second table entry to the number of merged items that can be refreshed in a single time.

12. The controller according to any one of claims 7-11, characterized in that, The controller includes a processing unit, an L2P buffer, and a P2L buffer; wherein, the processing unit is configured as follows: Obtain the first table entry and write the first table entry into the P2L cache; According to the write instruction, the first mapping data is written into the P2L buffer; Based on the first mapping data, write storage data into the first physical address; Obtain the second table entry, write the second table entry into the L2P cache, and write the second mapping data into the L2P cache; When the product of the first time and the second time is greater than or equal to the first value, the second entry is updated from the L2P cache into the memory.

13. The controller according to any one of claims 7-11, characterized in that, The first entry is greater than 16Kb.

14. A storage system, characterized in that, Includes a memory and a controller; the memory is coupled to the controller; the controller is configured to: Retrieve the first entry from the memory; According to the write instruction, first mapping data is written into the first table entry; the first mapping data is used to indicate the mapping relationship between the first physical address and the first logical address; the first physical address is the storage address in the memory; the first logical address is the storage address recorded in the write instruction; Based on the first mapping data, write storage data into the first physical address; The second entry is retrieved from the memory, and second mapping data is written into the second entry according to the first entry; the second mapping data is used to indicate the mapping relationship between the first logical address and the first physical address; when the product of the first time and the second time is greater than or equal to the first value, the second entry is updated into the memory, and the first time is the theoretical time to refresh the mapping data in the first entry; The second time is the theoretical time to refresh the mapping data in the second table entry.

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