Multi-chip controller upgrading method and device, equipment and storage medium

Abstract

The invention discloses a multi-chip controller upgrading method and device, equipment and a storage medium, and relates to the technical field of controller upgrading, in the method, when a controller chip master node receives upgrading starting information, to-be-verified slave nodes corresponding to the sent upgrading starting information are added to a flash list; when the preset upgrading time is up, obtaining a target upgrading node contained in the flashing list; performing preset version inspection on a target upgrade package corresponding to the target upgrade node based on the flash list; and when the verification is passed, controlling the target upgrade node to perform parallel data upgrade based on the target upgrade package. According to the method, the chip master node is set to add the slave nodes in the upgrading state to the flashing list, then version verification is performed on the upgrading data packets of the slave nodes based on the flashing list, and the slave nodes are controlled to perform parallel data upgrading when the version verification of the upgrading packets of the slave nodes is passed. Therefore, the upgrading time consumption is reduced in parallel, and the upgrading reliability of the multi-chip controller is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of controller upgrade technology, and in particular to a multi-chip controller upgrade method, device, equipment and storage medium. Background Art

[0002] In the modern automotive field, with the growing demand for software system complexity, the architecture of automotive electronic domain controllers is usually composed of multiple chips. Whether in the development stage or in the mass production process, the software of each chip needs to be continuously updated and maintained.

[0003] For a multi-chip controller, the controller version may include different version combinations of different chips inside it. There are two main existing methods for flashing multi-chip controllers: one is to set a master node, and all flashing-related interactions are performed by the master node with the outside, and then the master node is responsible for distributing updates to different chips inside the controller. This method uses master node serial control, and the upgrade takes a long time; the other is that each chip is distributed through the switch inside the controller, and each chip handles the upgrade interaction with the host computer. Although the upgrade time is short, there is a security risk of asynchronous upgrade.

[0004] Therefore, there is an urgent need for a multi-chip controller upgrade method that is both reliable and less time-consuming. Summary of the invention

[0005] The main purpose of the present application is to provide a multi-chip controller upgrade method, device, equipment and storage medium, aiming to solve the technical problem of how to provide a reliable and less time-consuming multi-chip controller upgrade method.

[0006] To achieve the above object, the present application proposes a multi-chip controller upgrade method, which is applied to a multi-chip controller, wherein the controller includes a chip as a master node and a plurality of chips as slave nodes, and the method is executed by the chip master node, and the method includes:

[0007] When receiving the upgrade startup information, the slave node to be verified corresponding to the upgrade startup information is added to the flash list; the upgrade startup information is generated by the slave node to be verified when receiving the software upgrade package sent by the host computer;

[0008] When the preset upgrade time is reached, obtaining the target upgrade node contained in the flash list;

[0009] Performing a preset version check on the target upgrade package corresponding to the target upgrade node based on the flash list;

[0010] When the verification passes, the target upgrade node is controlled to perform parallel data upgrade based on the target upgrade package.

[0011] In one embodiment, the step of performing a preset version check on the target upgrade package corresponding to the target upgrade node based on the flash list includes:

[0012] Determine whether the target upgrade node passes the preset download verification;

[0013] If the target upgrade node passes the preset download verification, obtaining the target version information corresponding to the software upgrade package of the target upgrade node based on the flash list;

[0014] A version consistency check is performed according to the target version information.

[0015] In one embodiment, the step of determining whether the target upgrade node passes a preset download verification includes:

[0016] Obtaining installation verification information corresponding to the target upgrade node;

[0017] Determining whether the target upgrade node passes a preset download verification based on the installation verification information;

[0018] In one embodiment, after determining whether the target upgrade node passes the preset download verification, the method further includes:

[0019] If the target upgrade node fails the preset download verification, verification failure information is sent to the target upgrade node. When the target upgrade node receives the verification failure information, it stops the upgrade download operation and feeds back verification abnormality information to the upper computer.

[0020] In one embodiment, when the verification is passed, the step of controlling the target upgrade node to perform parallel data upgrade based on the target upgrade package includes:

[0021] When the verification passes, an upgrade success message is sent to the target upgrade node. When the target upgrade node receives the upgrade success message, it switches the current storage area to the corresponding target upgrade storage area according to the corresponding storage identifier for parallel data upgrade; the target upgrade storage area stores the target upgrade package.

[0022] In one embodiment, after performing a preset version check on the target upgrade package corresponding to the target upgrade node based on the flash list, the method further includes:

[0023] When the check fails, an upgrade failure message is sent to the target upgrade node. When the target upgrade node receives the upgrade failure message, it stops the partition switching operation and feeds back upgrade abnormality information to the upper computer.

[0024] In one embodiment, when the preset upgrade time is reached, before obtaining the target upgrade node included in the flash list, the method further includes:

[0025] When it detects that the host computer sends a software upgrade package, it adds itself to the flash list.

[0026] In addition, to achieve the above purpose, the present application also proposes a multi-chip controller upgrade device, which includes:

[0027] A list control module is used to add the slave node to be verified corresponding to the upgrade startup information to the flash list when receiving the upgrade startup information; the upgrade startup information is generated by the slave node to be verified when receiving the software upgrade package sent by the host computer;

[0028] A node determination module, used for obtaining the target upgrade node included in the flash list when the preset upgrade time is reached;

[0029] An information verification module, configured to perform a preset version verification on a target upgrade package corresponding to the target upgrade node based on the flash list;

[0030] The upgrade control module is used to control the target upgrade node to perform parallel data upgrade based on the target upgrade package when the verification is passed.

[0031] In addition, to achieve the above-mentioned objectives, the present application also proposes a multi-chip controller upgrade device, the device including: a memory, a processor, and a multi-chip controller upgrade program stored in the memory and runnable on the processor, the multi-chip controller upgrade program being configured to implement the steps of the multi-chip controller upgrade method as described above.

[0032] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a storage medium on which a multi-chip controller upgrade program is stored. When the multi-chip controller upgrade program is executed by the processor, the steps of the multi-chip controller upgrade method as described above are implemented.

[0033] The present application provides a method, device, equipment and storage medium for upgrading a multi-chip controller. The method is applied to a multi-chip controller, and the controller includes a chip as a master node and several chips as slave nodes. The method is executed by the chip master node, and the method includes: when receiving the upgrade startup information, adding the slave node to be verified corresponding to the upgrade startup information to the flash list; the upgrade startup information is generated by the slave node to be verified when receiving the software upgrade package sent by the upper computer; when the preset upgrade time is reached, obtaining the target upgrade node contained in the flash list; performing a preset version check on the target upgrade package corresponding to the target upgrade node based on the flash list; when the check passes, controlling the target upgrade node to perform parallel data upgrade based on the target upgrade package. The present application sets the chip master node in the controller to add the slave nodes in the upgrade state to the flash list, and then performs version check on the upgrade data packets of each slave node based on the flash list, and only controls the parallel data upgrade of the slave nodes when the upgrade package version check of each slave node passes, thereby reducing the upgrade time while ensuring the consistency of the upgrade version of each slave node and the reliability of the multi-chip controller upgrade. Therefore, this application ensures the synchronization of versions while ensuring that each chip handles its own flashing. The overall flashing time takes the flashing time of the longest chip, which also ensures the shortest flashing time, effectively providing a multi-chip controller upgrade method that is both reliable and less time-consuming. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0036] Figure 1 This is a flow chart of the first embodiment of the multi-chip controller upgrade method of the present application;

[0037] Figure 2 This is a schematic diagram of the master-slave node upgrade interaction of the first embodiment of the multi-chip controller upgrade method of the present application;

[0038] Figure 3 This is a flow chart of a second embodiment of a multi-chip controller upgrade method of the present application;

[0039] Figure 4 This is a schematic diagram of the master-slave node flashing interaction of the second embodiment of the multi-chip controller upgrade method of the present application;

[0040] Figure 5 This is a schematic diagram of an upgrade exception handling process of a second embodiment of a multi-chip controller upgrade method of the present application;

[0041] Figure 6 This is a schematic diagram of the module structure of the multi-chip controller upgrade device according to an embodiment of the present application;

[0042] Figure 7 Schematic diagram of the device structure of the hardware operating environment involved in the multi-chip controller upgrade method in the embodiment of the present application.

[0043] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0044] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0045] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0046] The main solution of the present application is: setting a chip as a master node and several chips as slave nodes for the numerous chips contained in the controller, the method is executed by the chip master node, and the method includes: when the upgrade startup information is received, adding the slave node to be verified corresponding to the upgrade startup information to the flash list; the upgrade startup information is generated by the slave node to be verified when the software upgrade package sent by the upper computer is received; when the preset upgrade time is reached, obtaining the target upgrade node contained in the flash list; performing a preset version check on the target upgrade package corresponding to the target upgrade node based on the flash list; when the check passes, controlling the target upgrade node to perform parallel data upgrade based on the target upgrade package.

[0047] At present, when a multi-chip controller is upgraded, the upgrade takes a long time when serial control of the master node is adopted; when parallel control of each chip is adopted, there is a security risk of version mismatch. Therefore, a reliable and time-saving upgrade method is urgently needed.

[0048] To solve the above problems, the present application sets the chip master node to add the slave nodes in the upgrade state to the flash list, and then performs version verification on the upgrade data packet of each slave node based on the flash list, and only controls the parallel data upgrade of the slave nodes when the upgrade package version verification of each slave node passes. In this way, while reducing the upgrade time by upgrading the slave nodes in parallel, it ensures the consistency of the upgraded versions of each slave node and ensures the reliability of the multi-chip controller upgrade.

[0049] It should be noted that the present embodiment is applied to a multi-chip controller, which includes a chip as a master node and several chips as slave nodes. Therefore, the execution subject of the present embodiment can be a chip master node, or a multi-chip controller upgrade system including a chip master node, or a computing service device including a chip master node with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or a multi-chip controller upgrade device that can realize the above functions, etc. The present embodiment does not make any specific limitations on this.

[0050] Based on this, the embodiment of the present application provides a multi-chip controller upgrade method, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the multi-chip controller upgrade method of the present application.

[0051] In this embodiment, the method includes steps S10 to S40:

[0052] Step S10, when receiving the upgrade startup information, adding the slave node to be verified corresponding to the sending of the upgrade startup information to the flash list; the upgrade startup information is generated by the slave node to be verified when receiving the software upgrade package sent by the host computer;

[0053] It should be understood that in this embodiment, several chips of the controller can be set as a flash chip master node and several flash chip slave nodes, each chip can receive its own flash instruction, and the setting of the master and slave nodes can be set arbitrarily according to the needs. Specifically, in this embodiment, each chip can communicate data through Ethernet, and each chip has a corresponding IP address or MAC address. During the data communication process of each chip in the controller, the network data communication destination address of each slave node chip is set to the IP address or MAC address of the master node, and the setting of the flash master node can be set.

[0054] It is easy to understand that in this embodiment, when any chip from the node chip accepts the download from the external host computer, it can inform the master node that it is in the download state through the network communication inside the controller, that is, it sends the upgrade startup information to the master node. After receiving any upgrade startup information, the master node can mark the entire controller as entering the flashing state and add the first chip that triggers the flashing state to the flashing list created by itself.

[0055] It should be understood that in this embodiment, when the user integrates and packages the upgrade data software of each chip on the host computer, in addition to the data in the storage area of ​​each chip, the header structure of the data is additionally added to contain the version information, chip information and signature information of the target, and then compressed to generate the software upgrade package corresponding to each chip to be upgraded. Each software upgrade package can also be matched with different chips by naming or identifier, which is convenient for the host computer to perform relevant identification and establish connections with different chips respectively, so as to issue them in parallel. The above data packaging can be combined with the software packages of any number of chips of the controller. The host computer can only identify the corresponding software package to establish a connection with the corresponding chip and transmit the software upgrade package and trigger the installation.

[0056] It is understandable that the above flash list is a list created by the master node after any chip triggers the upgrade flash for the first time each time it is powered on. When each slave node receives the software upgrade package sent by the host computer and enters the flash state, it generates the upgrade startup information and notifies the master node to record it, so that the master node can subsequently compare and verify the versions of the software upgrade packages of each slave node to be tested. The flash list can be cleared 20 seconds after the master node loses power or the version comparison fails.

[0057] In a feasible implementation manner, in this embodiment, when the preset upgrade time is reached, before obtaining the target upgrade node included in the flash list, the step S11 is further included:

[0058] Step S11, when detecting that the upper computer sends a software upgrade package, add itself to the flash list.

[0059] It is easy to understand that after the master node receives the upgrade startup information sent by the first slave node and generates a flash list, the upper computer may also request other slave nodes or notify the master node to start flashing itself. Similarly, the master node can also add its corresponding node to the flash list after receiving the software upgrade package sent by the upper computer.

[0060] Step S20, when the preset upgrade time is reached, obtaining the target upgrade node contained in the flash list;

[0061] It is understandable that after any node notifies the master node to enter the flashing state or the master node itself enters the flashing state, the master node adds the corresponding node to the flashing list, notifies the entire controller to enter the flashing state, and starts a timeout timer A (chips are no longer allowed to enter the flashing state when the preset upgrade time is exceeded). At this time, the status notified by the master node to the slave node includes the default state, the existence of a node in the flashing state, any node flashing failure, all nodes flashing success and all nodes partitioning success. The master node can send different status codes to each slave node in different states. Therefore, when the master node determines that the preset upgrade time has arrived based on the timeout timer, the master node no longer allows the addition of chip slave nodes, and uses the chip nodes already included in the current flashing list as the above-mentioned target upgrade nodes. It is easy to understand that the target upgrade node may include the master node itself and / or each node to be verified that sends upgrade startup information.

[0062] Step S30, performing a preset version check on the target upgrade package corresponding to the target upgrade node based on the flash list;

[0063] It is understandable that after receiving the corresponding software upgrade package sent by the host computer, i.e. the above target upgrade package, the target upgrade node can obtain the software package information of the target upgrade package, confirm the information and version of the corresponding upgrade package, and synchronize the version information with the master node through network communication. The master node can perform consistency check on the upgrade data package version information of all slave nodes contained therein based on the flash list, thereby realizing the above preset version check.

[0064] Step S40: When the verification is passed, control the target upgrade node to perform parallel data upgrade based on the target upgrade package.

[0065] In a first feasible implementation manner, step S40 may include step S41:

[0066] Step S41, when the inspection passes, sends an upgrade success message to the target upgrade node. When the target upgrade node receives the upgrade success message, it switches the current storage area to the corresponding target upgrade storage area according to the corresponding storage identifier for parallel data upgrade; the target upgrade storage area stores the target upgrade package.

[0067] It should be understood that in this embodiment, if the master node detects that the upgrade data packet versions of each node included in the flash list are the same, the inspection is passed. In addition, in this embodiment, the controller can be designed to run in dual partitions. After the host computer requests the upgrade installation of each chip to start, each chip performs the relevant installation and overwrites the corresponding upgrade storage partition. Therefore, after the master node detects that the target versions of all chips in the flash list are aligned, the master node will make relevant notifications through the network, allowing each target upgrade node to switch from the current storage area containing the old version of the system to the target upgrade storage partition containing the upgraded version of the system. The target upgrade storage area is the download storage area of ​​the target upgrade package (if the master node itself is involved in the upgrade flash, it also switches the partition).

[0068] Specifically, the switching and upgrading storage partitions corresponding to each chip can be loaded by writing the identification bit of the fixed power-on identified storage partition, that is, the above storage identification, and each chip can also confirm which partition to start from by identifying the corresponding storage identification when officially performing data upgrade. In this embodiment, each slave node to be verified will not switch partitions before the master node notifies all chips that they are successful. This ensures that the controller can achieve an overall new version update when upgrading.

[0069] In a second feasible implementation manner, after step S30, step S50 may also be included:

[0070] Step S50: When the verification fails, an upgrade failure message is sent to the target upgrade node. When the target upgrade node receives the upgrade failure message, it stops the partition switching operation and feeds back upgrade abnormality information to the upper computer.

[0071] It is easy to understand that if the master node detects that the upgrade data package version of any node in the flash list is different from the upgrade data package version of other nodes, the test fails. The master node will send an upgrade failure message to notify all slave nodes entering the flash of the overall failure. When all chips receive the upgrade failure message, they stop the partition switching operation and feedback the host computer upgrade exception information to report the upgrade failure, ensuring that all chips in the entire controller are in a complete old version.

[0072] In addition, if the chip needs to be started after the upgrade, in this embodiment, each chip slave node confirms to start from the corresponding upgraded storage partition by identifying the corresponding storage identifier at startup, and responds to the restart command of the host computer. However, the slave node chip here does not execute its own restart, but notifies the master node through network communication that its own partition switching is successful. Then, after all the nodes in the flash list have completed the partition switching, the master node notifies all the chips in the flash list that all the chips have successfully cut partitions, and updates the version number according to the version number of each chip during the upgrade process, and then restarts the entire controller. The specific upgrade and update process of this embodiment can be as follows: Figure 2 As shown, Figure 2 This is a schematic diagram of the master-slave node upgrade interaction of the first embodiment of the multi-chip controller upgrade method of this application. Figure 2 Actor1 is the host computer.

[0073] In this embodiment, the chip master node in the controller is set to add the slave nodes in the upgrade state to the flash list, and then perform version verification on the upgrade data packets of each slave node based on the flash list, and only control the parallel data upgrade of the slave nodes when the upgrade package version verification of each slave node passes, thereby reducing the upgrade time while ensuring the consistency of the upgrade version of each slave node and the reliability of the multi-chip controller upgrade. Therefore, this embodiment ensures that each chip processes its own flash while ensuring the synchronization of the version, and the overall flash time takes the flash time of the longest chip, which also ensures the shortest flash time, effectively providing a multi-chip controller upgrade method that is both reliable and less time-consuming.

[0074] The present embodiment provides a multi-chip controller upgrade method, which is applied to a multi-chip controller. The controller includes a chip master node and several chip slave nodes. The method is executed by the chip master node. The method includes: when it is detected that the upper computer sends a software upgrade package, add itself to the flash list. When the upgrade startup information is received, add the slave node to be verified corresponding to the upgrade startup information to the flash list; the upgrade startup information is generated by the slave node to be verified when receiving the software upgrade package sent by the upper computer; when the preset upgrade time is reached, obtain the target upgrade node contained in the flash list; perform a preset version check on the target upgrade package corresponding to the target upgrade node based on the flash list; when the check passes, send the upgrade success information to the target upgrade node, and when the target upgrade node receives the upgrade success information, according to the corresponding storage identifier, switch the current storage area to the corresponding target upgrade storage area for parallel data upgrade; the target upgrade storage area stores the target upgrade package. When the check fails, send the upgrade failure information to the target upgrade node, and the target upgrade node stops the partition switching operation when receiving the upgrade failure information, and feedbacks the upgrade abnormal information to the upper computer. In this embodiment, the chip master node in the controller adds the slave nodes in the upgrade state to the flash list, and then performs version verification on the upgrade data packets of each slave node based on the flash list, and only controls the parallel data upgrade of the slave nodes when the upgrade package version verification of each slave node passes, thereby reducing the upgrade time by parallel upgrading of the slave nodes, ensuring the consistency of the upgraded versions of each slave node, and ensuring the reliability of the multi-chip controller upgrade. Therefore, this embodiment ensures that each chip handles its own flashing while ensuring the synchronization of the version, and the overall flashing time takes the flashing time of the longest chip, which also ensures the shortest flashing time, effectively providing a multi-chip controller upgrade method that is both reliable and less time-consuming.

[0075] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction and will not be repeated later.

[0076] It is easy to understand that in order to further ensure the reliability of controller upgrade, this embodiment can further confirm the download integrity check of the upgrade data packet of each target upgrade node before performing the preset version check of the target upgrade node. Figure 3 , Figure 3 This is a flow chart of the second embodiment of the multi-chip controller upgrade method of the present application. In this embodiment, step S30 includes steps A1 to A3:

[0077] Step A1, determining whether the target upgrade node passes the preset download verification;

[0078] It is easy to understand that in this embodiment, the external host computer may establish a link with any chip node in the controller at any time, and start the flashing action, requesting the corresponding chip to download the software upgrade package. At this time, the corresponding chip responds normally to the host computer action and periodically notifies its own flashing status to the master node. In this embodiment, the flashing status notified by the slave node to the master node may include the default state, flashing, flashing success, flashing failure and partition cutting success; the verification status notified to the master node may include verification success and verification failure. It is easy to understand that the status code sent by the slave node to the master node in the above different flashing states or verification states is also different.

[0079] In a feasible implementation manner, in this embodiment, step A1 includes steps A11 to A12:

[0080] Step A11, obtaining installation verification information corresponding to the target upgrade node;

[0081] Step A12: determining whether the target upgrade node passes a preset download verification based on the installation verification information.

[0082] It is easy to understand that the above-mentioned installation verification information can be the upgrade package installation status code corresponding to the upgrade package flashing and installation and the verification status code corresponding to the upgrade package verification performed by the slave node or the master node itself after receiving the software upgrade package sent by the host computer. The master node can then determine whether all target upgrade nodes have entered the flashing success state based on the installation verification information, that is, whether they have passed the preset download verification.

[0083] Specifically, after each slave node responds to the download and installation request of the host computer, during the download, verification and decompression process of the software upgrade package, it can periodically send its own upgrade package installation status and upgrade package verification status to the master node. The master node will query in turn whether all the nodes in the current flash list have entered the flash success state. If they have, it means that the target upgrade node has passed the preset download verification. At this time, the master node can turn off the timeout timer and no longer allow new nodes to be added to the flash list. At the same time, the master node can synchronize the flash status to all nodes successfully flashed, thereby notifying all chips in the flash list that the preset download verification has passed.

[0084] Step A2: if the target upgrade node passes the preset download verification, then obtaining the target version information corresponding to the software upgrade package of the target upgrade node based on the flash list;

[0085] Step A3: perform version consistency check according to the target version information.

[0086] It should be understood that after the corresponding software upgrade package is downloaded, verified and decompressed, each slave node and master node can obtain the relevant software package information and confirm the information and version of the corresponding upgrade package. In the final installation verification phase, the master node is notified that the flashing is complete, and the corresponding target version information is synchronized with the master node through network communication, and the host computer is periodically replied to wait.

[0087] Therefore, the master node can obtain the target version information corresponding to the software upgrade package of each target upgrade node in turn according to the flash list, and perform a version consistency check to determine whether the software versions corresponding to each target upgrade node are the same according to the target version information.

[0088] It is easy to understand that the above version consistency check is only a feasible way of preset version check in this embodiment, but does not limit its specific implementation content, which can be determined according to actual conditions. For example, if the user's version upgrade requirement is to perform a decremental version update in the response order, the specific implementation content of the above preset version check can be to perform a decremental version check on each target upgrade node according to the arrangement order of the flash list.

[0089] In a feasible implementation manner, in this embodiment, step A1 further includes step B1:

[0090] Step B1: If the target upgrade node fails the preset download verification, verification failure information is sent to the target upgrade node. When the target upgrade node receives the verification failure information, it stops the upgrade download operation and feeds back verification abnormality information to the upper computer.

[0091] It is easy to understand that if the master node detects that any of the target upgrade nodes has a software upgrade package download failure, a software upgrade package overwrite failure, or a software upgrade package verification failure, it indicates that the target upgrade node has not passed the preset download verification. At this time, the master node can synchronize the flashing status to any node flashing failure, that is, send the above verification failure information to the target upgrade node. If each target upgrade node is performing an upgrade download operation, it can stop accordingly and feedback the verification exception information to the upper computer. At this time, all chips in the entire controller will not cut partitions, and all will remain in the old partition to ensure version consistency. The specific software upgrade package flashing process of this embodiment can be as follows Figure 4 As shown, Figure 4 This is a schematic diagram of the master-slave node flashing interaction of the second embodiment of the multi-chip controller upgrade method of the present application.

[0092] In summary, in this embodiment, during the controller multi-chip upgrade process, there are two upgrade abnormalities: flash abnormality and upgrade version abnormality. Figure 5 To illustrate with an example, Figure 5This is a schematic diagram of the upgrade exception handling process of the second embodiment of the multi-chip controller upgrade method of the present application.

[0093] like Figure 5 As shown in the figure, if any step of the flashing process of any node fails during the upgrade process, the master node will be notified of the failure. The master node will then notify all chips in the flashing list that the flashing failed, and the corresponding chips will reply to the host computer with a negative response, that is, feedback of the above verification abnormality information. All chips in the entire controller will not be partitioned, and all will be retained in the old partition to ensure version consistency.

[0094] At the same time, if during the upgrade process, after notifying all chips that the flashing is complete, the master node finds that the target version of the target upgrade node in the flashing list is inconsistent, the master node will also notify other chips of the failure. At this time, all chips in the entire controller will not be partitioned, and all will remain in the original current storage partition to ensure version consistency.

[0095] Therefore, in this implementation, only when all chip target versions in the flash list meet the preset version verification requirements and the storage area corresponding to another partition is overwritten successfully, the master node will make relevant notifications through the network, allowing each target upgrade node to switch partitions, further ensuring the upgrade reliability of the multi-chip controller.

[0096] This embodiment obtains the installation verification information corresponding to the target upgrade node; based on the installation verification information, it determines whether the target upgrade node has passed the preset download verification. If the target upgrade node passes the preset download verification, the target version information corresponding to the software upgrade package of the target upgrade node is obtained based on the flash list; and the version consistency check is performed according to the target version information. If the target upgrade node fails to pass the preset download verification, a verification failure message is sent to the target upgrade node. When the target upgrade node receives the verification failure message, it stops the upgrade download operation and feeds back the verification exception information to the upper computer. In this embodiment, only after ensuring that all chip target versions in the flash list meet the requirements of the preset version verification and the storage area corresponding to another partition is overwritten successfully, the master node will make relevant notifications through the network, allowing each target upgrade node to switch partitions, and further ensuring the upgrade reliability of the multi-chip controller.

[0097] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the multi-chip controller upgrade method of the present application. More simple transformations based on this technical concept are all within the protection scope of the present application.

[0098] This application also provides a multi-chip controller upgrade device, please refer to Figure 6 , Figure 6This is a schematic diagram of the module structure of a multi-chip controller upgrade device according to an embodiment of the present application. In this embodiment, the multi-chip controller upgrade device includes:

[0099] The list control module 601 is used for adding the slave node to be verified corresponding to the sending of the upgrade startup information to the flash list when receiving the upgrade startup information; the upgrade startup information is generated by the slave node to be verified when receiving the software upgrade package sent by the host computer;

[0100] The node determination module 602 is used to obtain the target upgrade node included in the flash list when the preset upgrade time is reached;

[0101] An information verification module 603 is used to perform a preset version verification on the target upgrade package corresponding to the target upgrade node based on the flash list;

[0102] The upgrade control module 604 is used to control the target upgrade node to perform parallel data upgrade based on the target upgrade package when the verification passes.

[0103] Optionally, in this embodiment, the information verification module 603 is further used to determine whether the target upgrade node passes the preset download verification;

[0104] The information verification module 603 is further configured to obtain target version information corresponding to the software upgrade package of the target upgrade node based on the flash list if the target upgrade node passes the preset download verification;

[0105] The information verification module 603 is further used to perform version consistency verification according to the target version information.

[0106] Optionally, in this embodiment, the information verification module 603 is further used to obtain installation verification information corresponding to the target upgrade node;

[0107] The information verification module 603 is further used to determine whether the target upgrade node passes the preset download verification based on the installation verification information.

[0108] Optionally, in this embodiment, the information verification module 603 is also used to send verification failure information to the target upgrade node if the target upgrade node fails to pass the preset download verification. When the target upgrade node receives the verification failure information, it stops the upgrade download operation and feeds back verification exception information to the upper computer.

[0109] Optionally, in this embodiment, the upgrade control module 604 is also used to send an upgrade success message to the target upgrade node when the inspection passes. When the target upgrade node receives the upgrade success message, it switches the current storage area to the corresponding target upgrade storage area according to the corresponding storage identifier for parallel data upgrade; the target upgrade storage area stores the target upgrade package.

[0110] Optionally, in this embodiment, the upgrade control module 604 is also used to send an upgrade failure message to the target upgrade node when the inspection fails. When the target upgrade node receives the upgrade failure message, it stops the partition switching operation and feeds back the upgrade exception information to the upper computer.

[0111] Optionally, in this embodiment, the list control module 601 is also used to add itself to the flash list when it detects that the upper computer sends a software upgrade package.

[0112] The multi-chip controller upgrade device provided by the present application adopts the multi-chip controller upgrade method in the above embodiment, and can solve the technical problem of multi-chip controller upgrade. Compared with the prior art, the beneficial effects of the multi-chip controller upgrade device provided by the present application are the same as the beneficial effects of the multi-chip controller upgrade method provided by the above embodiment, and other technical features in the multi-chip controller upgrade device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0113] The present application provides a multi-chip controller upgrade device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the multi-chip controller upgrade method in the above-mentioned embodiment one.

[0114] Reference below Figure 7 , which shows a schematic diagram of the structure of a multi-chip controller upgrade device suitable for implementing an embodiment of the present application. The multi-chip controller upgrade device in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The multi-chip controller upgrade device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0115] like Figure 7 As shown, the multi-chip controller upgrade device may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the multi-chip controller upgrade device are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the multi-chip controller upgrade device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a multi-chip controller upgrade device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or provided instead.

[0116] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a multi-chip controller upgrade program product, which includes a multi-chip controller upgrade program carried on a computer-readable medium, and the multi-chip controller upgrade program contains program code for executing the method shown in the flowchart. In such an embodiment, the multi-chip controller upgrade program can be downloaded and installed from the network through a communication device, or installed from a storage device 1003, or installed from ROM1002. When the multi-chip controller upgrade program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0117] The multi-chip controller upgrade device provided by the present application adopts the multi-chip controller upgrade method in the above embodiment, which can solve the technical problem that the reliability of multi-chip controller upgrade and the time consumption of upgrade cannot be taken into account at the same time. Compared with the prior art, the beneficial effects of the multi-chip controller upgrade device provided by the present application are the same as the beneficial effects of the multi-chip controller upgrade method provided by the above embodiment, and the other technical features in the multi-chip controller upgrade device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0118] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0119] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0120] The present application provides a storage medium having computer-readable program instructions (ie, a multi-chip controller upgrade program) stored thereon, wherein the computer-readable program instructions are used to execute the multi-chip controller upgrade method in the above-mentioned embodiment.

[0121] The storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0122] The storage medium may be included in the multi-chip controller upgrade device; or may exist independently without being assembled into the multi-chip controller upgrade device.

[0123] The storage medium carries one or more programs. When the one or more programs are executed by the multi-chip controller upgrade device, the multi-chip controller upgrade device is enabled to upgrade the multi-chip controller.

[0124] The multi-chip controller upgrade program code for performing the operations of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0125] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and multi-chip controller upgrade program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0126] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0127] The readable storage medium provided by the present application is a storage medium, which stores computer-readable program instructions (i.e., a multi-chip controller upgrade program) for executing the above-mentioned multi-chip controller upgrade method, and can solve the technical problem that the reliability of the multi-chip controller upgrade and the time-consuming upgrade cannot be taken into account at the same time. Compared with the prior art, the beneficial effects of the storage medium provided by the present application are the same as the beneficial effects of the multi-chip controller upgrade method provided by the above-mentioned embodiment, and will not be repeated here.

[0128] The above are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A multi-chip controller upgrade method, characterized in that: The method is applied to a multi-chip controller, the controller includes a chip as a master node and a plurality of chips as slave nodes, the method is executed by the chip master node, and the method includes: When receiving the upgrade startup information, the slave node to be verified corresponding to the upgrade startup information is added to the flash list; the upgrade startup information is generated by the slave node to be verified when receiving the software upgrade package sent by the host computer; When the preset upgrade time is reached, obtaining the target upgrade node contained in the flash list; Performing a preset version check on the target upgrade package corresponding to the target upgrade node based on the flash list; When the verification passes, the target upgrade node is controlled to perform parallel data upgrade based on the target upgrade package.

2. The multi-chip controller upgrade method according to claim 1, characterized in that: The step of performing a preset version check on the target upgrade package corresponding to the target upgrade node based on the flash list includes: Determine whether the target upgrade node passes the preset download verification; If the target upgrade node passes the preset download verification, obtaining the target version information corresponding to the software upgrade package of the target upgrade node based on the flash list; A version consistency check is performed according to the target version information.

3. The multi-chip controller upgrade method according to claim 2, characterized in that: The step of determining whether the target upgrade node passes the preset download verification includes: Obtaining installation verification information corresponding to the target upgrade node; Based on the installation verification information, it is determined whether the target upgrade node passes the preset download verification.

4. The multi-chip controller upgrade method according to claim 3, characterized in that: After determining whether the target upgrade node passes the preset download verification, the method further includes: If the target upgrade node fails the preset download verification, verification failure information is sent to the target upgrade node. When the target upgrade node receives the verification failure information, it stops the upgrade download operation and feeds back verification abnormality information to the upper computer.

5. The multi-chip controller upgrade method according to claim 1, characterized in that: The step of controlling the target upgrade node to perform parallel data upgrade based on the target upgrade package when the verification passes includes: When the verification passes, an upgrade success message is sent to the target upgrade node. When the target upgrade node receives the upgrade success message, it switches the current storage area to the corresponding target upgrade storage area according to the corresponding storage identifier for parallel data upgrade; the target upgrade storage area stores the target upgrade package.

6. The multi-chip controller upgrade method according to claim 1, characterized in that: After performing a preset version check on the target upgrade package corresponding to the target upgrade node based on the flash list, the method further includes: When the check fails, an upgrade failure message is sent to the target upgrade node. When the target upgrade node receives the upgrade failure message, it stops the partition switching operation and feeds back upgrade abnormality information to the upper computer.

7. The multi-chip controller upgrade method according to claim 1, characterized in that: When the preset upgrade time is reached, before obtaining the target upgrade node included in the flash list, the method further includes: When it detects that the host computer sends a software upgrade package, it adds itself to the flash list.

8. A multi-chip controller upgrade device, characterized in that: The multi-chip controller upgrading device comprises: A list control module is used to add the slave node to be verified corresponding to the upgrade startup information to the flash list when receiving the upgrade startup information; the upgrade startup information is generated by the slave node to be verified when receiving the software upgrade package sent by the host computer; A node determination module, used for obtaining the target upgrade node included in the flash list when the preset upgrade time is reached; An information verification module, configured to perform a preset version verification on a target upgrade package corresponding to the target upgrade node based on the flash list; The upgrade control module is used to control the target upgrade node to perform parallel data upgrade based on the target upgrade package when the verification is passed.

9. A multi-chip controller upgrade device, characterized in that: The multi-chip controller upgrade device includes: a memory, a processor, and a multi-chip controller upgrade program stored in the memory and executable on the processor, wherein the multi-chip controller upgrade program is configured to implement the steps of the multi-chip controller upgrade method according to any one of claims 1 to 7.

10. A storage medium, characterized in that: The storage medium is a storage medium on which a multi-chip controller upgrade program is stored. When the multi-chip controller upgrade program is executed by a processor, the steps of the multi-chip controller upgrade method according to any one of claims 1 to 7 are implemented.

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