Distributed processing method and device for neural mimicry computing chip and storage medium

Abstract

The invention relates to the technical field of neural mimicry computing chips, and discloses a distributed processing method and device for a neural mimicry computing chip and a storage medium. The method comprises the following steps: carrying out characteristic decomposition on a calculation task of a neural mimicry calculation chip to obtain a task coding vector; performing working state acquisition on the neuron core to obtain a core state matrix; inputting the task coding vector and the core state matrix into an initial deep reinforcement learning network to generate a resource allocation strategy; performing sequence reconstruction on the resource allocation strategy, and outputting a mapping scheme of a neuron core and a calculation task; a synaptic connection weight is configured according to a mapping scheme, a calculation task is converted into a pulse signal sequence, and the pulse signal sequence is transmitted and executed among neuron cores through an asynchronous event triggering mechanism; and calculating a synaptic weight update gradient to carry out parameter optimization to obtain a target deep reinforcement learning network. The resource utilization rate and the processing efficiency of the neural mimicry computing chip are improved, and the energy consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of neuromorphic computing chips, and in particular to a distributed processing method, device and storage medium for a neuromorphic computing chip. Background Art

[0002] With the rapid development of artificial intelligence technology, traditional von Neumann architecture computing chips face serious power consumption and performance bottlenecks when processing large-scale neural network calculations. This is mainly due to the separation of computing units and storage units in traditional architectures, and the frequent transmission of data between the two, resulting in excessive energy consumption. At the same time, the serial processing method also limits the improvement of computing efficiency. To solve this problem, neuromorphic computing chips came into being. It imitates the working mechanism of the human brain and uses a storage-computing integrated architecture and an asynchronous event-driven mechanism to process information. However, current neuromorphic computing chips still have problems such as low resource scheduling efficiency, unbalanced task allocation, and high communication overhead between cores in distributed task processing scenarios, which seriously affects the overall performance and energy efficiency of the chip.

[0003] Especially when dealing with multi-task parallel computing, how to effectively allocate computing resources, balance the load of processing cores, reduce communication overhead, and how to dynamically adjust processing strategies according to task characteristics are all key technical issues that need to be solved. Existing task scheduling methods often fail to fully utilize the computing resources of neuromorphic chips, and cannot effectively respond to dynamically changing computing needs. Summary of the invention

[0004] The present invention provides a distributed processing method, device and storage medium for a neuromorphic computing chip, which improves the resource utilization and processing efficiency of the neuromorphic computing chip and reduces energy consumption.

[0005] In a first aspect, the present invention provides a distributed processing method for a neuromorphic computing chip, the distributed processing method for the neuromorphic computing chip comprising: Performing feature decomposition on the computing tasks of the neuromorphic computing chip, establishing a task topology graph, and performing message passing aggregation operation on the task topology graph to obtain a task encoding vector; Collect the working status of the neuron core in the neuromorphic computing chip and obtain the core state matrix including synaptic weight distribution, neuron activation threshold, and storage and computing unit occupancy rate; Input the task encoding vector and the core state matrix into an initial deep reinforcement learning network, construct an action value function based on an Actor-Critic architecture, and generate a resource allocation strategy; Reconstructing the resource allocation strategy in sequence, calculating the temporal dependencies between tasks, and outputting a mapping scheme between neuron cores and computing tasks; Configuring synaptic connection weights according to the mapping scheme, converting the computing task into a pulse signal sequence, and transmitting and executing between the neuron cores through an asynchronous event triggering mechanism; The processing results of the pulse signal sequence are collected, the synaptic weight update gradient is calculated, and the action value function of the initial deep reinforcement learning network is optimized to obtain the target deep reinforcement learning network.

[0006] In a second aspect, the present invention provides a distributed processing device of a neuromorphic computing chip, wherein the distributed processing device of the neuromorphic computing chip comprises: A decomposition module is used to perform feature decomposition on the computing tasks of the neuromorphic computing chip, establish a task topology graph, and perform message passing aggregation operation on the task topology graph to obtain a task encoding vector; The acquisition module is used to collect the working status of the neuron core in the neuromorphic computing chip and obtain the core state matrix including synaptic weight distribution, neuron activation threshold, and storage and computing unit occupancy rate; A construction module, used for inputting the task encoding vector and the core state matrix into an initial deep reinforcement learning network, constructing an action value function based on an Actor-Critic architecture, and generating a resource allocation strategy; A reconstruction module, used to sequentially reconstruct the resource allocation strategy, calculate the temporal dependencies between tasks, and output a mapping scheme between neuron cores and computing tasks; An execution module, configured to configure synaptic connection weights according to the mapping scheme, convert the computing task into a pulse signal sequence, and transmit and execute the sequence between the neuron cores through an asynchronous event triggering mechanism; The optimization module is used to collect the processing results of the pulse signal sequence, calculate the synaptic weight update gradient, and optimize the parameters of the action value function of the initial deep reinforcement learning network to obtain the target deep reinforcement learning network.

[0007] A third aspect of the present invention provides a distributed processing device for a neuromorphic computing chip, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor calls the instructions in the memory so that the distributed processing device of the neuromorphic computing chip executes the above-mentioned distributed processing method of the neuromorphic computing chip.

[0008] A fourth aspect of the present invention provides a computer-readable storage medium, which stores instructions that, when executed on a computer, enable the computer to execute the above-mentioned distributed processing method of the neuromorphic computing chip.

[0009] In the technical solution provided by the present invention, a graph neural network is introduced to conduct an in-depth analysis of task features and dependencies, and a deep reinforcement learning network is combined to realize dynamic optimization allocation of computing resources. An asynchronous event trigger mechanism is used to perform parallel processing of tasks, and data transmission overhead is reduced based on a storage-computing integrated architecture. At the same time, through an adaptive parameter optimization method, online learning and optimization of the deep reinforcement learning network are realized, so that the system can dynamically adjust the processing strategy according to the real-time load conditions. This method significantly improves the resource utilization and processing efficiency of neuromorphic computing chips, reduces energy consumption, enhances the system's adaptability in complex computing environments, and provides an efficient solution for large-scale neural network computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0011] Figure 1 A schematic diagram of a distributed processing method for a neuromorphic computing chip provided in an embodiment of the present application; Figure 2 A schematic block diagram of the structure of a distributed processing device of a neuromorphic computing chip provided in an embodiment of the present application; Figure 3 A schematic block diagram of the structure of a distributed processing device of a neuromorphic computing chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change based on actual conditions.

[0014] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0015] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0016] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0017] See also Figure 1 , Figure 1 A schematic diagram of a distributed processing method for a neuromorphic computing chip provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the distributed processing method of the neuromorphic computing chip provided in the embodiment of the present application includes steps S100 to S600.

[0018] Step S100, feature decomposing the computing task of the neuromorphic computing chip, establishing a task topology graph, and performing message passing aggregation operation on the task topology graph to obtain a task encoding vector; It is understandable that the execution subject of the present invention may be a distributed processing device of a neuromorphic computing chip, or may be a terminal or a server, which is not specifically limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0019] Specifically, the computing tasks of the neuromorphic computing chip are collected for timing features, and task features such as task arrival time, required number of neurons, number of synaptic connections, and data flow are extracted. These features provide basic information for each computing task and help identify the computing requirements and resource consumption of the task. Data dependency analysis is performed on the task feature set to analyze the data transmission relationship and computing dependency between tasks, and calculate the dependencies between tasks. The dependencies between tasks are established by determining the input and output data flows and execution order between tasks. Based on the dependencies between tasks, a task topology graph is constructed. The task topology graph is a directed graph structure in which each node represents a computing task, and the edges in the graph represent the dependencies between tasks. The feature set of the task is mapped to the attributes of the graph nodes, and the attributes of the nodes include information such as the computing requirements and required resources of the task. At the same time, the dependency strength between tasks is determined by calculating the amount of data transmission or the transmission frequency between tasks, so that the dependencies are mapped to the edge weights in the graph to obtain a specific task topology graph. Multi-head attention calculation is performed on the nodes in the task topology graph. This process is similar to the application of the attention mechanism in the graph neural network, which enables the model to focus on the key features of each task node. Through the multi-head attention mechanism, each node can not only focus on its own information, but also on the information of the neighboring nodes connected to it, thereby dynamically adjusting its representation ability. The node attention features are input into the graph convolution layer. In the graph convolution layer, the features of adjacent nodes are weighted and summed through the message aggregation function to enhance the correlation between tasks and extract the hidden layer representation of the node. The node hidden layer representation is a high-dimensional representation obtained by combining its own and neighborhood information, which can effectively capture the complex relationship and information flow between tasks. The global features of the graph are calculated based on the node hidden layer representation. The features of all nodes are aggregated, and the pooling operation is used to reduce the dimension and integrate the important information of the nodes in the graph. At the same time, the structural information of the graph is transformed in dimension, and the features of the task are mapped to a target space through a fully connected neural network. Through nonlinear transformation, these features are mapped to a low-dimensional space to obtain a compressed feature vector, which effectively represents the overall requirements and behavior patterns of the task in the neuromorphic computing chip. The compressed feature vector and the node hidden layer representation are feature fused to improve the expression ability of the task encoding vector. Feature fusion is achieved through residual connections, which can retain the original feature information and combine the compressed feature vector with the node hidden layer representation through addition operations to obtain the encoding vector of the task.

[0020] Step S200, collecting the working status of the neuron core in the neuromorphic computing chip to obtain a core state matrix including synaptic weight distribution, neuron activation threshold, and storage and computing unit occupancy rate; Specifically, the synaptic connections of the neuron cores in the neuromorphic computing chip are scanned in parallel to extract information such as the synaptic weight, connection state, and transmission bandwidth of each neuron core. By calculating the weight density of the synaptic connection features, a synaptic weight distribution map is obtained. The synaptic weight distribution map shows the connection strength and information transmission density between neurons, which helps to analyze the communication load and execution efficiency of neurons. The neuron state of each neuron core is sampled to obtain the activation threshold set of the neuron. The activation threshold is a key parameter for each neuron to determine whether to trigger, and the discharge frequency of the neuron is affected by this threshold. Sampling these thresholds and analyzing them helps to understand the working state of the neuron and its performance in task execution. State mapping is performed according to the activation threshold set, and the pulse triggering conditions and corresponding discharge frequency of the neuron core are obtained through quantitative calculation. Quantitative calculation can help evaluate the activation state of the neuron and reveal whether the neuron is in an overloaded or idle state. The workload analysis is performed through the obtained threshold distribution sequence and the storage and computing unit of the neuron core to calculate the load state value. The load state value reflects the working intensity and resource consumption of the neuron core at a certain moment. After the load state value is input into the adaptive sampler, the real-time occupancy of the storage and computing unit is captured by dynamically adjusting the sampling frequency to obtain the occupancy sequence. The adaptive sampler adjusts the sampling frequency according to the real-time changing load conditions, thereby improving the sampling efficiency and making the collected data more in line with the actual working state of the chip. The occupancy sequence is feature integrated with the synaptic weight distribution map. Through multi-dimensional matrix operations, these feature data are merged and processed to obtain a state feature matrix, which contains information such as synaptic weight distribution, neuron activation threshold, and occupancy of storage and computing units, reflecting the working state of the neuron core. Based on the state feature matrix and threshold distribution sequence, data fusion operations are performed. The state information from multiple data sources is merged through tensor operations, and all feature data are fused together to obtain the core state matrix.

[0021] Step S300: Input the task encoding vector and the core state matrix into the initial deep reinforcement learning network, construct an action value function based on the Actor-Critic architecture, and generate a resource allocation strategy; Specifically, the task encoding vector and the core state matrix are dimensionally aligned, the task features and the core state data of the chip are integrated into a unified input format, and the data from different sources are mapped to a 128-dimensional input feature space by feature reorganization to obtain the state input vector. The state input vector is input into the Actor network, which models the action space according to the computing power of neurons and synapses and outputs a preliminary action distribution. The preliminary action represents different resource allocation schemes that may be taken under the current resource state. In order to ensure the feasibility of the action, the feasibility constraint is executed on the initial action distribution. Based on the hardware resource constraints of the system, such as 16PB / s memory bandwidth and 3.5PB / s inter-core communication bandwidth, resource allocation verification is performed to ensure that the generated actions are executable under the actual hardware resource conditions, and a valid action set is obtained. The valid action set contains all resource allocation schemes that meet the hardware constraints, ensuring that subsequent calculations can be efficiently executed within the limits of hardware capabilities. The state input vector and the valid action set are input into the Critic network. The task of the Critic network is to calculate the value evaluation of the state. Based on 380 trillion synaptic operations and 240 trillion neuron operations, the Critic network can estimate the value of each state and provide a quantitative assessment of the effect of different resource allocation strategies. The value evaluation function is calculated based on the mapping of the current state and the action set, providing key feedback for the policy update of the Actor network. The value evaluation function is subjected to temporal difference (TD) operation, and the instant reward is constructed by calculating the 192KB cache utilization of each neuron core. The instant reward reflects the instant effect of the current state and action combination, helping to evaluate the pros and cons of different resource allocation schemes. By calculating the TD error, the deviation between the current strategy and the expected strategy is measured, so as to perform gradient updates on the policy distribution of the Actor network. The gradient update is optimized in an asynchronous event-driven manner to improve the probability of action selection and ensure that the resource allocation strategy continues to move towards the optimal. After the policy update is completed, the updated policy is input into the resource scheduler, and the resource scheduler performs actual resource allocation according to the policy. In this process, the scheduler performs action mapping based on the configuration space of 4096 neuron states to obtain a set of scheduling schemes. The scheduling scheme set contains multiple potential resource allocation schemes, each of which corresponds to different computing task allocation and resource utilization methods. In order to select the best scheme, these schemes are evaluated for performance, and the evaluation criteria include indicators such as the occupancy rate of storage and computing units and the synaptic connection load. By calculating these indicators and sorting the schemes, the optimal resource allocation scheme is finally selected to obtain an effective resource allocation strategy.

[0022] Step S400, reconstructing the resource allocation strategy in sequence, calculating the temporal dependencies between tasks, and outputting a mapping scheme between neuron cores and computing tasks; Specifically, the resource allocation strategy is sequence encoded. By using the Seq2Seq encoder, the scheduling requests of multiple concurrent tasks are converted into input sequences. The Seq2Seq model converts complex task allocation relationships into task timing vectors by encoding scheduling requests from the perspective of timing and tasks. The task timing vector is passed into the encoder of the recurrent neural network (RNN) as input. The design of the RNN can capture the dependencies between tasks in the time series. The data flow dependencies between tasks are constructed by extracting timing features to obtain a timing feature matrix. Hierarchical clustering is performed on the timing feature matrix. The hierarchical clustering method divides task groups based on the data flow direction and transmission bandwidth requirements between tasks. By analyzing the mutual dependencies and resource requirements between tasks, the tasks are effectively organized into a hierarchical structure to obtain a hierarchical dependency tree. The hierarchical dependency tree presents the priorities and dependencies between tasks, which is helpful for priority allocation and resource optimization in subsequent task scheduling. Based on the hierarchical dependency tree, an attention weight matrix is ​​constructed, and the task priority score is calculated through the attention mechanism in the RNN decoder. The attention mechanism allows the model to automatically focus on the most relevant other task features when processing each task, thereby allocating resources more accurately. By calculating the task priorities, a scheduling priority sequence is obtained, which determines the execution order of tasks and the priority of resource allocation. In this process, the generation of the scheduling priority sequence is dynamic and can be adjusted as the dependencies between tasks change. The scheduling priority sequence is matched with the computing resources of the neuron core. Based on the synaptic connection state and the storage and computing unit occupancy rate of each neuron core, resources are matched to ensure that tasks can be executed on the appropriate core and obtain an effective core allocation plan. The core allocation plan is input into the timing verification module, and the rationality of the task execution timing is verified by the decoder of the recurrent neural network. The decoder can simulate the execution process of the task and check whether there is a conflict in the actual execution of the task. By verifying the execution timing of the task, an execution timing diagram is obtained to show the execution order of the task at different time nodes. Conflict detection is performed on the execution timing diagram. Resource competition is analyzed based on the neuron activation threshold and synaptic weight distribution. If resource competition or conflict is found between tasks, a conflict elimination strategy is generated. The conflict elimination strategy analyzes the conflicts between tasks and formulates a strategy to avoid resource conflicts, ensuring that all tasks can be executed smoothly without delays due to insufficient resources or conflicts. The conflict elimination strategy includes means such as task rescheduling and resource reallocation, which help to re-plan the execution order of tasks and make reasonable adjustments according to the current resource conditions. The core allocation plan is adjusted through the conflict elimination strategy to form the final mapping plan between neuron cores and computing tasks. This mapping plan ensures the optimal utilization of resources through task rescheduling and resource reallocation, while avoiding conflicts or delays in task execution.

[0023] Step S500: configure synaptic connection weights according to the mapping scheme, convert the computing task into a pulse signal sequence, and transmit and execute it between neuron cores through an asynchronous event triggering mechanism; Specifically, the mapping scheme is analyzed for connection relationships. By analyzing the computing tasks and data transmission requirements of each neuron core, a connection topology is constructed to reflect the relationship between the tasks and the neuron cores. Based on the connection topology, a synaptic connection matrix is ​​generated to show the connection between different neurons and their interaction paths. After the synaptic connection matrix is ​​input into the weight configurator, the weight configurator configures the weight of each synapse according to the information transmission intensity of each connection. This process is completed through an event-based spiking neural network, in which the weight of each connection reflects the efficiency and priority of information transmission, and the synaptic weight distribution is obtained. The synaptic weight distribution is normalized to ensure that the weights of all synapses are compared and adjusted on a uniform scale. Weight scaling is performed based on the neuron activation threshold and the storage unit occupancy rate to maintain the balance and stability of the calculation under different resource usage conditions. The scaled weights are standardized to form standardized weights suitable for neural pulse coding. After the standardized weights are input into the task coding module, they are converted into timing signals by pulse frequency modulation to generate pulse coding sequences. The pulse coding sequence is a timing signal containing task load information, and the execution intensity and order of the task are reflected by the pulse frequency. Event-triggered mapping is performed on the pulse coding sequence. Since the discharge characteristics of neurons have certain delays and refractory periods, trigger thresholds and refractory period parameters are set for each pulse signal to ensure that the pulse signal is triggered at the right time point and avoid repeated triggering. Through these parameters, a set of trigger rules is obtained to help the system coordinate the activities between different neurons to ensure the synchronization and correctness of the signal. After the trigger rule set is input into the asynchronous controller, the asynchronous controller can adjust the execution timing of multiple neuron cores in an event-driven manner. In this way, the asynchronous controller can dynamically control the work of different cores so that the computing tasks are coordinated and executed between the cores to avoid conflicts and resource waste. The pulse signals in the execution control sequence are propagated and routed. The path and strength of signal transmission are determined based on the synaptic connection weight. By calculating the weight of the synaptic connection, it is determined which paths require more computing resources, thereby optimizing the transmission efficiency of the signal and ensuring that the pulse signal can be quickly and accurately transmitted to the target neuron. According to the signal transmission scheme, data paths are established between the neuron cores, which can efficiently transmit and process pulse signals. Through the asynchronous parallel mechanism, the transmission and calculation of pulse signals are realized between multiple neuron cores to complete the processing of computing tasks. The asynchronous parallel mechanism enables neuromorphic computing chips to maintain efficient resource utilization and computing efficiency while executing multiple tasks simultaneously.

[0024] Step S600: collect the processing results of the pulse signal sequence, calculate the synaptic weight update gradient, optimize the parameters of the action value function of the initial deep reinforcement learning network, and obtain the target deep reinforcement learning network.

[0025] Specifically, the processing results of the pulse signal sequence are statistically analyzed. By statistically analyzing the computing and communication performance of the 128 neuron cores in the neuromorphic computing chip, the execution efficiency of the system is evaluated, and a performance sampling matrix is ​​obtained, which contains the performance of each neuron core when executing computing tasks, such as computing speed, communication delay and other indicators. By comparing the target task completion time with the actual execution time, a performance loss function is constructed to quantify the performance loss of the system during the actual execution process. The calculation of the loss function can reflect the shortcomings of the system when processing tasks and provide a basis for subsequent optimization. Based on the performance loss function, the performance sampling matrix is ​​calculated to obtain a loss vector. The loss vector reveals the performance bottlenecks and potential problems of the system through gradient analysis, and helps to construct the gradient update direction. Combined with the synaptic weight distribution and the neuron activation threshold, the gradient update strategy is optimized to obtain the weight adjustment matrix. Based on the weight adjustment matrix, the storage and computing unit is updated in state. This process constructs the optimization target by calculating the workload and resource occupancy rate of each storage and computing unit, and obtains the state update vector. The state update vector provides a basis for dynamic adjustment of resource scheduling and task allocation of the storage and computing unit, ensuring that the system can perform optimal resource configuration and computing task allocation under different workloads. After the state update vector is input to the Actor network, the Actor network iteratively optimizes the policy parameters of the action value function through a dynamic programming algorithm. The dynamic programming method can continuously adjust the policy through feedback from multiple iterative calculations, and gradually find the optimal resource allocation and task execution policy. During the optimization process, the optimization policy generated by the Actor network needs to be evaluated by the Critic. The Critic network calculates the value evaluation score of the state-action pair according to the current policy and constructs a value network to evaluate the quality of the current policy. Through the calculated value evaluation score, the Critic network can provide more accurate feedback to the Actor network to help it adjust its policy. At this time, the update amount of the value function is the result of the Critic evaluation, which represents the deviation of the current policy from the ideal policy. The value function update amount is input into the parameter optimizer, and the weight parameters of the deep reinforcement learning network are updated through the stochastic gradient descent method (SGD). SGD is an optimization algorithm that gradually minimizes the loss function and improves the network performance by adjusting the weight parameters in each iteration. The updated weight parameter set is the optimized parameter set, which provides the latest resource allocation and computing task scheduling strategy for the deep reinforcement learning network. By optimizing the parameter set, the parameters of the initial deep reinforcement learning network are updated so that the network structure gradually converges to the optimal solution. The update of network parameters is completed through the back propagation algorithm, which adjusts the weights and biases of each layer of the network according to the gradient of the error to optimize the network structure. After multiple iterations, the target deep reinforcement learning network is finally obtained, which can better adapt to the resource management requirements of neuromorphic computing chips and achieve efficient task scheduling and resource allocation.

[0026] In the embodiment of the present invention, a graph neural network is introduced to conduct an in-depth analysis of task characteristics and dependencies, and a deep reinforcement learning network is combined to achieve dynamic optimization allocation of computing resources. An asynchronous event trigger mechanism is used to perform parallel processing of tasks, and data transmission overhead is reduced based on a storage-computing integrated architecture. At the same time, through an adaptive parameter optimization method, online learning and optimization of the deep reinforcement learning network are achieved, so that the system can dynamically adjust the processing strategy according to the real-time load conditions. This method significantly improves the resource utilization and processing efficiency of neuromorphic computing chips, reduces energy consumption, enhances the system's adaptability in complex computing environments, and provides an efficient solution for large-scale neural network computing.

[0027] In a specific embodiment, the process of executing step S100 may specifically include the following steps: Collect timing features of computing tasks of neuromorphic computing chips, extract task feature sets including task arrival time, number of neurons required, number of synaptic connections, and data flow, perform data dependency analysis on the task feature sets, and calculate task dependencies based on data transmission relationships between tasks; A directed graph structure is constructed based on task dependencies, the task feature set is mapped to graph node attributes, and the dependency strength matrix is ​​mapped to edge weights to obtain a task topology graph. Perform multi-head attention calculation on the nodes in the task topology graph to obtain the node attention features, and input the node attention features into the graph convolution layer. Perform weighted sum operation on the features of adjacent nodes through the message aggregation function to obtain the node hidden layer representation; According to the global features of the computation graph represented by the node hidden layer, the node features are pooled and dimensionally transformed to obtain the graph structure code, and the graph structure code is input into the fully connected neural network. The features are mapped to the target dimensional space through nonlinear transformation to obtain the compressed feature vector. The compressed feature vector and the node hidden layer representation are fused, and the task encoding vector is obtained through residual connection.

[0028] Specifically, the timing features of the computing tasks are collected, and a set of important task feature sets are extracted. These feature sets include task arrival time, the number of neurons required, the number of synaptic connections, and the data flow direction. The task arrival time refers to the timestamp when the task starts to execute, reflecting the time information of task scheduling. The number of neurons required refers to the number of neuron cores required to execute the task, reflecting the demand for task computing resources. The number of synaptic connections indicates the connection strength between the task and the neuron core, while the data flow direction describes the data transmission path in the task. Data dependency analysis is performed on the task feature set, and the task dependency is calculated based on the data transmission relationship between tasks. The data transmission relationship between tasks is established by calculating the dependency of the input and output data of the tasks. For example, if task B requires the output of task A as input, then task B depends on task A. The dependency relationship between these tasks is represented by a dependency strength matrix, in which each element represents the dependency strength between two tasks. The dependency strength is calculated by the following formula: ; Among them, depend Indicates the task To the task The strength of dependence, It's a task and tasks The time delay between them. The longer the delay time, the lower the dependency strength. A directed graph structure is constructed based on task dependencies. Each node of the graph represents a task, and each edge represents the dependency between tasks. The set of task features is mapped to graph node attributes. The attributes of each node include information such as task arrival time, the number of neurons required, the number of synaptic connections, and the direction of data flow, which can comprehensively describe the characteristics of the task. The dependency strength matrix is ​​mapped to edge weights, which reflect the strength of the dependencies between tasks. Multi-head attention calculation is performed on the nodes in the task topology graph. The multi-head attention mechanism is a method of capturing multiple dependencies between different nodes in the graph through multiple attention heads. Multi-head attention calculation helps to extract important features of nodes, especially to capture complex dependencies between tasks. For each node , whose attention feature is calculated by the following formula: ; in, Representation Node The set of neighbor nodes of Is a node and neighbor nodes The attention weights between Is a node The feature vector of . Attention weight Calculated by: ; in, Representation Node and nodes The similarity between them is calculated by dot product or other similarity metrics. Through multi-head attention calculation, the attention features of each node are obtained. These features can reflect the degree of association between the node and other nodes. The attention features of the node are input into the graph convolution layer. The graph convolution network performs weighted summation operation on the features of adjacent nodes through the message aggregation function to improve the expressive power of the node representation. Assume that the node The hidden layer is represented as , the update rule of the graph convolutional layer is expressed as: ; in, is the weight matrix of the graph convolutional layer, is the activation function, Representation Node The set of neighbor nodes of a node. Through the aggregation process, the node hidden layer representation can fuse key information from neighboring nodes. The global features of the graph are calculated based on the node hidden layer representation. The global features are obtained by performing pooling operations (such as maximum pooling or average pooling) and dimensionality conversion on the node features. The pooling operation can compress node features, reduce redundant information, and extract the global information of the graph. The pooled features are nonlinearly transformed through a fully connected neural network to map the features of the graph to the target dimensional space to obtain a compressed feature vector. In order to enhance the representation ability of the graph, feature fusion is performed on the compressed feature vector and the node hidden layer representation. Through residual connection, the node hidden layer representation is combined with the compressed feature vector to retain the local information of the node and the global information of the graph. The fusion process is implemented by the following formula: ; in, represents the fused task encoding vector, is the compressed feature vector, is the node hidden layer representation. The introduction of residual connections enables the model to be effectively trained and optimized while avoiding information loss during transmission. The task encoding vector obtained after feature fusion is used as the input for task scheduling and resource allocation, providing an effective basis for the distributed processing of neuromorphic computing chips.

[0029] In a specific embodiment, the process of executing step S200 may specifically include the following steps: The synaptic connections of the neuron cores in the neuromorphic computing chip are scanned in parallel, and the synaptic weight, connection state and transmission bandwidth of each core are extracted to obtain the synaptic connection characteristics; The weight density of synaptic connection features is calculated to obtain a weight distribution map, and the neuron state of each neuron core is sampled to obtain an activation threshold set; Based on the activation threshold set, the state mapping is performed to quantify the pulse triggering conditions and discharge frequency of the neuron core to obtain the threshold distribution sequence, and the workload of the threshold distribution sequence and the storage and calculation unit is analyzed to obtain the load state value; The load state value is input into the adaptive sampler, and the real-time occupancy of the storage and computing unit is captured by dynamically adjusting the sampling frequency to obtain the occupancy sequence. The occupancy sequence and the weight distribution map are then feature integrated, and the state feature matrix is ​​constructed through multi-dimensional matrix operations. Data fusion is performed based on the state feature matrix and the threshold distribution sequence, and multi-source state information is merged through tensor operations to obtain the core state matrix.

[0030] Specifically, the synaptic connections in the neuron cores are scanned in parallel to extract key information such as the synaptic weight, connection state, and transmission bandwidth of each neuron core. This information constitutes the synaptic connection characteristics of the neuron core. Synaptic weight refers to the strength of the synapses connecting different neurons, the connection state reflects whether an effective connection is established between neurons, and the transmission bandwidth indicates the ability and speed of data transmission between neuron cores. The weight density of the synaptic connection characteristics is calculated to generate a weight distribution map. The weight density reflects the connection strength and resource occupancy between neuron cores by calculating the density of synaptic connections. For example, assuming the synaptic weight matrix is ,in Represents the neuron core and core The connection weight between them, the weight density is defined as: ; in, Represents the neuron core The total number of all connections, Reflecting neuronal core The weight density represents the connection strength and data transmission density between neuron cores. Through calculation, a weight distribution diagram is obtained to show the distribution characteristics of the connections between neuron cores in the entire neuromorphic computing chip. The neuron state of each neuron core is sampled to obtain the activation threshold set. The activation threshold refers to the minimum activation value of the neuron core to generate a pulse after receiving the input signal, which is related to the excitability of the neuron. Assume that the activation threshold of each neuron core is , the activation threshold set is the set of all neuron core activation thresholds, expressed as ,in Represents the total number of neuron cores. By sampling the threshold, the activity characteristics of the neuron core are obtained, which provides data support for the quantitative calculation of the pulse triggering conditions and discharge frequency. Based on the activation threshold set, state mapping is performed to quantify the pulse triggering conditions and discharge frequency of the neuron core. The pulse triggering condition refers to when the neuron core will emit a pulse, and the discharge frequency refers to the frequency at which the neuron core emits a pulse. In order to quantify these conditions, the following calculation formula is used: ; in, Represents the neuron core The discharge frequency, is the activation threshold of the core, Represents the core of the neuron Pass to core The synaptic signal strength is obtained by quantifying the pulse triggering conditions and discharge frequency to obtain the activity frequency distribution of each neuron core. At the same time, the workload of the threshold distribution sequence and the storage and calculation unit is analyzed to obtain the load state value. The load state value reflects the workload of the neuron core and takes into account the demand of the computing task on the neuron core resources. Assume that the load state value is calculated by the following formula: ; in, Indicates the task Neuronal core The computational requirements Represents the neuron core The resource availability of each neuron core is obtained through analysis, and these values ​​are used to determine the resource occupancy of the neuron core. The load state value is input into the adaptive sampler. The adaptive sampler captures the occupancy of the storage and computing units in real time by dynamically adjusting the sampling frequency to obtain the occupancy sequence. The occupancy refers to the resource occupancy degree of the storage and computing unit when performing a computing task, reflecting the resource consumption of the task. By continuously adjusting the sampling frequency, the adaptive sampler can accurately capture the resource occupancy dynamics of the storage and computing unit to ensure the accuracy and real-time nature of resource allocation. The occupancy sequence reflects the resource occupancy of the storage and computing unit at each moment, which can help adjust the resource allocation strategy to optimize the performance of the chip. The occupancy sequence and the weight distribution map are feature integrated, and the state feature matrix is ​​constructed through multi-dimensional matrix operations. The state feature matrix contains the load state information of the neuron core and integrates the characteristics of the occupancy and weight distribution. The occupancy sequence and the weight distribution map are integrated through the following matrix operations: state_matrix=weight_distribution occupancy_rate; Among them, state_matrix represents the state feature matrix, weight_distribution is the weight distribution of synaptic connections, and occupancy_rate is the occupancy rate sequence of storage and computing units. Through matrix operations, information from different sources is integrated to generate a comprehensive state feature matrix. Data fusion is performed based on the state feature matrix and the threshold distribution sequence. Multi-source state information is merged through tensor operations to obtain the core state matrix. Tensor operations are an efficient multi-dimensional data processing method that can effectively fuse feature information from different sources. Assume that the state feature matrix is , the threshold distribution sequence is , then the fused core state matrix M is expressed as: ; In this way, different types of state information are fused, and the generated core state matrix can fully reflect the working state of the neuron core.

[0031] In a specific embodiment, the process of executing step S300 may specifically include the following steps: Align the dimensions of the task encoding vector and the core state matrix, construct a 128-dimensional input feature space through feature reorganization, and obtain the state input vector; The state input vector is input into the Actor network, and the action space is modeled based on the computing power of neurons and synapses to obtain the initial action distribution. The feasibility constraints are then enforced on the initial action distribution. Resource allocation is verified based on the 16PB / s memory bandwidth and 3.5PB / s inter-core communication bandwidth to obtain the valid action set. The state input vector and the valid action set are input into the Critic network, and the state value is calculated based on 380 trillion synaptic operations and 240 trillion neuron operations to obtain the value evaluation function. Perform temporal difference operation on the value evaluation function, build instant rewards by calculating the 192KB cache utilization of each neuron core, obtain TD error, and perform gradient update on the policy distribution of the Actor network based on the TD error. Optimize the action selection probability in an asynchronous event-driven manner to obtain the updated policy. The update strategy is input into the resource scheduler, and action mapping is performed based on the configuration space of 4096 neuron states to obtain a set of scheduling schemes. Performance evaluation is performed on the scheduling scheme set, and the schemes are sorted by calculating the occupancy rate of storage and computing units and the synaptic connection load to obtain the resource allocation strategy.

[0032] Specifically, the dimensions of the task encoding vector and the core state matrix are aligned so that they can adapt to the input requirements of the deep reinforcement learning model. Assume that the dimension of the task encoding vector is , the dimension of the core state matrix is , then the two are combined into a 128-dimensional input feature space by feature recombination. Feature recombination is accomplished by standardizing, normalizing, or linearly mapping each feature. For example, the task encoding vector is mapped to dimension, and the core state matrix is ​​mapped to The two pieces of information are fused into a 128-dimensional input vector by concatenation or weighted summation. This input vector is the state input vector, which represents the task requirements and neuron core state of the chip at a specific moment. When the state input vector is input into the Actor network, the goal of the network is to model the action space based on the computing power of the neuron core and synapses. The core task of action space modeling is to allocate resources for each possible computing task to optimize the overall computing efficiency and performance. Assume that the computing power of the neuron core and the computing power of the synapse are represented by the vector and Represents that the action space is modeled as: ; in, Represents the action distribution generated by the model, describing the probability of resource allocation between each task and the neuron core. Based on the memory bandwidth (16PB / s) and the inter-core communication bandwidth (3.5PB / s), the feasibility constraints are enforced on the initial action distribution. These bandwidth limitations have an important impact on the scheduling of computing tasks. Excessive memory or communication bandwidth requirements lead to inefficient task execution or system overload. The action distribution is adjusted according to the actual bandwidth. For example, if the memory requirement of task A is 5PB and the bandwidth limit is 16PB / s, then the action probability of the task should be affected by the bandwidth limitation and adjusted to a reasonable value. Based on this constraint, the effective action set is obtained. , contains all valid actions that can meet the bandwidth requirements. The state input vector and the valid action set are input to the Critic network. The goal of the Critic network is to evaluate the value of a given state and action, using a temporal difference learning method. The Critic network calculates the state value function based on the computing power of synapses (380 trillion operations) and neurons (240 trillion operations). , its formula is expressed as: ; in, Indicates status The value of is the discount factor, Indicates that at time step Instant rewards on is the maximum time step. The calculation of the immediate reward is closely related to the cache utilization of the neuron core. For example, assuming that the cache size of each neuron core is 192KB, the cache utilization is calculated by the following formula: ; in, Represents the neuron core The amount of cache used, This reflects the cache utilization of the core. By calculating the cache utilization of each neuron core, generating an immediate reward for each state, and calculating the TD error: ; The TD error represents the deviation of the current strategy in a given state and is used to adjust the strategy distribution of the Actor network. Based on the TD error, the strategy of the Actor network is optimized through gradient updates. The update formula is: ; in, Represents the parameters of the Actor network, is the learning rate, Indicates a given state Next select action The probability of action selection of the Actor network is optimized through asynchronous event-driven mode to obtain the updated strategy. The updated strategy is input into the resource scheduler. The goal of the scheduler is to schedule tasks according to the configuration space of 4096 neuron states. The configuration space represents the state combination of the neuron core when executing a task. Each combination corresponds to different resource requirements and computing power. The scheduler generates a corresponding set of scheduling solutions based on these state spaces. , each scheduling scheme contains detailed information on how to allocate resources to achieve optimal task execution. After obtaining the set of scheduling schemes, the scheduler evaluates the performance of these schemes. The evaluation indicators include the occupancy rate of the storage and computing units and the load of the synaptic connections. For example, the occupancy rate of the storage and computing units is expressed as: ; in, Represents the neuron core workload, Represents the neuron core By calculating these performance indicators, the scheduling schemes are sorted and the optimal resource allocation strategy is obtained.

[0033] In a specific embodiment, the process of executing step S400 may specifically include the following steps: Sequence encoding is performed on the resource allocation strategy. Based on the Seq2Seq encoder, the scheduling requests of multiple concurrent tasks are converted into input sequences to obtain task timing vectors. The task timing vector is input into the encoder of the recurrent neural network. The data flow dependency relationship between tasks is constructed through timing feature extraction to obtain a timing feature matrix. Hierarchical clustering is performed on the timing feature matrix to divide the task groups based on the data flow direction and transmission bandwidth requirements of adjacent tasks to obtain a hierarchical dependency tree. The attention weight matrix is ​​constructed based on the hierarchical dependency tree. The task priority scores are calculated through the attention mechanism in the decoder of the recurrent neural network to obtain the scheduling priority sequence. The scheduling priority sequence is then allocated to neuron cores. Resources are matched based on the synaptic connection state and storage and computing unit occupancy of each core to obtain the core allocation plan. The core allocation plan is input into the timing verification module, and the rationality of the task execution timing is verified through the decoder of the recurrent neural network to obtain the execution timing diagram. The execution timing diagram is then subjected to conflict detection, and resource competition analysis is performed based on the neuron activation threshold and synaptic weight distribution to obtain the conflict elimination strategy. The core allocation scheme is adjusted based on the conflict elimination strategy, and the mapping scheme between neuron cores and computing tasks is generated through task rearrangement and resource reallocation.

[0034] Specifically, the resource allocation strategy is sequence-encoded, and the scheduling requests of multiple concurrent tasks are converted into input sequences based on the Seq2Seq encoder. The scheduling requests of multiple concurrent tasks are converted into input sequences so that they can be processed by the deep learning model. The task scheduling requests in the resource allocation strategy are represented as a set of tasks. Assume that these tasks are , where each task It has multiple attributes, such as task arrival time, required computing resources, data flow direction, etc. In order to convert these task information into a form that the model can process, the Seq2Seq encoder is used. The role of the Seq2Seq encoder is to map the information sequence of these tasks to a fixed-length task timing vector , which can contain the dependencies between tasks and the timing information of scheduling requests. The Seq25eq encoder embeds the attributes of the task into a high-dimensional space, and then uses a recurrent neural network (RNN) to model the time series and output the task timing vector: ; in, Representation Task The Seq2Seq model converts these tasks into a task time series vector through the encoder The task time sequence vector is input into the encoder of the recurrent neural network (RNN). The encoder of the RNN captures the time sequence features between tasks and extracts the dependencies between tasks. These dependencies between tasks are represented by calculating the data flow dependencies between tasks. For example, suppose the task The input depends on the task The output of Representation Task and tasks The RNN encoder extracts these dependencies and forms a temporal feature matrix , which represents the dependency strength and order relationship between tasks. The time series feature matrix is ​​analyzed using a hierarchical clustering algorithm. Hierarchical clustering groups tasks according to the dependency relationship between tasks and the direction of data flow. Assume that the transmission bandwidth requirement between tasks is , then the hierarchical clustering algorithm is based on and Divide tasks into different task groups and form a hierarchical dependency tree , which represents the dependency structure between tasks. An attention weight matrix is ​​constructed based on the hierarchical dependency tree to optimize task scheduling. The attention mechanism helps the model focus on more important tasks during scheduling by assigning weights to tasks. For example, suppose the task in the hierarchical dependency tree The priority weight is , the priority of the task is calculated through the attention weight matrix: ; in, It is a task priority sequence calculated based on the hierarchical dependency tree and attention mechanism. The priority sequence reflects the importance and urgency of the task in the calculation process. Neuron cores are allocated to the scheduling priority sequence. The resource requirements and status of each neuron core, including the synaptic connection status and the storage unit occupancy rate, need to be optimized through task scheduling strategies. For example, the synaptic connection status of the neuron core is evaluated by the workload and bandwidth of the synapse, and the storage unit occupancy rate indicates the current load of the neuron core. If the task The computing requirements of the task are highly matched with the resources of the core, and the model assigns it to the core. The core allocation plan is obtained in this way, including the neuron core to which each task should be assigned and the specific resource usage of the core. In order to ensure the rationality of resource allocation, the core allocation plan is input into the timing verification module for verification. The timing verification module ensures that the execution order of tasks meets the constraints of system resources by analyzing the timing rationality of task execution. By inputting the core allocation plan into the decoder of the recurrent neural network, the model verifies the timing diagram of task execution to ensure that there will be no conflicts in task scheduling. For example, if the task and There is overlap in time and the resource requirements between them conflict with each other. The timing verification module identifies this problem through the conflict detection mechanism. The conflict detection algorithm is based on the neuron activation threshold and synaptic weight distribution, and calculates resource competition through the following formula: ; If a conflict exists, a conflict resolution strategy is designed based on the neuron activation threshold and synaptic weight distribution. Conflict resolution strategies include task rescheduling, resource reallocation, or adjusting the order of task execution. With the task If there is a resource conflict between them, we can adjust their execution order or move tasks Migrate to other idle cores to eliminate conflicts. After conflict elimination and resource reallocation, the core allocation plan is adjusted and the final mapping plan between neuron cores and computing tasks is generated. This mapping plan ensures that the computing resources of each task are reasonably allocated and conflicts during task execution are effectively avoided.

[0035] In a specific embodiment, the process of executing step S500 may specifically include the following steps: Analyze the connection relationship of the mapping scheme, build the connection topology based on the data transmission requirements of each neuron core, obtain the synaptic connection matrix, and input the synaptic connection matrix into the weight configurator. Calculate the information transmission strength of each connection through the event-based spiking neural network to obtain the synaptic weight distribution; Normalization is performed on the synaptic weight distribution, weight scaling is performed based on the neuron activation threshold and the storage unit occupancy rate to obtain the standardized weight, and the computing task is encoded into neural pulses based on the standardized weight, and the task load is converted into a timing signal through pulse frequency modulation to obtain a pulse coding sequence; Perform event-triggered mapping on the pulse coding sequence, set the trigger threshold and refractory period parameters based on the discharge characteristics of the neuron, obtain the trigger rule set, and input the trigger rule set into the asynchronous controller to coordinate the execution timing of multiple neuron cores in an event-driven manner to obtain the execution control sequence; The pulse signals in the execution control sequence are propagated and routed, the signal transmission path and strength are determined based on the synaptic connection weight, and a signal transmission scheme is obtained. According to the signal transmission scheme, a data path is established between the neuron cores, and the transmission and calculation of the pulse signals are completed through an asynchronous parallel mechanism to obtain the processing results of the pulse signal sequence.

[0036] Specifically, the data transmission requirements of each neuron core are analyzed and the connection topology is constructed. Neuron cores, numbered , each neuron core Each task has its corresponding task load and resource requirements, including computing power, memory bandwidth, storage unit occupancy, etc. There are complex data transmission relationships between these tasks, which are realized through synaptic connections. In order to reasonably map computing tasks and neuron cores, a synaptic connection matrix is ​​constructed. , where each element Indicates the core and core The construction of this matrix is ​​based on the data transmission requirements between tasks. Assuming that the task The output needs to be transferred to the task The bandwidth requirement for data transmission is expressed as ,therefore: ; in, Is a mapping function that can be based on bandwidth requirements Calculate the connection strength. In this way, we get the synaptic connection matrix , which can reflect the data transmission requirements and connection relationships between neuron cores. The synaptic connection matrix is ​​input into the weight configurator. The function of the weight configurator is to calculate the information transmission strength of each connection and calculate the synaptic weight distribution based on these strengths. Based on the event-driven pulse neural network model, these transmission strengths are converted into synaptic weights. Assuming that the transmission strength of each connection is , then the weight of the synapse Calculated according to the following formula: ; in, is a scaling factor, which represents the adjustment coefficient of the synaptic weight. Through this step, the synaptic weight distribution matrix is ​​obtained , which represents the connection strength between each neuron core. The synaptic weight distribution is normalized to eliminate the impact of differences in computing resources of different neuron cores, so that the synaptic weight can be adjusted within a reasonable range. The weights are scaled so that the sum of all weights is 1 or meets a specified range. For example, for the synaptic weight matrix , the normalized synaptic weight Calculated by the following formula: ; in, Indicates The sum of all synaptic weights of the neuron core. In this way, the standardized synaptic weight matrix is ​​obtained The computational task is encoded into neural pulses using the standardized synaptic weights. The neural pulses are encoded using the pulse frequency modulation method. Assume that the task The computational load is , the task load is encoded by the frequency of the pulse. The higher the pulse frequency, the heavier the computational load of the task. With task load The relationship is expressed by the following formula: ; in, is a constant that represents the mapping coefficient from load to pulse frequency. In this way, the computing task is encoded as a pulse signal sequence. The computing load of each task will be converted into pulses of the corresponding frequency, thereby generating a pulse code sequence : ; in, Indicates The pulse signal generated at each time point. Event-triggered mapping is performed on the pulse coding sequence. Event-triggered mapping adjusts the triggering timing and conditions of the pulse based on the discharge characteristics of the neuron. The discharge characteristics of each neuron are determined by its activation threshold and refractory period. Assume that the neuron The activation threshold is , the refractory period is , then in the neuron core When receiving a pulse from another core, it will only be activated when the strength of the pulse signal exceeds the activation threshold The neuron can only fire and discharge when . The triggering rule set R is represented as a set of conditions that describe under what circumstances the pulse signal will be triggered. For example, if the pulse signal of a task is at time point If the activation threshold of the neuron is exceeded, a spike signal is triggered, and the neuron will be in the refractory period. The trigger rule set is input into the asynchronous controller. The asynchronous controller coordinates the execution timing of multiple neuron cores according to the event-driven method. Through the event-driven method, the execution of neuron cores is performed asynchronously at different time points, thus achieving efficient parallel computing. The asynchronous controller generates an execution control sequence , which describes the execution timing and pulse triggering conditions of each neuron core at different time points. In the process of pulse signal transmission, the pulse signal in the execution control sequence is propagated and routed. The task of propagation routing is to Determine the transmission path and transmission strength of the pulse signal. For example, assuming the pulse signal From the neuron core Delivered to the neuron core , the transmission intensity is expressed as: ; in, is the normalized synaptic weight, From the core The strength of the pulse signal emitted. In this way, the transmission path and strength of the signal are determined according to the synaptic connection weight, and a signal transmission scheme is generated. According to the signal transmission scheme, data paths are established between neuron cores, and the transmission and calculation of pulse signals are completed through asynchronous parallel mechanism. The asynchronous parallel mechanism ensures that multiple neuron cores can perform computing tasks in parallel at different times, improving the overall computing efficiency. In the whole process, the processing results of the pulse signal sequence reflect the execution effect of the computing task and provide a basis for further optimization.

[0037] In a specific embodiment, the process of executing step S600 may specifically include the following steps: The processing results of the pulse signal sequence are statistically analyzed, and the execution efficiency is calculated based on the computing and communication performance of the 128 neuron cores in the neuromorphic computing chip to obtain a performance sampling matrix. The performance loss function is constructed by comparing the target task completion time with the actual execution time, and the loss is calculated on the performance sampling matrix to obtain the loss vector. The loss vector is then subjected to gradient analysis, and the gradient update direction is constructed based on the synaptic weight distribution and the neuron activation threshold to obtain the weight adjustment matrix. Update the state of the storage and computing units based on the weight adjustment matrix, build the optimization target by calculating the workload and resource occupancy rate of each unit, and obtain the state update vector; The state update vector is input into the Actor network, and the policy parameters of the action value function are iteratively optimized through the dynamic programming algorithm to obtain the optimized policy. The optimized policy is evaluated by the critic, and the value network is constructed by calculating the value evaluation scores of the state-action pairs to obtain the value function update amount. The updated value function is input into the parameter optimizer, and the weight parameters of the deep reinforcement learning network are updated by the stochastic gradient descent method to obtain the optimized parameter set. The parameters of the initial deep reinforcement learning network are updated according to the optimized parameter set, and the network structure is adjusted by the back propagation algorithm to obtain the target deep reinforcement learning network.

[0038] Specifically, the processing results of the pulse signal sequence are statistically analyzed, and the execution efficiency is calculated based on the computing and communication performance of the 128 neuron cores in the neuromorphic computing chip. Assume that the computing performance and communication performance of the neuron core are respectively expressed as and To indicate that Representative core computing power, and It represents the communication bandwidth of the core. By statistically analyzing the performance data of these 128 neuron cores, we can get the performance sampling matrix: , where each element Indicates the core and core The joint measurement of communication performance and computing performance between . The construction formula of this matrix is: ; in, is a fusion function that can calculate the joint performance between each neuron core based on their computing power and communication capabilities. In this way, a matrix that fully reflects the computing and communication performance is obtained. The performance loss function is constructed by comparing the difference between the target task completion time and the actual execution time. The target task completion time is usually the optimal time calculated in theory, while the actual execution time is the time obtained based on the current resource configuration and task execution status. Assume that the target task completion time is , while the actual execution time is , define a performance loss function To measure the difference between the two, the loss function is as follows: ; in, and Represent the theoretical completion time and actual execution time of the target task respectively. In order to evaluate the size of the loss, the performance sampling matrix Perform loss calculation to obtain a loss vector, where each element represents the loss size of each core in task execution. The calculation formula of the loss vector is: ; in, It is The actual execution time of each core. Through this step, the loss between each neuron core and the target task completion time is calculated, and the basis for gradient calculation is provided for the subsequent optimization process. Perform gradient analysis to determine how to update the synaptic connection weights and the state of the neuron core. Assume that the synaptic weight matrix is , the neuron activation threshold is , the gradient of the loss vector is calculated by the synaptic weight distribution and the activation threshold. Assume that the loss vector The relationship between the synaptic weight matrix and the activation threshold is expressed as: ; in, and Respectively represent the gradient of the loss function with respect to the synaptic weight and the neuron activation threshold. Through gradient analysis, the weight adjustment matrix is ​​obtained , used to guide subsequent optimization. Based on the weight adjustment matrix , update the status of the storage and computing unit. The status update of the storage and computing unit is usually completed by calculating the workload and resource utilization of each unit. Assume that the workload of each storage and computing unit is , the occupancy rate is , then the state update of the unit is calculated by the following formula: ; in, Indicates the status update of the storage and computing unit. It is obtained by weighted calculation of load and resource occupancy. In this way, the state of the storage and computing unit is dynamically adjusted according to the gradient in the loss vector to make it more in line with the target performance requirements. The updated state vector is input into the Actor network. The Actor network iteratively optimizes the policy parameters of the action value function through a dynamic programming algorithm. Assume that the current policy parameters are , the policy parameters are optimized through the dynamic programming algorithm, with the goal of maximizing the overall performance of the system. The dynamic programming algorithm obtains the optimal policy by gradually calculating the optimal action for each state. The optimized policy will give an updated action selection distribution. The Actor network will continuously adjust the policy during each optimization process to make resource scheduling and task allocation more efficient. During the policy update, the optimized policy is input into the Critic network for evaluation. The Critic network judges the pros and cons of the current policy by calculating the value evaluation score of each state-action pair. Assume that the current state-action pair is , and its value evaluation function is , the Critic network calculates the value of each state-action pair according to the value evaluation function: ; in, represents the immediate reward of the current state-action pair, is the discount factor, which represents the weight of future rewards. The Critic network further optimizes the strategy based on the calculated value evaluation score. The value function update is input into the parameter optimizer, and the weight parameters of the deep reinforcement learning network are updated by the stochastic gradient descent method. The goal of the stochastic gradient descent method is to minimize the loss function and optimize the strategy by continuously adjusting the parameters in the network. Assume that the current network weight is , the updated weight is calculated by the following formula: ; in, represents the learning rate, is the gradient of the loss function. Through the back-propagation algorithm, the optimizer updates the weight parameters according to the gradient to make the network's strategy closer to the optimal strategy. Through this step, the strategy is continuously adjusted and optimized in the deep reinforcement learning network, and finally the target deep reinforcement learning network is obtained.

[0039] See also Figure 2 , Figure 2 A schematic block diagram of the structure of a distributed processing device 200 of a neuromorphic computing chip provided in an embodiment of the present application, such as Figure 2 As shown, the distributed processing device 200 of the neuromorphic computing chip includes: A decomposition module 210 is used to perform feature decomposition on the computing task of the neuromorphic computing chip, establish a task topology graph, and perform message passing aggregation operation on the task topology graph to obtain a task encoding vector; The acquisition module 220 is used to collect the working status of the neuron core in the neuromorphic computing chip and obtain the core state matrix including the synaptic weight distribution, neuron activation threshold, and storage and computing unit occupancy rate; A construction module 230 is used to input the task encoding vector and the core state matrix into the initial deep reinforcement learning network, construct an action value function based on the Actor-Critic architecture, and generate a resource allocation strategy; The reconstruction module 240 is used to sequentially reconstruct the resource allocation strategy, calculate the temporal dependencies between tasks, and output a mapping scheme between neuron cores and computing tasks; An execution module 250 is used to configure synaptic connection weights according to the mapping scheme, convert the computing task into a pulse signal sequence, and transmit the execution between neuron cores through an asynchronous event triggering mechanism; The optimization module 260 is used to collect the processing results of the pulse signal sequence, calculate the synaptic weight update gradient, optimize the parameters of the action value function of the initial deep reinforcement learning network, and obtain the target deep reinforcement learning network.

[0040] Through the collaborative cooperation of the above components, the graph neural network is introduced to conduct in-depth analysis of task characteristics and dependencies, and the dynamic optimization allocation of computing resources is realized in combination with the deep reinforcement learning network. The asynchronous event trigger mechanism is used for parallel processing of tasks, and the data transmission overhead is reduced based on the storage and computing integrated architecture. At the same time, through the adaptive parameter optimization method, the online learning and optimization of the deep reinforcement learning network are realized, so that the system can dynamically adjust the processing strategy according to the real-time load conditions. This method significantly improves the resource utilization and processing efficiency of the neuromorphic computing chip, reduces energy consumption, enhances the system's adaptability in complex computing environments, and provides an efficient solution for large-scale neural network computing.

[0041] See also Figure 3 , Figure 3 The present invention is a block diagram showing a structure of a distributed processing device 300 of a neuromorphic computing chip provided in an embodiment of the present application. The distributed processing device 300 of the neuromorphic computing chip includes a processor 301 and a memory 302. The processor 301 and the memory 302 are connected via a device bus 303, wherein the memory 302 may include a non-volatile storage medium and an internal memory.

[0042] The non-volatile storage medium can store a computer program. The computer program includes program instructions, and when the program instructions are executed by the processor 301, the processor 301 can execute any of the above-mentioned distributed processing methods of the neuromorphic computing chip.

[0043] The processor 301 is used to provide computing and control capabilities to support the operation of the distributed processing device 300 of the entire neuromorphic computing chip.

[0044] The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium. When the computer program is executed by the processor 301, the processor 301 can execute any of the above-mentioned distributed processing methods of the neuromorphic computing chip.

[0045] Those skilled in the art will understand that Figure 3 The structure shown in the figure is only a block diagram of a partial structure related to the present application scheme, and does not constitute a limitation on the distributed processing device 300 of the neuromorphic computing chip involved in the present application scheme. The specific distributed processing device 300 of the neuromorphic computing chip may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0046] It should be understood that the processor 301 may be a central processing unit (CPU), and the processor 301 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0047] It should be noted that technical personnel in the relevant field can clearly understand that, for the convenience and conciseness of description, the specific working process of the distributed processing device 300 of the neuromorphic computing chip described above can refer to the corresponding process of the distributed processing method of the aforementioned neuromorphic computing chip, and will not be repeated here.

[0048] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by one or more processors, the one or more processors implement the distributed processing method of the neuromorphic computing chip provided in the embodiment of the present application.

[0049] The computer-readable storage medium may be an internal storage unit of the distributed processing device 300 of the neuromorphic computing chip of the aforementioned embodiment, such as a hard disk or memory of the distributed processing device 300 of the neuromorphic computing chip. The computer-readable storage medium may also be an external storage device of the distributed processing device 300 of the neuromorphic computing chip, such as a plug-in hard disk, a smart memory card (SmartMedia Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc., equipped with the distributed processing device 300 of the neuromorphic computing chip.

[0050] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0051] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0052] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A distributed processing method for a neuromorphic computing chip, characterized in that: include: Performing feature decomposition on the computing tasks of the neuromorphic computing chip, establishing a task topology graph, and performing message passing aggregation operation on the task topology graph to obtain a task encoding vector; Collect the working status of the neuron core in the neuromorphic computing chip and obtain the core state matrix including synaptic weight distribution, neuron activation threshold, and storage and computing unit occupancy rate; Input the task encoding vector and the core state matrix into an initial deep reinforcement learning network, construct an action value function based on an Actor-Critic architecture, and generate a resource allocation strategy; Reconstructing the resource allocation strategy in sequence, calculating the temporal dependencies between tasks, and outputting a mapping scheme between neuron cores and computing tasks; Configuring synaptic connection weights according to the mapping scheme, converting the computing task into a pulse signal sequence, and transmitting and executing between the neuron cores through an asynchronous event triggering mechanism; The processing results of the pulse signal sequence are collected, the synaptic weight update gradient is calculated, and the action value function of the initial deep reinforcement learning network is optimized to obtain the target deep reinforcement learning network.

2. The distributed processing method of the neuromorphic computing chip according to claim 1, characterized in that: The feature decomposition of the computing task of the neuromorphic computing chip is performed to establish a task topology map, and the message passing aggregation operation is performed on the task topology map to obtain a task encoding vector, including: Collecting timing features of computing tasks of the neuromorphic computing chip, extracting a task feature set including task arrival time, required number of neurons, number of synaptic connections, and data flow direction, performing data dependency analysis on the task feature set, and calculating task dependency relationships based on data transmission relationships between tasks; Constructing a directed graph structure based on the task dependency relationship, mapping the task feature set into graph node attributes, and mapping the dependency strength matrix into edge weights to obtain a task topology graph; Perform multi-head attention calculation on the nodes in the task topology graph to obtain node attention features, and input the node attention features into the graph convolution layer, perform weighted sum operation on the features of adjacent nodes through the message aggregation function to obtain the node hidden layer representation; According to the global features of the computation graph represented by the node hidden layer, the node features are pooled and dimensionally transformed to obtain a graph structure code, and the graph structure code is input into a fully connected neural network, and the features are mapped to a target dimensional space through a nonlinear transformation to obtain a compressed feature vector; The compressed feature vector and the node hidden layer representation are subjected to feature fusion, and a task encoding vector is obtained through residual connection.

3. The distributed processing method of the neuromorphic computing chip according to claim 2, characterized in that: The working state of the neuron core in the neuromorphic computing chip is collected to obtain a core state matrix including synaptic weight distribution, neuron activation threshold, and storage and computing unit occupancy rate, including: The synaptic connections of the neuron cores in the neuromorphic computing chip are scanned in parallel, and the synaptic weight, connection state and transmission bandwidth of each core are extracted to obtain the synaptic connection characteristics; Performing weight density calculation on the synaptic connection features to obtain a weight distribution map, and sampling the neuron state of each neuron core to obtain an activation threshold set; Based on the activation threshold set, state mapping is performed, the pulse triggering condition and discharge frequency of the neuron core are quantitatively calculated to obtain a threshold distribution sequence, and workload analysis is performed on the threshold distribution sequence and the storage and calculation unit to obtain a load state value; The load state value is input into an adaptive sampler, and the real-time occupancy of the storage and computing unit is captured by dynamically adjusting the sampling frequency to obtain an occupancy sequence, and the occupancy sequence and the weight distribution map are feature integrated to construct a state feature matrix through multi-dimensional matrix operations; Data fusion is performed based on the state feature matrix and the threshold distribution sequence, and multi-source state information is merged through tensor operations to obtain a core state matrix.

4. The distributed processing method of the neuromorphic computing chip according to claim 3, characterized in that: The step of inputting the task encoding vector and the core state matrix into an initial deep reinforcement learning network, constructing an action value function based on an Actor-Critic architecture, and generating a resource allocation strategy includes: Dimensionally aligning the task encoding vector and the core state matrix, constructing a 128-dimensional input feature space through feature recombination, and obtaining a state input vector; Input the state input vector into the Actor network, perform action space modeling based on the computing power of neurons and synapses, obtain an initial action distribution, perform feasibility constraints on the initial action distribution, perform resource allocation verification based on 16PB / s memory bandwidth and 3.5PB / s inter-core communication bandwidth, and obtain a valid action set; Input the state input vector and the valid action set into the Critic network, calculate the state value based on 380 trillion synaptic operations and 240 trillion neuron operations, and obtain a value evaluation function; Performing a temporal difference operation on the value evaluation function, constructing an instant reward by calculating the 192KB cache utilization of each neuron core, obtaining a TD error, and performing a gradient update on the policy distribution of the Actor network based on the TD error, optimizing the action selection probability in an asynchronous event-driven manner, and obtaining an updated policy; The update strategy is input into the resource scheduler, action mapping is performed based on the configuration space of 4096 neuron states to obtain a scheduling scheme set, and performance evaluation is performed on the scheduling scheme set. The schemes are sorted by calculating the storage and computing unit occupancy rate and the synaptic connection load to obtain the resource allocation strategy.

5. The distributed processing method of the neuromorphic computing chip according to claim 4, characterized in that: The method of sequentially reconstructing the resource allocation strategy, calculating the temporal dependencies between tasks, and outputting a mapping scheme between neuron cores and computing tasks includes: Sequentially encode the resource allocation strategy, and convert the scheduling requests of multiple concurrent tasks into an input sequence based on a Seq2Seq encoder to obtain a task timing vector; Inputting the task timing vector into the encoder of the recurrent neural network, constructing the data flow dependency relationship between the tasks through timing feature extraction, obtaining a timing feature matrix, performing hierarchical clustering on the timing feature matrix, dividing the task groups based on the data flow direction and transmission bandwidth requirements of adjacent tasks, and obtaining a hierarchical dependency tree; An attention weight matrix is ​​constructed based on the hierarchical dependency tree, and the task priority scores are calculated through the attention mechanism in the decoder of the recurrent neural network to obtain a scheduling priority sequence, and the scheduling priority sequence is allocated to neuron cores, and resource matching is performed based on the synaptic connection state and storage and computing unit occupancy rate of each core to obtain a core allocation plan; The core allocation scheme is input into the timing verification module, and the rationality of the task execution timing is verified by the decoder of the recurrent neural network to obtain an execution timing diagram, and conflict detection is performed on the execution timing diagram, and resource competition analysis is performed based on the neuron activation threshold and synaptic weight distribution to obtain a conflict elimination strategy; The core allocation scheme is adjusted based on the conflict elimination strategy, and a mapping scheme between neuron cores and computing tasks is generated through task rearrangement and resource reallocation.

6. The distributed processing method of the neuromorphic computing chip according to claim 5, characterized in that: The step of configuring synaptic connection weights according to the mapping scheme, converting the computing task into a pulse signal sequence, and transmitting and executing the sequence between the neuron cores through an asynchronous event triggering mechanism includes: Performing a connection relationship analysis on the mapping scheme, constructing a connection topology structure based on the data transmission requirements of each neuron core, obtaining a synaptic connection matrix, and inputting the synaptic connection matrix into a weight configurator, calculating the information transmission strength of each connection through an event-based spiking neural network, and obtaining a synaptic weight distribution; Performing normalization processing on the synaptic weight distribution, performing weight scaling based on the neuron activation threshold and the storage and computing unit occupancy rate to obtain a standardized weight, encoding the computing task into a neural pulse based on the standardized weight, converting the task load into a timing signal through pulse frequency modulation, and obtaining a pulse code sequence; Performing event-triggered mapping on the pulse coding sequence, setting a trigger threshold and a refractory period parameter based on the discharge characteristics of the neuron to obtain a trigger rule set, and inputting the trigger rule set into an asynchronous controller to coordinate the execution timing of multiple neuron cores in an event-driven manner to obtain an execution control sequence; The pulse signals in the execution control sequence are propagated and routed, the signal transmission path and strength are determined based on the synaptic connection weight, a signal transmission scheme is obtained, and a data path is established between neuron cores according to the signal transmission scheme. The transmission and calculation of the pulse signals are completed through an asynchronous parallel mechanism to obtain the processing result of the pulse signal sequence.

7. The distributed processing method of the neuromorphic computing chip according to claim 6, characterized in that: The processing result of collecting the pulse signal sequence, calculating the synaptic weight update gradient, and optimizing the parameters of the action value function of the initial deep reinforcement learning network to obtain the target deep reinforcement learning network include: Performing index statistics on the processing results of the pulse signal sequence, calculating the execution efficiency based on the computing and communication performance of 128 neuron cores in the neuromorphic computing chip, and obtaining a performance sampling matrix; A performance loss function is constructed by comparing the target task completion time with the actual execution time, a loss calculation is performed on the performance sampling matrix to obtain a loss vector, a gradient analysis is performed on the loss vector, a gradient update direction is constructed based on the synaptic weight distribution and the neuron activation threshold, and a weight adjustment matrix is ​​obtained; Based on the weight adjustment matrix, the state of the storage and computing unit is updated, and the optimization target is constructed by calculating the workload and resource occupancy rate of each unit to obtain a state update vector; The state update vector is input into the Actor network, the policy parameters of the action value function are iteratively optimized by a dynamic programming algorithm to obtain an optimized policy, and the optimized policy is evaluated by a critic, and a value network is constructed by calculating the value evaluation scores of the state-action pairs to obtain the value function update amount; The updated value function is input into the parameter optimizer, and the weight parameters of the deep reinforcement learning network are updated by the stochastic gradient descent method to obtain an optimized parameter set. The parameters of the initial deep reinforcement learning network are updated according to the optimized parameter set, and the network structure is adjusted by the back propagation algorithm to obtain the target deep reinforcement learning network.

8. A distributed processing device for a neuromorphic computing chip, characterized in that: A distributed processing method for executing a neuromorphic computing chip according to any one of claims 1 to 7, comprising: A decomposition module is used to perform feature decomposition on the computing tasks of the neuromorphic computing chip, establish a task topology graph, and perform message passing aggregation operation on the task topology graph to obtain a task encoding vector; The acquisition module is used to collect the working status of the neuron core in the neuromorphic computing chip and obtain the core state matrix including synaptic weight distribution, neuron activation threshold, and storage and computing unit occupancy rate; A construction module, used for inputting the task encoding vector and the core state matrix into an initial deep reinforcement learning network, constructing an action value function based on an Actor-Critic architecture, and generating a resource allocation strategy; A reconstruction module, used to sequentially reconstruct the resource allocation strategy, calculate the temporal dependencies between tasks, and output a mapping scheme between neuron cores and computing tasks; An execution module, configured to configure synaptic connection weights according to the mapping scheme, convert the computing task into a pulse signal sequence, and transmit and execute the sequence between the neuron cores through an asynchronous event triggering mechanism; The optimization module is used to collect the processing results of the pulse signal sequence, calculate the synaptic weight update gradient, and optimize the parameters of the action value function of the initial deep reinforcement learning network to obtain the target deep reinforcement learning network.

9. A distributed processing device for a neuromorphic computing chip, characterized in that: The distributed processing device of the neuromorphic computing chip includes: a memory and at least one processor, wherein instructions are stored in the memory; The at least one processor calls the instruction in the memory so that the distributed processing device of the neuromorphic computing chip executes the distributed processing method of the neuromorphic computing chip as described in any one of claims 1-7.

10. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instruction is executed by the processor, the distributed processing method of the neuromorphic computing chip as described in any one of claims 1-7 is implemented.

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