On-chip protection device, method and chip

Abstract

The present application provides an on-chip protection device, method and chip, the method is applied to the chip, and the device includes a state machine protection circuit and a key signal protection circuit; the state machine protection circuit is used to judge the protection effectiveness based on a target state protection configuration signal pre-configured for the target state before the state machine executes the target state based on the target trigger signal, and determine the judgment result of the protection effectiveness; if the judgment result of the protection effectiveness is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state; the key signal protection circuit is used to generate a protection signal, and when the protection signal is valid, controls the specified key signal related to the state machine to be valid; the specified key signal includes the output control signal of the state machine, which ensures the stability of the chip system when the state machine runs abnormally and solves the stability of the key control signal.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an on-chip protection device, method, and chip. Background Art

[0002] When an abnormality occurs in the system clock of an existing chip, such as abnormal jitter or glitches, a metastable state may occur due to the internal timing of the chip not being met, causing the chip state machine to run away. If a certain state is incorrectly entered, a corresponding erroneous control signal will be generated, causing the entire chip system to be abnormal or even damage the entire machine. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide an on-chip protection device, method and chip, which can solve the problem of chip system instability caused by abnormal clock or chip power-off, and solve the stability problem of key control signals, to ensure that the chip functions normally and reliably when the system is abnormal or interfered.

[0004] An on-chip protection device provided in an embodiment of the present application is applied to a chip, the device comprising a state machine protection circuit and a key signal protection circuit;

[0005] The state machine protection circuit is configured to, before the state machine executes the target state based on the target trigger signal, perform a protection validity judgment based on a target state protection configuration signal pre-configured for the target state, and determine a judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state;

[0006] The key signal protection circuit is used to generate a protection signal. When the protection signal is valid, the designated key signal related to the state machine is controlled to be valid; the designated key signal includes the output control signal of the state machine.

[0007] In some embodiments, in the on-chip protection device, the state machine protection circuit is pre-configured with a verification rule corresponding to a target state of the chip's state machine;

[0008] The state machine protection circuit is configured to perform protection validity judgment based on a target state protection configuration signal pre-configured for the target state before the state machine executes the target state based on the target trigger signal, and determine the judgment result of the protection validity, specifically for:

[0009] Before the state machine executes the target state based on the target trigger signal, the protection validity judgment circuit in the state machine protection circuit receives a target state protection configuration signal for the target state sent by the state machine;

[0010] The protection validity judgment circuit determines the judgment result of the protection validity by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state.

[0011] In some embodiments, in the on-chip protection device, determining the protection effectiveness judgment result by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state includes:

[0012] When the target state protection configuration signal is enabled and matches the verification rule corresponding to the target state, the protection validity judgment circuit generates a target state protection signal for the target state and determines that the protection validity judgment result is that the state protection is valid;

[0013] When the target state protection configuration signal is not enabled or does not match the verification rule corresponding to the target state, the protection validity judgment circuit does not generate a target state protection signal for the target state, and determines that the judgment result of the protection validity is that the state protection is invalid.

[0014] In some embodiments, in the on-chip protection device, after the state machine protection circuit determines the judgment result of protection effectiveness, if the judgment result of protection effectiveness is that the state protection is invalid, the state machine does not execute the target state and enters the idle state.

[0015] In some embodiments, in the on-chip protection device, the check rule is a check value, and the check value is a multi-bit sequence.

[0016] In some embodiments, in the on-chip protection device, the critical signal protection circuit receives a specified critical signal output by the state machine protection circuit; when the protection signal is valid, the specified critical signal generated by the state machine protection circuit and sent to the state machine is controlled to be valid.

[0017] In some embodiments, in the on-chip protection device, the critical signal protection circuit includes a protection register and a control register;

[0018] The protection register is used to generate a protection signal and send the protection signal to the control register;

[0019] The control register is used to receive a designated key signal related to the state machine, and when the protection signal is valid, control the designated key signal to be valid and output the valid designated key signal.

[0020] In some embodiments, in the on-chip protection device, the critical signal protection circuit further includes an enable register and clock gating of the enable register; the enable register is located at a level below the control register;

[0021] The clock gating of the enabling register receives the protection signal of the protection register as a gating signal to control whether the clock of the enabling register is turned on;

[0022] The enable register receives the valid designated key signal output by the control register, and determines whether to output the designated key signal based on whether the clock is turned on.

[0023] In some embodiments, an on-chip protection method is further provided. The method is applied to a chip, the chip including the on-chip protection device, the on-chip protection device including a state machine protection circuit and a key signal protection circuit; the protection method includes:

[0024] The state machine protection circuit performs a protection validity judgment based on a target state protection configuration signal pre-configured for the target state before the state machine executes the target state based on the target trigger signal, and determines a judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state;

[0025] The key signal protection circuit generates a protection signal. When the protection signal is valid, the designated key signal related to the state machine is controlled to be valid; the designated key signal includes the output control signal of the state machine.

[0026] In some embodiments, a chip is further provided, the chip including the on-chip protection device, the on-chip protection device including a state machine protection circuit and a key signal protection circuit;

[0027] The state machine protection circuit is configured to, before the state machine executes the target state based on the target trigger signal, perform a protection validity judgment based on a target state protection configuration signal pre-configured for the target state, and determine a judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state;

[0028] The key signal protection circuit is used to generate a protection signal. When the protection signal is valid, the designated key signal related to the state machine is controlled to be valid; the designated key signal includes the output control signal of the state machine.

[0029] The embodiment of the present application provides an on-chip protection device, method and chip, the on-chip protection device is applied to the chip, the device includes a state machine protection circuit and a key signal protection circuit; before the state machine executes the target state based on the target trigger signal, the state machine protection circuit judges the protection validity based on the target state protection configuration signal pre-configured for the target state, and determines the judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state; the key signal protection circuit is used to generate a protection signal, and when the protection signal is valid, controls the state machine related indicators. The designated key signal is valid; the designated key signal includes the output control signal of the state machine; the state machine protection circuit switches the uncontrollable state to the IDLE idle state when the state machine runs away, ensuring that the logic inside the chip does not generate an internal control signal, thereby solving the problem that the system may be unstable due to clock abnormality or the state machine may run away abnormally during chip power-off; the key signal protection circuit can ensure that the key control signal is locked when the chip runs away due to system abnormality, and no unnecessary control signal will be generated due to system abnormality, thereby solving the stability of the key control signal and ensuring that the chip functions normally and reliably when the system is abnormal or interfered with. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 A schematic structural diagram of an on-chip protection device according to an embodiment of the present application is shown;

[0032] Figure 2 shows a block diagram illustrating a state machine protection mechanism;

[0033] Figure 3 A schematic diagram showing the principle of the protection effectiveness judgment circuit described in an embodiment of the present application is shown;

[0034] Figure 4 A schematic structural diagram of the on-chip protection device described in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0036] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0037] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0038] When an abnormality occurs in the system clock of an existing chip, such as abnormal jitter or glitches, a metastable state may occur due to the internal timing of the chip not being met, causing the chip state machine to run away. If a certain state is incorrectly entered, a corresponding erroneous control signal will be generated, causing the entire chip system to be abnormal or even damage the entire machine.

[0039] Based on this, an embodiment of the present application provides an on-chip protection device, method and chip, wherein the on-chip protection device is applied to a chip, and the device includes a state machine protection circuit and a key signal protection circuit; before the state machine executes the target state based on the target trigger signal, the state machine protection circuit judges the protection validity based on the target state protection configuration signal pre-configured for the target state, and determines the judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state; the key signal protection circuit is used to generate a protection signal, and when the protection signal is valid, controls the state machine related The designated key signal is valid; the designated key signal includes the output control signal of the state machine; the state machine protection circuit switches the uncontrollable state to the IDLE idle state when the state machine runs away, ensuring that the logic inside the chip does not generate internal control signals, thereby solving the problem that the system may be unstable due to clock abnormality or the state machine may run away abnormally during chip power-off; the key signal protection circuit can ensure that the key control signal is locked when the chip runs away due to system abnormality, and no unnecessary control signal will be generated due to system abnormality, thereby solving the stability of the key control signal and ensuring that the chip functions normally and reliably when the system is abnormal or interfered with.

[0040] Please refer to Figure 1 , Figure 1 The schematic diagram of the structure of the on-chip protection device according to the embodiment of the present application is shown; the on-chip protection device 100 is applied to a chip, such as Figure 1 As shown, the device includes a state machine protection circuit 101 and a key signal protection circuit 102;

[0041] The state machine protection circuit 100 is configured to, before the state machine executes a target state based on a target trigger signal, perform a protection validity judgment based on a target state protection configuration signal pre-configured for the target state, and determine a judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state;

[0042] The key signal protection circuit 102 is used to generate a protection signal. When the protection signal is valid, the designated key signal related to the state machine is controlled to be valid; the designated key signal includes the output control signal of the state machine.

[0043] Please refer to Figure 2 , Figure 2 The principle block diagram of the state machine protection mechanism is shown; Figure 2As shown, the normal state of the state machine mainly includes the state jump of IDLE->State 1->State 2...->State n–>IDLE. The corresponding control signal required by each state is generated in each state. For example, after executing state 1, control signal 1 is output, after executing state 2, control signal 2 is output, and after executing state n, control signal n is output.

[0044] A protection validity judgment is performed based on a target state protection configuration signal pre-configured for the target state, and a judgment result of the protection validity is determined. The judgment result of the protection validity includes state protection valid and state protection invalid.

[0045] That is to say, in the embodiment of the present application, a state machine protection circuit is added, that is, the protection of state n (n=1, 2, 3...). Only when this function is turned on normally can the state machine be guaranteed to execute normally. Otherwise, it will enter the IDLE idle state and will not execute the corresponding function, thereby solving the problem that the state machine may run away abnormally due to clock abnormality or chip power-off, resulting in chip system instability.

[0046] The state machine protection circuit described in the embodiment of the present application is pre-configured with verification rules corresponding to the target state of the chip's state machine.

[0047] The verification rule is used to verify that the target state protection configuration signal configured for the target state is valid.

[0048] In some optional embodiments, the state machine protection circuit includes a protection validity judgment circuit, please refer to Figure 3 , Figure 3 A schematic diagram showing the principle of the protection effectiveness judgment circuit described in an embodiment of the present application is shown.

[0049] The state machine protection circuit is configured to perform protection validity judgment based on a target state protection configuration signal pre-configured for the target state before the state machine executes the target state based on the target trigger signal, and determine the judgment result of the protection validity, specifically for:

[0050] Before the state machine executes the target state based on the target trigger signal, the protection validity judgment circuit in the state machine protection circuit receives a target state protection configuration signal for the target state sent by the state machine;

[0051] The protection validity judgment circuit determines the judgment result of the protection validity by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state.

[0052] Specifically, determining the protection validity judgment result by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state includes:

[0053] When the target state protection configuration signal is enabled and matches the verification rule corresponding to the target state, the protection validity judgment circuit generates a target state protection signal for the target state and determines that the protection validity judgment result is that the state protection is valid;

[0054] When the target state protection configuration signal is not enabled or does not match the verification rule corresponding to the target state, the protection validity judgment circuit does not generate a target state protection signal for the target state, and determines that the judgment result of the protection validity is that the state protection is invalid.

[0055] If the result of the protection validity judgment is that the state protection is valid, the state machine normally executes the target state and generates an output control signal corresponding to the target state;

[0056] After the state machine protection circuit determines the judgment result of protection effectiveness, if the judgment result of protection effectiveness is that the state protection is invalid, the state machine does not execute the target state and enters the idle state.

[0057] In some embodiments, the verification rule is a verification value, and the verification value is a multi-bit sequence. The multi-bit sequence can improve the accuracy of validity judgment.

[0058] Assuming the check value is 1 bit, there may be a situation where the check fails incorrectly, but a multi-bit sequence can avoid this situation.

[0059] Please refer to Figure 3 The target state protection configuration signal includes a state 1 protection configuration signal, a state 2 protection configuration signal...a state n protection configuration signal. The protection validity circuit can determine whether a corresponding state protection signal, such as a state 1 protection signal and a state n protection signal, is generated based on whether the corresponding configuration signal is enabled and whether the corresponding key (that is, the check value) is matched; if the corresponding configuration is performed and the key is matched, the corresponding target state protection signal is generated.

[0060] For example, when the state 1 protection configuration signal stat1_cfg == stat1_key1, the state 1 protection signal stat1_prot is generated. Other state protection signals are similar.

[0061] The target state protection configuration signal may be generated through register configuration or generated by an internal circuit.

[0062] The check value for the target state in the check rule, such as stat1_key, is a special sequence, such as 0x5a5a5a5a.

[0063] Different states in the state machine correspond to different check values.

[0064] In some embodiments, please refer to Figure 4 , Figure 4 4 shows a schematic structural diagram of an on-chip protection device according to an embodiment of the present application; in the on-chip protection device, the key signal protection circuit includes a protection register 401 and a control register 402;

[0065] The protection register 401 is used to generate a protection signal and send the protection signal to the clock gating of the control register and the enable register;

[0066] The control register 402 is used to receive a designated key signal related to the state machine, and when the protection signal is valid, control the designated key signal to be valid and output the valid designated key signal.

[0067] The critical signal protection circuit further includes an enable register 403 and a clock gating 404 of the enable register 403; the enable register 403 is located at the next level of the control register 402;

[0068] The clock gating 404 of the enable register 403 receives the protection signal of the protection register 401 as a gating signal to control whether the clock of the enable register 403 is turned on;

[0069] The enable register 403 receives the valid designated key signal output by the control register 402 and determines whether to output the designated key signal based on whether the clock is turned on.

[0070] The key signal protection circuit is used to generate a protection signal. When the protection signal is valid, the designated key signal related to the state machine is controlled to be valid; the designated key signal includes the output control signal of the state machine; please refer to Figure 1 , the key signal protection circuit receives the specified key signal output by the state machine protection circuit; when the protection signal is valid, the specified key signal generated by the state machine protection circuit and sent to the state machine is controlled to be valid.

[0071] The designated key signal is a signal related to the state machine, specifically, including the output control signal of the state machine, the control signal input to the state machine, and the control signal input to the state machine, such as the control signal input to the state machine by the state machine protection circuit, such as a write signal, a clear signal, etc.

[0072] The designated key signal is a control signal determined according to the business, for example, at least part of the output control signal determined from output control signal 1, output control signal 2, ... output control signal n corresponding to state 1, state 2, ... state n of the state machine.

[0073] Specifically, a protection signal is generated through a register or an internal circuit, so that the Q end of the protect reg generates an r_prot signal; when the value of the protection signal is valid (i.e., r_prot=1), the control signal ctrl can generate a ctrl=1 signal in the corresponding state, that is, the control signal ctrl is valid; otherwise, the ctrl=1 signal cannot be generated, that is, the control signal ctrl is invalid.

[0074] Furthermore, the generated protection signal r_prot signal will also serve as the gating signal for the clock of the next-level enable register ctrlenable reg, controlling whether the clock of the lower-level register is turned on; that is, if the protection is not turned on, when the control signal ctrl becomes valid due to a system abnormality, the next-level enable register ctrl enable reg can be protected from being affected by controlling the clock gating, thereby ensuring the stability of the chip.

[0075] The control signal ctrl generated in the state machine is transmitted to the D terminal of the final enable register (ctrl enable reg), which is equivalent to using two-level registers for simple synchronous filtering. This method can solve the metastable problem caused by clock glitches in the system and avoid the erroneous generation of the ctrl_en signal due to system clock anomalies.

[0076] It should be noted that, to protect the target critical signals, more levels of protection may be added, or more levels of registers may be added.

[0077] For the state machine, the output control signal corresponding to the target state will be generated only when the target state of the state machine is judged by the protection validity; based on the protection signal of the protection register in the key signal protection circuit, the control signal generated by the state machine is filtered once, and the pulse control signal (such as glitch) generated by error when the state machine runs away will be locked, and no unnecessary control signal will be generated due to system abnormality; further, the protection signal will also serve as the gating signal of the enable register clock of the next level. When the output control signal becomes valid due to system abnormality, it can also protect the enable register of the next level from being affected by controlling the clock gating, thereby ensuring the stability inside the chip, thereby fully ensuring the stable operation of the state machine.

[0078] Based on the same inventive concept, an on-chip protection method corresponding to the on-chip protection device is also provided in the embodiment of the present application. Since the principle of solving the problem by the on-chip protection method in the embodiment of the present application is similar to that of the above-mentioned on-chip protection device in the embodiment of the present application, the implementation of the on-chip protection method can refer to the implementation of the on-chip protection device, and the repeated parts will not be repeated.

[0079] In some embodiments, an on-chip protection method is further provided. The method is applied to a chip, the chip including the on-chip protection device, the on-chip protection device including a state machine protection circuit and a key signal protection circuit; the protection method includes:

[0080] The state machine protection circuit performs a protection validity judgment based on a target state protection configuration signal pre-configured for the target state before the state machine executes the target state based on the target trigger signal, and determines a judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state;

[0081] The key signal protection circuit generates a protection signal. When the protection signal is valid, the designated key signal related to the state machine is controlled to be valid; the designated key signal includes the output control signal of the state machine.

[0082] In some embodiments, in the on-chip protection method, the state machine protection circuit is pre-configured with a verification rule corresponding to a target state of the chip's state machine;

[0083] The state machine protection circuit is configured to perform protection validity judgment based on a target state protection configuration signal pre-configured for the target state before the state machine executes the target state based on the target trigger signal, and determine the judgment result of the protection validity, specifically for:

[0084] Before the state machine executes the target state based on the target trigger signal, the protection validity judgment circuit in the state machine protection circuit receives a target state protection configuration signal for the target state sent by the state machine;

[0085] The protection validity judgment circuit determines the judgment result of the protection validity by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state.

[0086] In some embodiments, in the on-chip protection method, determining the protection effectiveness judgment result by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state includes:

[0087] When the target state protection configuration signal is enabled and matches the verification rule corresponding to the target state, the protection validity judgment circuit generates a target state protection signal for the target state and determines that the protection validity judgment result is that the state protection is valid;

[0088] When the target state protection configuration signal is not enabled or does not match the verification rule corresponding to the target state, the protection validity judgment circuit does not generate a target state protection signal for the target state, and determines that the judgment result of the protection validity is that the state protection is invalid.

[0089] In some embodiments, in the on-chip protection method, after the state machine protection circuit determines the judgment result of protection effectiveness, if the judgment result of protection effectiveness is that the state protection is invalid, the state machine does not execute the target state and enters the idle state.

[0090] In some embodiments, in the on-chip protection method, the check rule is a check value, and the check value is a multi-bit sequence.

[0091] In some embodiments, in the on-chip protection method, the critical signal protection circuit receives a specified critical signal output by the state machine protection circuit; when the protection signal is valid, the specified critical signal generated by the state machine protection circuit and sent to the state machine is controlled to be valid.

[0092] In some embodiments, in the on-chip protection method, the critical signal protection circuit includes a protection register and a control register;

[0093] The protection register is used to generate a protection signal and send the protection signal to the control register;

[0094] The control register is used to receive a designated key signal related to the state machine, and when the protection signal is valid, control the designated key signal to be valid and output the valid designated key signal.

[0095] In some embodiments, in the on-chip protection method, the critical signal protection circuit further includes an enable register and clock gating of the enable register; the enable register is located at a level below the control register;

[0096] The clock gating of the enabling register receives the protection signal of the protection register as a gating signal to control whether the clock of the enabling register is turned on;

[0097] The enable register receives the valid designated key signal output by the control register, and determines whether to output the designated key signal based on whether the clock is turned on.

[0098] Based on the same inventive concept, a chip corresponding to the on-chip protection device is also provided in the embodiment of the present application. Since the principle of solving the problem by the chip in the embodiment of the present application is similar to that of the above-mentioned on-chip protection device in the embodiment of the present application, the implementation of the chip can refer to the implementation of the on-chip protection device, and the repeated parts will not be repeated.

[0099] In some embodiments, a chip is further provided, the chip including the on-chip protection device, the on-chip protection device including a state machine protection circuit and a key signal protection circuit;

[0100] The state machine protection circuit is configured to, before the state machine executes the target state based on the target trigger signal, perform a protection validity judgment based on a target state protection configuration signal pre-configured for the target state, and determine a judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state;

[0101] The key signal protection circuit is used to generate a protection signal. When the protection signal is valid, the designated key signal related to the state machine is controlled to be valid; the designated key signal includes the output control signal of the state machine.

[0102] In some embodiments, in the chip, the state machine protection circuit is pre-configured with a verification rule corresponding to a target state of the chip's state machine;

[0103] The state machine protection circuit is configured to perform protection validity judgment based on a target state protection configuration signal pre-configured for the target state before the state machine executes the target state based on the target trigger signal, and determine the judgment result of the protection validity, specifically for:

[0104] Before the state machine executes the target state based on the target trigger signal, the protection validity judgment circuit in the state machine protection circuit receives a target state protection configuration signal for the target state sent by the state machine;

[0105] The protection validity judgment circuit determines the judgment result of the protection validity by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state.

[0106] In some embodiments, in the chip, determining the protection validity judgment result by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state includes:

[0107] When the target state protection configuration signal is enabled and matches the verification rule corresponding to the target state, the protection validity judgment circuit generates a target state protection signal for the target state and determines that the protection validity judgment result is that the state protection is valid;

[0108] When the target state protection configuration signal is not enabled or does not match the verification rule corresponding to the target state, the protection validity judgment circuit does not generate a target state protection signal for the target state, and determines that the judgment result of the protection validity is that the state protection is invalid.

[0109] In some embodiments, in the chip, after the state machine protection circuit determines the judgment result of protection effectiveness, if the judgment result of protection effectiveness is that state protection is invalid, the state machine does not execute the target state and enters an idle state.

[0110] In some embodiments, in the chip, the verification rule is a verification value, and the verification value is a multi-bit sequence.

[0111] In some embodiments, in the chip, the critical signal protection circuit receives a specified critical signal output by the state machine protection circuit; when the protection signal is valid, the specified critical signal generated by the state machine protection circuit and sent to the state machine is controlled to be valid.

[0112] In some embodiments, in the chip, the critical signal protection circuit includes a protection register and a control register;

[0113] The protection register is used to generate a protection signal and send the protection signal to the control register;

[0114] The control register is used to receive a designated key signal related to the state machine, and when the protection signal is valid, control the designated key signal to be valid and output the valid designated key signal.

[0115] In some embodiments, in the chip, the critical signal protection circuit further includes an enable register and clock gating of the enable register; the enable register is located at a level below the control register;

[0116] The clock gating of the enabling register receives the protection signal of the protection register as a gating signal to control whether the clock of the enabling register is turned on;

[0117] The enable register receives the valid designated key signal output by the control register, and determines whether to output the designated key signal based on whether the clock is turned on.

[0118] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0119] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network elements. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0120] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0121] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, platform server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0122] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An on-chip protection device, characterized in that: Applied to a chip, the device includes a state machine protection circuit and a key signal protection circuit; the state machine protection circuit is pre-configured with a verification rule corresponding to the target state of the chip's state machine; The state machine protection circuit is configured to, before the state machine executes the target state based on the target trigger signal, perform a protection validity judgment based on a target state protection configuration signal pre-configured for the target state, and determine a judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state; The key signal protection circuit is used to generate a protection signal, and when the protection signal is valid, controls the designated key signal related to the state machine to be valid; the designated key signal includes the output control signal of the state machine; The state machine protection circuit is configured to perform protection validity judgment based on a target state protection configuration signal pre-configured for the target state before the state machine executes the target state based on the target trigger signal, and determine the judgment result of the protection validity, specifically for: Before the state machine executes the target state based on the target trigger signal, the protection validity judgment circuit in the state machine protection circuit receives a target state protection configuration signal for the target state sent by the state machine; The protection validity judgment circuit determines the judgment result of the protection validity by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state.

2. The on-chip protection device according to claim 1, wherein: The determining of the protection validity by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state includes: When the target state protection configuration signal is enabled and matches the verification rule corresponding to the target state, the protection validity judgment circuit generates a target state protection signal for the target state and determines that the protection validity judgment result is that the state protection is valid; When the target state protection configuration signal is not enabled or does not match the verification rule corresponding to the target state, the protection validity judgment circuit does not generate a target state protection signal for the target state, and determines that the judgment result of the protection validity is that the state protection is invalid.

3. The on-chip protection device according to claim 1 or 2, characterized in that: After the state machine protection circuit determines the judgment result of protection effectiveness, if the judgment result of protection effectiveness is that the state protection is invalid, the state machine does not execute the target state and enters the idle state.

4. The on-chip protection device according to claim 1, wherein: The verification rule is a verification value, and the verification value is a multi-bit sequence.

5. The on-chip protection device according to claim 1, wherein: The key signal protection circuit receives a designated key signal output by the state machine protection circuit; when the protection signal is valid, the designated key signal generated by the state machine protection circuit and sent to the state machine is controlled to be valid.

6. The on-chip protection device according to claim 1 or 5, characterized in that: The key signal protection circuit includes a protection register and a control register; The protection register is used to generate a protection signal and send the protection signal to the control register; The control register is used to receive a designated key signal related to the state machine, and when the protection signal is valid, control the designated key signal to be valid and output the valid designated key signal.

7. The on-chip protection device according to claim 6, wherein: The critical signal protection circuit further includes an enable register and a clock gating control of the enable register; the enable register is located at a level below the control register; The clock gating of the enabling register receives the protection signal of the protection register as a gating signal to control whether the clock of the enabling register is turned on; The enable register receives the valid designated key signal output by the control register, and determines whether to output the designated key signal based on whether the clock is turned on.

8. An on-chip protection method, characterized in that: The method is applied to a chip, wherein the chip includes an on-chip protection device, and the on-chip protection device includes a state machine protection circuit and a key signal protection circuit; The state machine protection circuit is pre-configured with a verification rule corresponding to the target state of the chip's state machine; The protection method includes: The state machine protection circuit performs a protection validity judgment based on a target state protection configuration signal pre-configured for the target state before the state machine executes the target state based on the target trigger signal, and determines a judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state; The key signal protection circuit generates a protection signal, and when the protection signal is valid, controls the designated key signal related to the state machine to be valid; the designated key signal includes the output control signal of the state machine; The state machine protection circuit is configured to perform protection validity judgment based on a target state protection configuration signal pre-configured for the target state before the state machine executes the target state based on the target trigger signal, and determine the judgment result of the protection validity, specifically for: Before the state machine executes the target state based on the target trigger signal, the protection validity judgment circuit in the state machine protection circuit receives a target state protection configuration signal for the target state sent by the state machine; The protection validity judgment circuit determines the judgment result of the protection validity by judging whether the target state protection configuration signal is enabled and whether it matches the verification rule corresponding to the target state.

9. A chip, characterized in that: The chip includes the on-chip protection device according to any one of claims 1 to 7, wherein the on-chip protection device includes a state machine protection circuit and a key signal protection circuit; The state machine protection circuit is configured to, before the state machine executes the target state based on the target trigger signal, perform a protection validity judgment based on a target state protection configuration signal pre-configured for the target state, and determine a judgment result of the protection validity; if the judgment result of the protection validity is that the state protection is valid, the state machine executes the target state normally and generates an output control signal corresponding to the target state; The key signal protection circuit is used to generate a protection signal. When the protection signal is valid, the designated key signal related to the state machine is controlled to be valid; the designated key signal includes the output control signal of the state machine.

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