Data burning and self-checking method and device of display panel and Flash IC (integrated circuit) flash memory chip

Abstract

The invention relates to the technical field of display screens, in particular to a data burning and self-checking method and device of a display panel, a Flash IC flash memory chip, a computer readable storage medium and a computer program product. The method comprises the following steps: outputting an output voltage with at least one voltage state under the condition of detecting that the Flash IC flash memory chip receives a burning driving signal; according to the voltage state and an addressing area mapping table, a to-be-burnt addressing area, corresponding to the output voltage of the sequential control module, in the Flash IC flash memory chip is determined, and other areas are controlled to be in a latch state; after data burning is finished, current cyclic redundancy check values of all areas in the Flash IC flash memory chip are obtained; and performing comparison verification on the current cyclic redundancy check value and a preset cyclic redundancy check value to obtain a data burning self-checking result. By adopting the method, the influence on the data of other address areas in the Flash IC can be reduced in the process of carrying out the burning operation twice in sequence and under the condition that interference signals exist outside.

Description

Technical Field

[0001] The present application relates to the technical field of display screens, and in particular to a method and device for data burning and self-testing of a display panel, a Flash IC flash memory chip, a computer-readable storage medium, and a computer program product. Background Art

[0002] With the rapid development of mobile devices and smart terminals, applying TDDI (touch and display driver integration) technology to OLED (organic light-emitting diode) display devices can improve the reliability of display devices.

[0003] In the design of general OLED display devices, the TP (touch panel) firmware data is burned into the TP IC (touch panel integrated circuit), and the Demura (color correction) compensation data is burned into the Flash IC (flash memory chip). In the application of TDDI technology, the two types of data will be burned in the same area. If there are interference signals in the external environment, the data is easily erased or rewritten by mistake, thus affecting the reliability of the display device.

[0004] Therefore, there is an urgent need for a data burning and self-test method, device, Flash IC flash memory chip, computer-readable storage medium and computer program product for a display panel, which can reduce the impact on data in other address areas in the Flash IC during two consecutive burning operations and when there are external interference signals. Summary of the invention

[0005] Based on this, it is necessary to provide a data burning and self-test method, device, Flash IC flash memory chip, computer-readable storage medium and computer program product for a display panel to address the above technical problems. In the process of performing two burning operations successively and in the presence of external interference signals, the impact on the data in other address areas in the Flash IC can be reduced.

[0006] In a first aspect, the present application provides a data burning and self-testing method for a display panel, comprising:

[0007] When it is detected that the Flash IC flash memory chip receives a programming drive signal, the timing control module outputs an output voltage having at least one voltage state;

[0008] According to the voltage state and addressing area mapping table, determine the addressing area to be burned in the Flash IC flash memory chip corresponding to the output voltage of the timing control module, and control other areas except the addressing area to be burned to be in a latched state;

[0009] Burning corresponding data to be burned in the addressing area to be burned, wherein the data to be burned includes first data and second data;

[0010] After the data burning is completed, the current cyclic redundancy check values ​​of all areas in the Flash IC flash memory chip are obtained;

[0011] The current cyclic redundancy check value is compared and verified with the preset cyclic redundancy check value to obtain the data burning self-test result.

[0012] In a second aspect, the present application also provides a data burning and self-testing device for a display panel, comprising:

[0013] A timing control module, configured to output an output voltage having at least one voltage state when detecting that the Flash IC flash memory chip receives a programming drive signal;

[0014] A processing module, used for determining the addressing area to be burned in the Flash IC flash memory chip corresponding to the output voltage of the timing control module according to the voltage state and the addressing area mapping table, and controlling other areas except the addressing area to be burned to be in a latched state;

[0015] A burning module, used for burning corresponding data to be burned in the addressing area to be burned, wherein the data to be burned includes first data and second data;

[0016] An acquisition module, used for acquiring the current cyclic redundancy check values ​​of all areas in the Flash IC flash memory chip after the data burning is completed;

[0017] The self-check module is used to compare and verify the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-check result.

[0018] In a third aspect, the present application further provides a Flash IC flash memory chip, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0019] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0020] In a fifth aspect, the present application also provides a computer program product, including a computer program, which implements the steps of the above method when executed by a processor.

[0021] The above-mentioned display panel data burning and self-checking method, device, Flash IC flash memory chip, computer-readable storage medium and computer program product can effectively prevent the influence of external interference signals on the data in the non-burning area by accurately controlling the addressing area to be burned in the Flash IC during the burning process and placing other areas in a latched state, thereby improving the reliability of data burning. Since the risk of accidentally erasing or rewriting the data in the non-burning area is reduced, the adoption of this scheme can enhance the stability of the OLED display device and reduce the equipment failure rate caused by data damage. Through the timing control module and the addressing area mapping table, the burning process is accurately controlled, making the burning operation more efficient and simplifying the burning process. After the data burning is completed, by obtaining the cyclic redundancy check value (CRC) of all areas in the Flash IC and comparing and verifying with the preset value, the self-check of the burned data is realized, ensuring the integrity and correctness of the data. Due to the optimization of the burning process and the realization of the self-checking function, the number of repeated burning times required due to data errors can be reduced, thereby saving time and cost and improving production efficiency. The realization of the self-check function allows rapid discovery and correction of programming errors during the production process, simplifies the fault diagnosis and testing process, and reduces the workload of subsequent maintenance and testing. It can maintain the accuracy of data programming in the presence of external interference signals, allowing the display device to maintain stable performance under various environmental conditions.

[0022] In summary, the present application improves the reliability and accuracy of display panel data burning and enhances the stability and production efficiency of OLED display devices by precisely controlling the burning process and realizing the self-checking function. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 This is a schematic diagram of the data burning structure of the display panel in the traditional Normal solution;

[0025] Figure 2 A schematic diagram of a flow chart of a data burning and self-checking method for a display panel in one embodiment;

[0026] Figure 3 A schematic diagram of a flow chart of a data burning and self-testing method for a display panel in another embodiment;

[0027] Figure 4A schematic diagram of the main data partitions of a TDDI project flash memory chip in one embodiment;

[0028] Figure 5 A schematic diagram of a flow chart of a data burning and self-testing method for a display panel in another embodiment;

[0029] Figure 6 is an expanded structural block diagram of a timing control module in one embodiment;

[0030] Figure 7 is a schematic diagram of the circuit structure of a gating circuit in another embodiment;

[0031] Figure 8 It is a signal timing diagram of TP firmware data and Demura compensation data in another embodiment;

[0032] Fig. 9 A schematic diagram of a flow chart of a data burning and self-testing method for a display panel in another embodiment;

[0033] Fig.10 is a schematic diagram of a display device in one embodiment;

[0034] Fig.11 A structural block diagram of a data burning and self-testing device for a display panel in one embodiment;

[0035] Fig.12 FIG. 4 is a diagram showing the internal structure of a Flash IC flash memory chip in one embodiment. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] like Figure 1As shown, in the traditional general solution, the firmware data of the touch panel (TP) is burned into the touch panel integrated circuit (TP IC). At the same time, the Demura (color correction) compensation data is burned into the flash chip (Flash IC). In this solution, the TP firmware data and the Demura compensation data are stored separately, burned independently, and do not affect each other. In order to further reduce the cost of the display panel and improve the integration of the touch display device, TDDI (Touch and Display Driver Integration) technology is adopted. TDDI (Touch and Display Driver Integration) technology is a technology that integrates touch function and display driver function on one chip. In the TDDI solution, due to the lack of an independent TP IC, both the TP firmware data and the Demura compensation data need to be burned into the same Flash IC. This means that the Flash IC needs to be burned twice: the first time to burn the TP firmware data, and the second time to burn the Demura compensation data.

[0038] In the TDDI solution, since the Flash IC needs to be burned twice, if there are interference signals in the external environment between the first and second burning, these interference signals may affect the storage state of the Flash IC. If the interference signal causes the control logic of the Flash IC to be abnormal, it may mistakenly erase or mistakenly write to the area in the Flash IC that should not be modified. This may cause the data burned for the first time (TP firmware data) to be rewritten or lost, or the data burned for the second time (demura compensation data) to have problems. If the data in the Flash IC is mistakenly erased or rewritten, it may cause the display device to not work properly, because the TP firmware data or demura compensation data is necessary for the operation of the device. This data loss or rewriting will reduce the reliability of the display device, increase maintenance costs, and affect the user experience.

[0039] Based on the problems existing in the above traditional technologies, such as Figure 2 As shown, a data burning and self-testing method for a display panel is provided, comprising the following steps S202 to S210. Among them:

[0040] Step S202: When it is detected that the Flash IC flash memory chip receives a programming driving signal, the timing control module outputs an output voltage having at least one voltage state.

[0041] Specifically, at the beginning of the programming process, it is first necessary to detect whether the Flash IC has received the programming drive signal. This signal is the instruction to start the programming operation, indicating that the programming operation is about to begin. The timing control module is a key component in the programming system. Its main function is to control the timing during the programming process and ensure that the data is written to the Flash IC at the right time and in the right order.

[0042] The timing control module will output an output voltage with at least one voltage state according to the detected burning drive signal. This output voltage is a power signal used to control the internal operation of the Flash IC, which determines the working state of the Flash IC. Different voltage states of the output voltage usually correspond to different operating modes inside the Flash IC, such as erasing, programming (writing) or reading. By controlling the output voltage, the timing control module can accurately control the Flash IC to enter a specific operating mode.

[0043] Step S204, according to the voltage state and addressing area mapping table, determining the addressing area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module, and controlling other areas except the addressing area to be programmed to be in a latched state.

[0044] Specifically, the addressing area mapping table is a data structure that defines the correspondence between different voltage states and different storage areas inside the Flash IC. Through the addressing area mapping table, the timing control module can determine the addressing area to be burned in the Flash IC corresponding to the output voltage; the addressing area to be burned is a predetermined storage area in the Flash IC that has been set to be ready to receive new data. After determining the addressing area to be burned, the timing control module will control the other areas in the Flash IC except the addressing area to be burned to be in a latched state. The latched state is a protection state that can prevent these areas from being affected by accidental erase or write operations.

[0045] Step S206, programming corresponding data to be programmed in the addressing area to be programmed, wherein the data to be programmed includes first data and second data.

[0046] Specifically, through the output voltage of the timing control module and the addressing area mapping table, it is determined that the addressing area to be burned has been selected and placed in a programmable (writable) state. Burning operation refers to the process of writing data into the Flash IC. In the addressing area to be burned, data will be written in a predetermined order and format.

[0047] The data to be programmed usually includes two different types of data. According to the design of the programming process, the first data and the second data may need to be programmed into the Flash IC in a specific order. It can be that all the first data is programmed first, and then the second data is programmed; or the first data and the second data are programmed alternately in different addressing areas.

[0048] Step S208, after the data burning is completed, the current cyclic redundancy check values ​​of all areas in the Flash IC flash memory chip are obtained.

[0049] Specifically, after burning each portion of data, a verification step is usually performed to ensure that the data is correctly written into the Flash IC flash memory chip, that is, calculating and verifying the CRC (cyclic redundancy check) value of the first data and the second data just written.

[0050] Among them, CRC is an error detection algorithm that generates a fixed-length check value by performing polynomial division. This value can detect errors in data transmission or storage. The basic idea of ​​CRC check is to treat the data as a polynomial, and then divide this polynomial by a predetermined generator polynomial. The remainder is the CRC check value. This value is then appended to the data to detect the integrity of the data. The calculation of CRC can be implemented in hardware or software. For example, the STM32 microcontroller has a built-in CRC calculation unit that can automatically perform CRC calculation on the data.

[0051] Step S210, comparing and verifying the current cyclic redundancy check value and the preset cyclic redundancy check value to obtain a data burning self-test result.

[0052] Specifically, the calculated current CRC value is compared with the preset CRC value. If the two values ​​are the same, it means that the data is not damaged during the burning process and the burning is successful. If the two values ​​are different, it means that the burned data may be disturbed or damaged during the burning process, and an error occurred during the burning process. This process is an automatic detection mechanism that can verify the correctness of the burning operation without human intervention. In this way, it can ensure that the data in the Flash IC is reliable and stable, thereby improving the performance and reliability of the entire system.

[0053] In the data burning and self-checking method of the display panel, by accurately controlling the addressing area to be burned in the Flash IC during the burning process and placing other areas in a latched state, the influence of external interference signals on the data in the non-burning area can be effectively prevented, thereby improving the reliability of data burning. Since the risk of mistakenly erasing or rewriting the data in the non-burning area is reduced, the adoption of this scheme can enhance the stability of the OLED display device and reduce the equipment failure rate caused by data damage. Through the timing control module and the addressing area mapping table, the precise control of the burning process is realized, making the burning operation more efficient and simplifying the burning process. After the data burning is completed, by obtaining the cyclic redundancy check value (CRC) of all areas in the Flash IC and comparing and verifying with the preset value, the self-check of the burned data is realized to ensure the integrity and correctness of the data. Due to the optimization of the burning process and the realization of the self-checking function, the number of repeated burning times required due to data errors can be reduced, thereby saving time and cost and improving production efficiency. The realization of the self-checking function enables the burning errors to be quickly discovered and corrected during the production process, simplifies the fault diagnosis and testing process, and reduces the workload of subsequent maintenance and detection. It can maintain the accuracy of data burning even in the presence of external interference signals, allowing the display device to maintain stable performance under various environmental conditions.

[0054] In an exemplary embodiment, the first data is TP firmware data, the second data is Demura compensation data, and the types of the addressing area to be burned include TP firmware addressing area and Demura compensation addressing area;

[0055] like Figure 3 As shown, burning corresponding data to be burned in the addressing area to be burned includes steps S302 to S304. Among them:

[0056] Step S302, after burning the TP firmware data in the TP firmware addressing area, burning the Demura compensation data in the Demura compensation addressing area;

[0057] Step S304, or, after burning the demura compensation data in the demura compensation addressing area, burning the TP firmware data in the TP firmware addressing area.

[0058] Specifically, Figure 4 As shown in the figure, the main data partition diagram of the TDDI flash memory chip is shown. First, in the TP firmware addressing area (i.e. Figure 4The TP firmware data is burned into the FW addressing area shown in the figure. This is achieved by coordinating the EN (Enable) timing signal to ensure that only the FW (Firmware) addressing area is operated. After the burning is completed, the CRC1 value of the area is calculated and compared with the CRC1 value of the original firmware before burning. If the comparison result is consistent (OK), the CRC1 value is burned into the blank area in the TP firmware addressing area. In this way, the CRC1 value can be used for subsequent integrity checks.

[0059] In another embodiment, the demura compensation data is first burned in the demura compensation addressing area. Again, this is achieved by coordinating the EN timing signal to ensure that only the demura compensation addressing area is operated. After the burning is completed, the CRC2 value of the area is calculated and compared with the original CRC2 value before burning. If the comparison result is consistent (OK), the CRC2 value is burned in the blank area in the demura compensation addressing area. In this way, the CRC2 value can be used for subsequent integrity checks.

[0060] The solution allows two burning orders, which can be flexibly selected according to actual needs and system configuration. For example, if TP firmware data has a higher priority, TP firmware data may be burned first; conversely, if demura compensation data needs to be processed first, demura compensation data may be burned first.

[0061] In this embodiment, by calculating and verifying the CRC value after each programming, the security and reliability of the data programming process are significantly improved, and even under external interference, the data programmed into the Flash IC can be ensured to be correct and complete.

[0062] In an exemplary embodiment, Figure 5 As shown, after the data burning is completed, the current cyclic redundancy check values ​​of all areas in the Flash IC flash memory chip are obtained, including steps S502 to S504. Among them:

[0063] Step S502, after burning the TP firmware data and the Demura compensation data, respectively obtaining the current cyclic redundancy check values ​​of all areas in the FlashIC flash memory chip;

[0064] Step S504, or, after burning the TP firmware data and the Demura compensation data, obtaining the current cyclic redundancy check values ​​of all areas in the Flash IC flash memory chip.

[0065] Specifically, after the TP firmware data is burned, the CRC values ​​of all areas in the Flash IC are immediately obtained (recorded as CRC1). Similarly, after the Demura compensation data is burned, the CRC values ​​of all areas in the Flash IC are obtained again (recorded as CRC2). This is accomplished by executing step S503. The advantage of this method is that each burning operation can be verified separately, and errors that may occur during each burning process can be discovered and corrected in a timely manner. This can reduce the problem of relying on erroneous data that may occur in subsequent burning operations.

[0066] Alternatively, burn the TP firmware data first, but do not obtain the CRC value immediately. Then burn the Demura compensation data, and also do not obtain the CRC value immediately. After completing all the burning operations, obtain the CRC values ​​of all areas in the Flash IC at one time. This is done by executing step S504. The advantage of this method is that it can provide an overall data integrity check after all the burning operations are completed. If there is a dependency between the burning operations, or it is necessary to ensure the consistency of all data as a whole, this method may be more appropriate.

[0067] In actual applications, the strategy to choose depends on many factors, including the complexity of the programming operation, the importance of the data, the system's ability to recover from errors, etc. For example, if the programming operation is relatively simple and the system can tolerate a certain risk of error, it may be chosen to perform a one-time verification after all programming is completed. On the contrary, if the programming operation is more complicated, or the system needs to ensure the accuracy of each step of the operation, it may be chosen to perform a verification after each programming.

[0068] In this embodiment, by setting different verification strategies according to actual applications, it can be ensured that the data burned into the Flash IC is accurate to ensure the reliability and stability of the system. By obtaining and verifying the CRC value, errors can be found and corrected in time during the burning process, thereby improving the overall data processing quality.

[0069] In an exemplary embodiment, the timing control module is electrically connected to at least one of an output pin of the integrated circuit IC or an output pin of the flexible printed circuit board FPC, and is used to output an output voltage having at least one voltage state according to the burning driving signal.

[0070] Specifically, the timing control module is electrically connected to the output pins of the integrated circuit IC or the output pins of the FPC. These pins are connected from the internal circuit of the chip to the peripheral circuit, forming the interface of the chip.

[0071] Electrical connection means that the timing control module is connected to the output pin of the IC or FPC through a conductive path. This connection can be a direct physical connection or can be achieved through traces on a circuit board or other types of electrical connections.

[0072] Among them, the output pins of the integrated circuit (IC) are the interfaces for the IC to interact with the external circuit. These pins can transmit control signals, data signals or power supply voltage, etc. During the burning process, the timing control module needs to control the burning timing of the Flash IC through these output pins. A flexible printed circuit board (FPC) is a flexible circuit board that also has pins for connecting electronic components. Due to its flexible characteristics, FPC can be bent and folded, and is suitable for applications where space is limited or flexible connections are required.

[0073] It is explained that the timing control module needs to be electrically connected to at least one of the output pins of the IC or the output pins of the FPC. Or it can be connected to both at the same time as needed to achieve more complex timing control or to provide a more stable power supply and signal path. Through this electrical connection, the timing control module can accurately control the voltage state and timing during the burning process to ensure that the Flash IC burns data at the correct voltage and timing. The way to achieve this electrical connection may include welding, socket connection, fixture fixation or the use of conductive glue. The specific connection method depends on factors such as design requirements, space limitations and production costs.

[0074] In this embodiment, by setting different electrical connection modes of the timing control modules, it is ensured that the programming operation can be performed under precisely controlled voltage and timing conditions, thereby improving the programming reliability and data integrity.

[0075] In an exemplary embodiment, the timing control module includes: a burning drive signal receiving submodule for receiving a burning drive signal, a burning drive signal identifying submodule for identifying the burning drive signal, and a voltage output submodule for outputting an output voltage having at least one voltage state.

[0076] like Figure 6 As shown, the timing control module is a key component in the burning system, which is responsible for managing the voltage and timing during the FlashIC burning process. This module consists of three sub-modules, each of which has different functions to ensure the correctness of the burning operation and the integrity of the data. The following is a detailed explanation of these three sub-modules:

[0077] The function of the programming drive signal receiving submodule is to receive the external programming drive signal. The programming drive signal is the instruction to start the programming operation, which notifies the timing control module to start the programming process. The programming drive signal may come from the system's main controller, microcontroller or other control logic, which triggers the start of the programming process.

[0078] The function of the programming drive signal identification submodule is to detect and verify whether the received programming drive signal is valid. This may include checking whether the format, frequency or voltage level of the signal meets the expected standards. If the programming drive signal does not meet the requirements, the identification submodule may reject the signal and send an error indication, thereby preventing incorrect programming operations.

[0079] The function of the voltage output submodule is to output an output voltage with at least one voltage state according to the received and recognized programming drive signal. These voltage states meet the voltage requirements of the Flash IC at different programming stages. The output voltage may include different voltage levels for erase, program (write) and read operations. The voltage output submodule ensures that these voltages are applied to the Flash IC at the correct timing.

[0080] The workflow of the timing control module is as follows:

[0081] When the programming operation needs to start, the programming drive signal receiving submodule receives the start signal. The programming drive signal identification submodule verifies the validity of this signal. Once the signal is confirmed to be valid, the voltage output submodule outputs the corresponding voltage state to the Flash IC according to the preset timing and voltage requirements. During the programming process, the voltage output submodule may switch to different voltage states as needed to complete data erasing, writing and other operations. After the programming is completed, the voltage output submodule outputs another voltage state to end the programming process and enter the reading or other mode.

[0082] In this embodiment, the entire timing control module is designed to ensure that the Flash IC can complete the burning under the conditions of accurately controlled voltage and timing, thereby improving the reliability of burning and the integrity of data. This modular design also contributes to the flexibility and maintainability of the burning system.

[0083] In an exemplary embodiment, the timing control module is connected to a gating circuit;

[0084] The control end of the gating circuit is electrically connected to the voltage output submodule, and is used to determine the addressing area to be burned in the Flash IC flash memory chip corresponding to the output voltage of the timing control module according to the voltage state and the addressing area mapping table, and to select any one of the first output end of the gating circuit and the second output end of the gating circuit;

[0085] The first output end of the gating circuit is electrically connected to the signal line of the TP firmware addressing area; the second output end of the gating circuit is electrically connected to the signal line of the Demura compensation addressing area.

[0086] Specifically, Figure 7 The gating circuit is shown. The timing control module is responsible for managing the voltage and timing during the Flash IC burning process. It is electrically connected to the control end of the gating circuit and can control the behavior of the gating circuit. The control end of the gating circuit receives a signal from the voltage output submodule (i.e., the data-IC shown in the figure). The voltage output submodule outputs specific voltage states according to the instructions of the timing control module. These states are associated with the addressing area mapping table to determine the specific addressing area in the Flash IC that needs to be burned.

[0087] The gating circuit selectively connects its first output terminal or second output terminal according to the voltage state signal received by the control terminal. This selective connection is called "gating" because it allows current to flow to a specific addressing area in the Flash IC. For example, the SW1 signal corresponds to the gating of the first output terminal, and the SW2 signal corresponds to the gating of the second output terminal.

[0088] For example, the first output end of the gating circuit is electrically connected to the storage TP firmware addressing area (i.e., the FW addressing area). When the TP firmware data needs to be burned, the gating circuit will select its first output end (i.e., data-F, FW data in the figure). The second output end of the gating circuit is electrically connected to the storage Demura compensation addressing area. When the Demura compensation data needs to be burned, the gating circuit will select its second output end (i.e., data-D, Demura data in the figure).

[0089] The gating circuit ensures that during the programming process, only the gating addressing area (TP firmware addressing area or Demura compensation addressing area) receives the programming data, while other addressing areas remain unchanged. This helps prevent data conflicts and ensure data accuracy.

[0090] In this embodiment, the timing control module accurately selects a specific addressing area in the Flash IC for programming by controlling the gating circuit. This design allows the system to switch between different addressing areas to program different types of data while ensuring the integrity of the data and the reliability of the Flash IC.

[0091] In an exemplary embodiment, before burning corresponding data to be burned in the addressing area to be burned, the method further includes:

[0092] When the voltage state is the first gradient voltage, the gating circuit controls the TP firmware addressing area to be in an open state, and other areas except the TP firmware addressing area are in a latched state; when the voltage state is the second gradient voltage, the gating circuit controls the Demura compensation addressing area to be in an open state, and other areas except the Demura compensation addressing area are in a latched state;

[0093] Or, when the voltage state is a first gradient voltage, the gating circuit controls the Demura compensation addressing area to be in an on state, and other areas except the Demura compensation addressing area are in a latched state; when the voltage state is a second gradient voltage, the gating circuit controls the TP firmware addressing area to be in an on state, and other areas except the TP firmware addressing area are in a latched state.

[0094] Specifically, the first gradient voltage and the second gradient voltage correspond to different addressing areas and programming processes respectively. Figure 8 The signal timing diagram of TP firmware data and Demura compensation data is shown, and the waveform diagram of EN signal and data (DATA) shows the timing of the burning process. The high and low changes of EN signal correspond to different burning stages, while DATA signal represents the actual burning data.

[0095] For example, Figure 8 As shown in the figure, the EN timing signal is used to control the start of the burning process. When EN is a high voltage, it indicates that the TP firmware data is started to be burned; when EN is a low voltage, it indicates that the Demura compensation data is started to be burned. The voltage state is output by the timing control module and controls which addressing area is activated through the gating circuit.

[0096] Under high voltage, the TP firmware addressing area is controlled by the gating circuit to be turned on, allowing the burning operation, while other areas (such as the Demura compensation addressing area) are in a latched state to prevent data from being accidentally modified. Under low voltage, the Demura compensation addressing area is controlled by the gating circuit to be turned on, allowing the burning operation, and other areas (such as the TP firmware addressing area) are in a latched state.

[0097] It should be noted that, in other embodiments, when EN is a high voltage, it indicates that the TP firmware data is started to be burned; when EN is a low voltage, it indicates that the Demura compensation data is started to be burned.

[0098] In this embodiment, through precise timing control and voltage timing management, independent programming of different addressing areas in the Flash IC is achieved, the safety and reliability of the programming process are improved, and the accuracy of the programming data is ensured.

[0099] In an exemplary embodiment, the gate circuit is integrated inside the display panel or inside the flexible printed circuit board FPC.

[0100] Specifically, as part of the display panel design, the gating circuit is directly integrated into the internal circuit of the display panel. In this way, the gating circuit can work closely with other electronic components on the panel to achieve precise timing control and data burning.

[0101] Flexible printed circuit board (FPC) is a bendable circuit board that is often used in applications where space is limited or flexible wiring is required. Alternatively, the gating circuit is integrated inside the FPC and can work together with other circuit elements on the FPC (such as connectors, signal cables, etc.) to provide the necessary signal control for the display panel.

[0102] It should be noted that integrating the gating circuit into the display panel or FPC requires consideration of the circuit board layout, optimization of the signal path, and compatibility with other system components.

[0103] In this embodiment, integrating the gating circuit inside the display panel or FPC is a design method that embeds necessary functions directly into the main components, which helps to achieve compactness, efficiency and cost-effectiveness.

[0104] In an exemplary embodiment, the effective burning period for receiving the burning driving signal includes a burning period for TP firmware data and a burning period for Demura compensation data.

[0105] Specifically, the programming drive signal is a signal that starts and controls the programming operation. It is usually sent by the system's main controller or programmer to instruct the Flash IC to start the data programming process. The effective programming period refers to the time interval when the programming drive signal is in a valid state (such as a high level or a low level). During this period, the Flash IC will receive and process the programming data.

[0106] Among them, TP firmware data refers to the firmware data of the touch panel, which is responsible for controlling the touch function. Burning period refers to the time interval specifically allocated for burning TP firmware data within the effective burning period. Demura compensation data is data used to improve the color uniformity of the display panel. Burning period refers to the time interval specifically allocated for burning Demura compensation data within the effective burning period.

[0107] The programming process involves multiple different data types, each of which may require different programming conditions or sequences. Therefore, the entire valid programming period is subdivided into multiple sub-periods, each corresponding to the programming of a data type. The timing control module is responsible for managing the conversion and coordination of these different programming periods to ensure that the data is programmed into the appropriate addressing area of ​​the Flash IC in the correct order. The timing of the programming drive signal is directly related to the accuracy and integrity of the data programming. Accurate timing control can prevent data misalignment, loss or damage.

[0108] In this embodiment, during the burning process, there are specific and controlled burning time periods for different types of data (such as TP firmware data and Demura compensation data). By accurately controlling these time periods, the burning operation can be ensured to proceed smoothly while maintaining data integrity and system reliability.

[0109] In an exemplary embodiment, at least one of the burning period of the TP firmware data or the burning period of the demura compensation data is at least one.

[0110] Specifically, within the operation cycle, there is at least one period for burning the TP firmware data or the Demura compensation data, and this period can be continuous or staggered.

[0111] For example, the burning period can be continuous, that is, one after another without interruption. For example, the TP firmware data is burned continuously first, and then the Demura compensation data is burned. The burning period can also be staggered, that is, during the burning process, the burning periods of the TP firmware data and the Demura compensation data are alternately performed. For example, the operation of burning the Demura compensation data is inserted in the gap of burning the TP firmware data.

[0112] An example of continuous programming is: Assume that the programming cycle of a display panel includes two main steps: programming TP firmware data and programming Demura compensation data. If in a certain cycle, the TP firmware data is programmed first, and then the Demura compensation data is programmed.

[0113] An example of interleaved burning is if the burning of TP firmware data is paused in the middle, and then the burning of demura compensation data begins, and then the burning of the remaining TP firmware data continues.

[0114] The programming process is usually precisely controlled by the timing control module to ensure that the correct programming operation is performed at the right time. The gating circuit plays a key role in this process. It selectively enables the corresponding programming period according to the signal of the timing control module, while keeping other areas in a latched state to avoid misoperation.

[0115] In this embodiment, in one programming cycle, at least one programming period of a data type is executed, and this programming period can be continuous or staggered. This design provides flexibility in programming operations to meet different production requirements and optimize programming efficiency.

[0116] In an exemplary embodiment, Fig. 9 As shown, the corresponding data to be burned is burned in the addressing area to be burned, including:

[0117] Step S902, obtaining the data capacity of the data to be burned;

[0118] Step S904, determining a target addressing area suitable for accommodating the data to be burned in the addressing area to be burned according to the data capacity;

[0119] Step S906, burning the corresponding data to be burned in the target addressing area.

[0120] Specifically, before burning, you first need to know the size or capacity of the data to be burned, in order to ensure that there is enough space to store the data and avoid overflow or shortage. Based on the acquired data capacity, the system will determine which part of the addressing area to be burned (the target addressing area) has enough space to accommodate the data. This may involve an analysis of the storage structure and used space of the Flash IC. Once the target addressing area is determined, the next step is to actually burn the corresponding data to be burned in the area, that is, write the data into a specific storage unit.

[0121] Example description: Assume that there is a Flash storage of a display panel and the TP firmware data and Demura compensation data need to be updated:

[0122] Step 1: First measure or determine the size of the TP firmware data and demura compensation data to be burned.

[0123] Step 2: Based on the size of the data, check the Flash storage to determine which area can accommodate the data. For example, if the TP firmware data requires 2MB of space and the Demura data requires 1MB, the system will look for an unoccupied area that is large enough.

[0124] Step 3: Burn data in the determined area (such as TP firmware addressing area and Demura compensation addressing area). This may involve erasing old data and writing new data.

[0125] In this embodiment, by determining the target addressing area suitable for accommodating the data to be burned in the addressing area to be burned according to the data capacity, it can be ensured that the data is burned to the correct location and all related data can be properly processed, thereby ensuring that the function and performance of the display panel are not affected. At the same time, correct addressing and burning process management helps to prevent data loss and ensure system stability.

[0126] In an exemplary embodiment, obtaining current cyclic redundancy check values ​​of all regions in a Flash IC flash memory chip includes:

[0127] Initialize the cyclic redundancy check register in the Flash IC flash memory chip to obtain an initial cyclic redundancy check value; read data blocks from all areas of the Flash IC flash memory chip in sequence; process the first read data block and the initial cyclic redundancy check value bit by bit to obtain a processing result; update the initial cyclic redundancy check value according to the processing result, and process the next read data block and the updated cyclic redundancy check value bit by bit; use the updated cyclic redundancy check value corresponding to the last read data block as the current cyclic redundancy check value.

[0128] Specifically, first, the CRC register in the Flash IC is initialized and an initial CRC value is set. Usually, this value is predefined, such as 0xFFFFFFFF or 0x00000000000.

[0129] Then, the system reads data blocks from all areas of the Flash IC in sequence. A data block is a certain size fragment of data in the Flash memory. The first data block read is processed bit by bit with the initial CRC value, which involves a CRC algorithm that calculates a result based on a specific polynomial and data bits. Based on the processing result of the first data block, the CRC value is updated. This updated CRC value is used for the CRC calculation of the next data block. The next data block read is processed bit by bit with the updated CRC value and the CRC value is updated again. This process is repeated until all data blocks are processed.

[0130] Finally, the updated CRC value corresponding to the read data block will be used as the current CRC value of the Flash IC. This value reflects the CRC check result of all read data blocks.

[0131] Example: Assume that the Flash storage is divided into three data blocks A, B, and C:

[0132] Step 1: Initialize the CRC value to 0xFFFFFFFF.

[0133] Step 2: Read data block A and perform CRC algorithm processing with the initial CRC value. Assume that the result is 0xABCDEFGH.

[0134] Step 3: Read data block B and process it with 0xABCD EFGH to get the new CRC value 0xIJKL MNO.

[0135] Step 4: Read data block C and process it with 0xIJKL MNOP to get the final CRC value 0xQRS TUV.

[0136] The final CRC value 0xQRS TUV represents the CRC check result of all data blocks in the Flash IC. This value is used for subsequent data integrity check or error detection. If it matches the expected CRC value, it means that the data is complete and there is no error; if it does not match, it means that the data may be damaged or an error occurred during transmission.

[0137] In this embodiment, by calculating and comparing the CRC value, it can be verified whether the data stored in the Flash IC is complete and has not been accidentally modified or damaged. By ensuring the correct burning and storage of data, the stability and performance of the entire system are improved.

[0138] In an exemplary embodiment, the addressing area to be burned includes a data occupied area and a to-be-used area, and the data occupied area is used to store the data to be burned; after comparing and verifying the current cyclic redundancy check value and the preset cyclic redundancy check value to obtain the data burning self-test result, it also includes:

[0139] When it is determined based on the data burning self-check result that the current cyclic redundancy check value is verified to be consistent with the cyclic redundancy check preset value, the current cyclic redundancy check value is burned into the area to be used.

[0140] Specifically, the burning addressing area is divided into two parts: a data occupied area and an area to be used. The data occupied area is an area actually used to store the burned data.

[0141] After burning the data, the system will calculate the cyclic redundancy check value (CRC) of the current data. This CRC value is used to verify the integrity and correctness of the burned data. The calculated current CRC value is compared with the preset CRC value (preset cyclic redundancy check value) to determine whether the burned data is correct. If the current CRC value matches the preset CRC value, it means that the burned data is complete and not damaged. In this case, the system will burn the current CRC value to the unused area. The unused area is the unused part of the burning address area, which is used to store or process additional information, such as the CRC value. The purpose of this is to record the results of the burning operation for future verification or diagnosis.

[0142] In this embodiment, the integrity protection of the data is increased by burning the CRC value into the area to be used. The CRC value of this area can be read later to verify whether the data has been tampered with or damaged during subsequent storage or transmission.

[0143] In an exemplary embodiment, after comparing and verifying the current cyclic redundancy check value and the preset cyclic redundancy check value to obtain the data burning self-test result, the method further includes:

[0144] When it is determined based on the data burning self-check result that the current cyclic redundancy check value and the cyclic redundancy check preset value are inconsistent in verification, the data to be burned that has been stored in the data occupied area is cleared, and the step of burning the corresponding data to be burned in the addressing area to be burned is re-executed; the cumulative number of consecutive verification inconsistencies is obtained; and when the cumulative number reaches a preset number threshold, the cyclic redundancy check preset value is adjusted.

[0145] Specifically, after burning the data, the system will calculate the current cyclic redundancy check value (CRC) and compare and verify it with the preset CRC value (preset cyclic redundancy check value) to obtain the self-test result of data burning. If the self-test result shows that the current CRC value is inconsistent with the preset value, this indicates that there may be errors in the burned data. In this case, the system will clear the data to be burned that has been stored in the data occupied area, that is, delete or erase those data that may be erroneous. Then, the system will re-execute the burning step, that is, re-burn the data to be burned to the addressing area to be burned, and try to perform the burning operation again.

[0146] The system will record the cumulative number of consecutive verification inconsistencies, that is, the number of consecutive CRC value comparisons that result in inconsistency. When the cumulative number of verification inconsistencies reaches a preset threshold (preset number threshold), the system will take corresponding adjustment measures. This includes adjusting the preset value of the cyclic redundancy check to adapt to possible data changes or changes in burning conditions. This design ensures high accuracy and reliability of data burning. Through the comparison and verification of CRC values, burning errors are discovered and corrected in a timely manner. The re-burning mechanism provides a second chance for the correct storage of data, reducing system failures or performance issues caused by burning errors. The record of the cumulative number of times and the adjustment measures after reaching the threshold provide the system with adaptability to cope with possible environmental changes or changes in data characteristics, maintaining long-term stability and reliability.

[0147] In this embodiment, a closed-loop data integrity protection mechanism is formed through CRC checking, error re-burning and condition adjustment, which significantly improves the reliability of the data burning process and the stability of the system.

[0148] In an exemplary embodiment, other areas except the addressing area to be burned include at least one buffer area for temporarily storing the data to be burned; wherein each addressing area to be burned is connected to at least one buffer area.

[0149] Specifically, the addressing area to be burned is a specific area in the Flash IC that is predetermined to store the burning data. In addition to the addressing area to be burned, there are other areas in the Flash IC, including at least one buffer for temporarily storing the data to be burned. The buffer plays a role in temporarily storing data during the data burning process, which helps to manage the data flow and ensure the stability and efficiency of the data burning. The buffer can temporarily store data to be burned into the Flash IC, or store intermediate data generated during the burning process. Each addressing area to be burned is connected to at least one buffer, which helps to quickly access and process data during the burning process. The buffer can provide necessary data support for the addressing area to be burned to ensure the continuity and efficiency of the burning operation.

[0150] Example: Assume that there are three addressing areas to be programmed in the Flash IC design, and each addressing area is connected to a buffer. During the programming operation, the data is first written into the buffer, and then transferred from the buffer to the addressing area to be programmed to complete the programming.

[0151] In this embodiment, by configuring at least one buffer in the addressing area to be burned, the efficiency and reliability of data burning are improved, ensuring the smooth progress of the burning operation. The use of the buffer can optimize the burning process, especially when processing a large amount of data, the buffer can be used to balance the data flow and avoid burning bottlenecks.

[0152] In an exemplary embodiment, after the data burning is completed, the method further includes:

[0153] Receive a data retrieval instruction for a Flash IC flash memory chip; in response to the data retrieval instruction, transfer the target data in the corresponding addressing area to be burned to the buffer; and retrieve the target data from the buffer according to the data retrieval method in the data retrieval instruction.

[0154] Specifically, after the data is burned, the system will receive data retrieval instructions for the Flash IC. These instructions are used to request to read or extract data stored in the Flash IC. In response to the received data retrieval instructions, the Flash IC transfers the target data in the addressing area to be burned to the buffer. This step is to prepare the data so that it can be further processed or transferred to other system parts. According to the method specified in the data retrieval instruction, the system extracts the target data from the buffer. The data retrieval method may include reading a specific part of the data, all the data, or data organized in a certain format.

[0155] Example: Assume that an embedded system needs to verify the update after updating the firmware in the Flash IC:

[0156] Step 1: The system sends a data retrieval command to the Flash IC, requesting to read the newly burned firmware data.

[0157] Step 2: The Flash IC recognizes the instruction and transfers the firmware data from its storage area to the internal buffer.

[0158] Step 3: The system extracts data from the buffer according to the instruction, and may perform verification or execute in memory to ensure that the firmware update is correct.

[0159] In this embodiment, it is ensured that after data burning is completed, data can be effectively managed and extracted to meet the reading or further processing requirements of the system. By using the buffer as intermediate storage, the data transmission process is optimized and the speed and efficiency of data access are improved. Flexible data retrieval methods are allowed, so that the system can obtain data in different ways according to specific needs, which increases the adaptability and flexibility of operations.

[0160] It should be understood that, although the various steps in the flow charts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flow charts involved in the above-mentioned embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0161] Based on the same inventive concept, the embodiment of the present application also provides a data burning and self-testing device for a display panel for implementing the data burning and self-testing method for a display panel involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the data burning and self-testing device for one or more display panels provided below can refer to the limitations of the data burning and self-testing method for a display panel above, and will not be repeated here.

[0162] The display device may be a display device such as a mobile phone or a tablet computer. Fig.10 , shows a schematic diagram of a display device in an embodiment, and the display device 100 may include a display panel 1002. The display panel may be an organic light emitting diode (OLED) display panel.

[0163] In an exemplary embodiment, Fig.10 As shown, a data burning and self-testing device for a display panel is provided, comprising: a timing control module 1102, which is used to output an output voltage having at least one voltage state when it is detected that a Flash IC flash memory chip receives a burning drive signal;

[0164] The processing module 1104 is used to determine the addressing area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module 1102 according to the voltage state and the addressing area mapping table, and control other areas except the addressing area to be programmed to be in a latched state;

[0165] The programming module 1106 is used to program the corresponding data to be programmed in the addressing area to be programmed, where the data to be programmed includes the first data and the second data;

[0166] The acquisition module 1108 is used to acquire the current cyclic redundancy check value of all areas in the Flash IC flash memory chip after the data burning is completed;

[0167] The self-check module 1110 is used to compare and verify the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-check result.

[0168] In an exemplary embodiment, the first data is TP firmware data, the second data is Demura compensation data, and the types of the addressing area to be burned include TP firmware addressing area and Demura compensation addressing area;

[0169] The burning module 1106 is specifically used to burn the demura compensation data in the demura compensation addressing area after burning the TP firmware data in the TP firmware addressing area; or, burn the TP firmware data in the TP firmware addressing area after burning the demura compensation data in the demura compensation addressing area.

[0170] In an exemplary embodiment, the acquisition module 1108 is specifically used to obtain the current cyclic redundancy check values ​​of all areas in the Flash IC flash chip after burning the TP firmware data and after burning the Demura compensation data; or, after burning the TP firmware data and the Demura compensation data, obtain the current cyclic redundancy check values ​​of all areas in the Flash IC flash chip.

[0171] In an exemplary embodiment, the timing control module 1102 is electrically connected to at least one of an output pin of the integrated circuit IC or an output pin of the flexible printed circuit board FPC, and is used to output an output voltage having at least one voltage state according to the burning driving signal.

[0172] In an exemplary embodiment, the timing control module 1102 includes: a burning drive signal receiving submodule for receiving a burning drive signal, a burning drive signal identifying submodule for identifying the burning drive signal, and a voltage output submodule for outputting an output voltage having at least one voltage state.

[0173] In an exemplary embodiment, the timing control module 1102 is connected to a gating circuit; the control end of the gating circuit is electrically connected to a voltage output submodule, which is used to determine the addressing area to be burned in the Flash IC flash memory chip corresponding to the output voltage of the timing control module 1102 according to a voltage state and an addressing area mapping table, and to select any one of the first output end of the gating circuit and the second output end of the gating circuit; the first output end of the gating circuit is electrically connected to the signal line of the TP firmware addressing area; the second output end of the gating circuit is electrically connected to the signal line of the Demura compensation addressing area.

[0174] In an exemplary embodiment, the processing module 1104 is also used to, when the voltage state is a first gradient voltage, control the TP firmware addressing area to be in an on state, and other areas except the TP firmware addressing area to be in a latched state; when the voltage state is a second gradient voltage, control the Demura compensation addressing area to be in an on state, and other areas except the Demura compensation addressing area to be in a latched state; or, when the voltage state is the first gradient voltage, control the Demura compensation addressing area to be in an on state, and other areas except the Demura compensation addressing area to be in a latched state; when the voltage state is the second gradient voltage, control the TP firmware addressing area to be in an on state, and other areas except the TP firmware addressing area to be in a latched state.

[0175] In an exemplary embodiment, the gate circuit is integrated inside the display panel or inside the flexible printed circuit board FPC.

[0176] In an exemplary embodiment, the effective burning period for receiving the burning driving signal includes a burning period for TP firmware data and a burning period for Demura compensation data.

[0177] In an exemplary embodiment, at least one of the burning period of the TP firmware data or the burning period of the demura compensation data is at least one.

[0178] In an exemplary embodiment, the burning module 1106 is further used to obtain the data capacity of the data to be burned; determine the target addressing area in the addressing area to be burned that is suitable for accommodating the data to be burned according to the data capacity; and burn the corresponding data to be burned in the target addressing area.

[0179] In an exemplary embodiment, the acquisition module 1108 is specifically used to initialize the cyclic redundancy check register in the Flash IC flash memory chip to obtain an initial cyclic redundancy check value; read data blocks from all areas of the Flash IC flash memory chip in sequence; process the first read data block and the initial cyclic redundancy check value bit by bit to obtain a processing result; based on the processing result, update the initial cyclic redundancy check value, and process the next read data block and the updated cyclic redundancy check value bit by bit; and use the updated cyclic redundancy check value corresponding to the last read data block as the current cyclic redundancy check value.

[0180] In an exemplary embodiment, the addressing area to be burned includes a data occupied area and a to-be-used area, and the data occupied area is used to store the data to be burned; the burning module 1106 is also used to burn the current cyclic redundancy check value into the to-be-used area when it is determined based on the data burning self-test result that the current cyclic redundancy check value and the cyclic redundancy check preset value are verified to be consistent.

[0181] In an exemplary embodiment, the burning module 1106 is further used to clear the stored data to be burned in the data occupied area and re-execute the step of burning the corresponding data to be burned in the addressing area to be burned, when it is determined based on the data burning self-check result that the current cyclic redundancy check value and the cyclic redundancy check preset value are verified to be inconsistent;

[0182] The acquisition module 1108 is further used to obtain the cumulative number of consecutive verification inconsistencies;

[0183] The processing module 1104 is further configured to adjust a cyclic redundancy check preset value when the accumulated number of times reaches a preset number threshold.

[0184] In an exemplary embodiment, other areas except the addressing area to be burned include at least one buffer area for temporarily storing the data to be burned; wherein each addressing area to be burned is connected to at least one buffer area.

[0185] In an exemplary embodiment, the processing module 1104 is used to receive a data retrieval instruction for a Flash IC flash memory chip; in response to the data retrieval instruction, transfer the target data in the corresponding addressing area to be burned to a buffer; and retrieve the target data from the buffer according to the data retrieval method in the data retrieval instruction.

[0186] Each module in the above-mentioned display panel data burning and self-test device can be implemented in whole or in part by software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the Flash IC flash memory chip in the form of hardware, or can be stored in the memory in the Flash IC flash memory chip in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules.

[0187] In an exemplary embodiment, a Flash IC flash memory chip is provided. The internal structure diagram of the Flash IC flash memory chip can be as follows: Fig.12 As shown. The Flash IC flash memory chip includes a processor, a memory, an input / output interface, a communication interface and an input device. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface and the input device are connected to the system bus through the input / output interface. Among them, the processor of the Flash IC flash memory chip is used to provide computing and control capabilities. The memory of the Flash IC flash memory chip includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the Flash IC flash memory chip is used to exchange information between the processor and an external device. The communication interface of the Flash IC flash memory chip is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (Near Field Communication, NFC) or other technologies. When the computer program is executed by the processor, a data burning and self-test method for a display panel is implemented.

[0188] Those skilled in the art will understand that Fig.12 The structure shown in the figure is only a block diagram of a partial structure related to the present application scheme, and does not constitute a limitation on the Flash IC flash memory chip to which the present application scheme is applied. The specific Flash IC flash memory chip may include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0189] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0190] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0191] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0192] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0193] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0194] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A data burning and self-testing method for a display panel, characterized in that: The method comprises: When it is detected that the Flash IC flash memory chip receives a programming drive signal, the timing control module outputs an output voltage having at least one voltage state; According to the voltage state and addressing area mapping table, determine the addressing area to be burned in the Flash IC flash memory chip corresponding to the output voltage of the timing control module, and control other areas except the addressing area to be burned to be in a latched state; Burning corresponding data to be burned in the addressing area to be burned, wherein the data to be burned includes first data and second data; After the data burning is completed, the current cyclic redundancy check values ​​of all areas in the Flash IC flash memory chip are obtained; The current cyclic redundancy check value is compared and verified with the preset cyclic redundancy check value to obtain the data burning self-test result.

2. The method according to claim 1, characterized in that The first data is TP firmware data, the second data is Demura compensation data, and the types of the addressing area to be burned include TP firmware addressing area and Demura compensation addressing area; The step of burning corresponding data to be burned in the addressing area to be burned comprises: After burning the TP firmware data in the TP firmware addressing area, burning the Demura compensation data in the Demura compensation addressing area; Or, after burning the demura compensation data in the demura compensation addressing area, the TP firmware data is burned in the TP firmware addressing area.

3. The method according to claim 2, characterized in that After the data burning is completed, obtaining the current cyclic redundancy check values ​​of all areas in the FlashIC flash memory chip includes: After burning the TP firmware data and after burning the Demura compensation data, respectively obtaining current cyclic redundancy check values ​​of all areas in the FlashIC flash memory chip; Or, after burning the TP firmware data and the Demura compensation data, the current cyclic redundancy check values ​​of all areas in the Flash IC flash memory chip are obtained.

4. The method according to claim 1, characterized in that: The timing control module is electrically connected to at least one of an output pin of an integrated circuit IC or an output pin of a flexible printed circuit board FPC, and is used to output an output voltage having at least one voltage state according to the burning driving signal.

5. The method according to claim 1, characterized in that The timing control module includes: a burning drive signal receiving submodule for receiving the burning drive signal, a burning drive signal identifying submodule for identifying the burning drive signal, and a voltage output submodule for outputting an output voltage having at least one voltage state.

6. The method according to claim 5, characterized in that The timing control module is connected to a gating circuit; The control end of the gating circuit is electrically connected to the voltage output submodule, and is used to determine the addressing area to be burned in the Flash IC flash memory chip corresponding to the output voltage of the timing control module according to the voltage state and the addressing area mapping table, and to select any one of the first output end of the gating circuit and the second output end of the gating circuit; The first output end of the gating circuit is electrically connected to the signal line of the TP firmware addressing area; the second output end of the gating circuit is electrically connected to the signal line of the Demura compensation addressing area.

7. The method according to claim 6, characterized in that Before burning the corresponding data to be burned in the addressing area to be burned, the method further comprises: When the voltage state is a first gradient voltage, the gating circuit controls the TP firmware addressing area to be in an open state, and other areas except the TP firmware addressing area to be in a latched state; when the voltage state is a second gradient voltage, the gating circuit controls the Demura compensation addressing area to be in an open state, and other areas except the Demura compensation addressing area to be in a latched state; Or, when the voltage state is a first gradient voltage, the gating circuit controls the Demura compensation addressing area to be in an on state, and other areas except the Demura compensation addressing area are in a latched state; when the voltage state is a second gradient voltage, the gating circuit controls the TP firmware addressing area to be in an on state, and other areas except the TP firmware addressing area are in a latched state.

8. The method according to claim 6, characterized in that The gating circuit is integrated inside the display panel or inside the flexible printed circuit board FPC.

9. The method according to claim 2, characterized in that: The effective programming period for receiving the programming driving signal includes a programming period for TP firmware data and a programming period for Demura compensation data.

10. The method according to claim 9, characterized in that At least one of the burning period of the TP firmware data or the burning period of the demura compensation data is at least one.

11. The method according to claim 1, characterized in that: The step of burning corresponding data to be burned in the addressing area to be burned comprises: Get the data capacity of the data to be burned; According to the data capacity, determining a target addressing area in the addressing area to be recorded that is suitable for accommodating the data to be recorded; The corresponding data to be recorded is recorded in the target addressing area.

12. The method according to claim 1, characterized in that The obtaining of current cyclic redundancy check values ​​of all regions in the Flash IC flash memory chip includes: Initializing a cyclic redundancy check register in the Flash IC flash memory chip to obtain an initial cyclic redundancy check value; Reading data blocks sequentially from all areas of the Flash IC flash memory chip; Processing the first read data block and the initial cyclic redundancy check value bit by bit to obtain a processing result; According to the processing result, the initial cyclic redundancy check value is updated, and the next read data block and the updated cyclic redundancy check value are processed bit by bit; The updated cyclic redundancy check value corresponding to the last read data block is used as the current cyclic redundancy check value.

13. The method according to claim 1, characterized in that The addressing area to be burned includes a data occupied area and a to-be-used area, wherein the data occupied area is used to store the data to be burned; After comparing and verifying the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-test result, the method further includes: When it is determined based on the data burning self-check result that the current cyclic redundancy check value is verified to be consistent with the cyclic redundancy check preset value, the current cyclic redundancy check value is burned into the area to be used.

14. The method according to claim 13, characterized in that After comparing and verifying the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-test result, the method further includes: In the case where it is determined based on the data burning self-check result that the current cyclic redundancy check value and the cyclic redundancy check preset value are verified to be inconsistent, clearing the data to be burned that has been stored in the data occupied area, and re-performing the step of burning the corresponding data to be burned in the addressing area to be burned; Get the cumulative number of consecutive verification inconsistencies; When the accumulated number of times reaches a preset number threshold, the cyclic redundancy check preset value is adjusted.

15. The method according to claim 1, characterized in that The other areas except the addressing area to be burned include at least one buffer area for temporarily storing the data to be burned; wherein each addressing area to be burned is connected to at least one buffer area.

16. The method according to claim 15, characterized in that After the data burning is completed, the method further includes: Receiving a data retrieval instruction for the Flash IC flash memory chip; In response to the data retrieval instruction, the target data in the corresponding addressing area to be burned is transferred to the buffer; The target data is retrieved from the buffer according to the data retrieval method in the data retrieval instruction.

17. A data burning and self-testing device for a display panel, characterized in that: The device comprises: A timing control module, which is used to output an output voltage having at least one voltage state when it is detected that the Flash IC flash memory chip receives a burning drive signal; A processing module, used for determining the addressing area to be burned in the Flash IC flash memory chip corresponding to the output voltage of the timing control module according to the voltage state and the addressing area mapping table, and controlling other areas except the addressing area to be burned to be in a latched state; A burning module, used for burning corresponding data to be burned in the addressing area to be burned, wherein the data to be burned includes first data and second data; An acquisition module, used for acquiring the current cyclic redundancy check values ​​of all areas in the Flash IC flash memory chip after the data burning is completed; The self-check module is used to compare and verify the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-check result.

18. A Flash IC flash memory chip, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 16 are implemented.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 16 are implemented.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 16 are implemented.

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