Data verification method and device of Flash memory, equipment and medium

Abstract

The invention relates to the field of data processing, and discloses a data verification method and device for a Flash memory, equipment and a medium, the method comprises the following steps: sending a data writing command to the Flash memory, and obtaining a first cyclic redundancy check code of page data corresponding to each storage unit when the Flash memory writes data; calculating a second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache region based on a cyclic redundancy check algorithm; judging whether the first cyclic redundancy check code is consistent with the second cyclic redundancy check code or not; if the first cyclic redundancy check code is consistent with the second cyclic redundancy check code, the data written into the Flash memory is correct, otherwise, the data written into the Flash memory is wrong. By means of the method, whether errors occur in the Flash data writing operation process or not can be accurately judged.

Description

Technical Field

[0001] The present invention relates to the technical field, and in particular to a data verification method, device, equipment and medium for a Flash memory. Background Art

[0002] In today's digital age, Flash memories based on ONFI and Toggle interfaces have become the core components of data storage in many electronic devices. However, the existing Flash technology architecture based on ONFI and Toggle interfaces has significant defects in data transmission. It only focuses on the basic data transmission process, but seriously ignores the construction of data protection transmission mechanism. In the data transmission link, when writing data from the Flash host to the Flash chip, there is a lack of built-in means to verify the accuracy and integrity of the data. Usually, only when the data reaches the application layer and is deeply processed can the data be found to be wrong, but at this time it is impossible to accurately determine whether the data error occurs in the write operation stage or the read operation stage.

[0003] In view of this, how to achieve effective data verification during Flash data transmission has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present invention provide a data verification method, device, equipment and medium for a Flash memory to solve the technical problem that the existing Flash technology architecture lacks data verification during data transmission.

[0005] In a first aspect, an embodiment of the present invention provides a data verification method based on a Flash memory, comprising:

[0006] Sending a write data command to the Flash memory, and obtaining a first cyclic redundancy check code of page data corresponding to each storage unit when the Flash memory writes data;

[0007] Calculate the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area based on the cyclic redundancy check algorithm;

[0008] Determine whether the first cyclic redundancy check code of the page data corresponding to each storage unit is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area when writing data to the Flash;

[0009] If the first cyclic redundancy check code of the page data corresponding to each storage unit when writing data to the Flash is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area, the data written to the Flash memory is correct, otherwise, the data written to the Flash memory is wrong.

[0010] In some embodiments, the step of calculating the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area based on the cyclic redundancy check algorithm includes:

[0011] Determining a cyclic redundancy check algorithm for calculating a second cyclic redundancy check code based on the acquired first cyclic redundancy check code, and acquiring a corresponding generating polynomial according to the determined cyclic redundancy check algorithm;

[0012] Obtaining page data corresponding to each storage unit in the Flash cache area, and initializing a cyclic redundancy check register according to a determined cyclic redundancy check algorithm;

[0013] Based on the initialized cyclic redundancy check register, the page data corresponding to each storage unit in the Flash cache area is processed bit by bit to obtain a second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area.

[0014] In some embodiments, the bit-by-bit processing of page data corresponding to each storage unit in the Flash cache area based on the initialized cyclic redundancy check register includes:

[0015] S1, fetching the data bits of the page data corresponding to each storage unit in the Flash cache area bit by bit, and performing an XOR operation on the data bits of the page data corresponding to each storage unit in the Flash cache area fetched and the highest bit of the cyclic redundancy check register;

[0016] S2, shifting the cyclic redundancy check register as a whole rightward by one bit, and storing the result of the XOR operation in the highest bit of the cyclic redundancy check register;

[0017] S3, judging whether the highest bit of the shifted cyclic redundancy check register is 1, if the highest bit of the cyclic redundancy check register is 1, performing an XOR operation on the cyclic redundancy check register and the corresponding generating polynomial;

[0018] S4. Repeat the above steps S1-S3 until all bits of the page data corresponding to each storage unit in the Flash cache area are processed.

[0019] In some embodiments, the step of determining whether a first cyclic redundancy check code of page data corresponding to each storage unit when writing data to the Flash is consistent with a second cyclic redundancy check code of page data corresponding to each storage unit in the Flash cache area includes:

[0020] Compare the first cyclic redundancy check code and the second cyclic redundancy check code bit by bit starting from the highest bit, to determine whether the values ​​of each bit of the first cyclic redundancy check code and the second cyclic redundancy check code are the same;

[0021] If all bits of the first cyclic redundancy check code and the second cyclic redundancy check code are the same, then it is determined that the first cyclic redundancy check code and the second cyclic redundancy check code are consistent, otherwise, they are inconsistent.

[0022] In some embodiments, after obtaining the first cyclic redundancy check code of the page data corresponding to each storage unit of the Flash memory when writing data, the data verification method further includes:

[0023] Acquire the data length of the first cyclic redundancy check code of the page data corresponding to each storage unit of the Flash memory when writing data, and increase the programming cache of each storage unit of the Flash memory according to the acquired data length of the first cyclic redundancy check code;

[0024] When the Flash memory is writing data, the data information of the first cyclic redundancy check code of the page data corresponding to each storage unit is stored in the increased programming cache of each storage unit.

[0025] In some embodiments, before sending a write data command to the Flash memory, the data verification method further includes:

[0026] Send an erase command to the Flash memory and set the cyclic redundancy check failure flag in the Flash memory to 0.

[0027] In some embodiments, the data verification method further includes:

[0028] If the data written into the Flash memory is wrong, a data rewrite command is sent to the Flash memory;

[0029] The Flash memory rewrites data in each storage unit of the Flash memory according to the received data rewriting command.

[0030] In a second aspect, an embodiment of the present invention provides a data verification device based on a Flash memory, the device comprising:

[0031] An acquisition module, used for sending a write data command to the Flash memory, and acquiring a first cyclic redundancy check code of page data corresponding to each storage unit when the Flash memory writes data;

[0032] A calculation module, used for calculating a second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area based on a cyclic redundancy check algorithm;

[0033] A judgment module, judging whether a first cyclic redundancy check code of page data corresponding to each storage unit when writing data to the Flash is consistent with a second cyclic redundancy check code of page data corresponding to each storage unit in the Flash cache area;

[0034] The verification module is configured to detect that if the first cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area when the Flash writes data, the data written by the Flash memory is correct; otherwise, the data written by the Flash memory is wrong.

[0035] In a third aspect, an embodiment of the present invention provides a computer device, the device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0036] Memory, which is used to store computer programs;

[0037] The processor is used to implement the steps of the method for controlling memory access based on the CPU as described in any one of the first aspects above when executing the program stored in the memory.

[0038] In a fourth aspect, the present invention proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method for controlling memory access based on a CPU as described in any one of the above-mentioned first aspects are implemented.

[0039] The data verification method, device, equipment and medium of the Flash memory proposed in the present invention send a write data command to the Flash memory, and obtain the first cyclic redundancy check code of the page data corresponding to each storage unit when the Flash memory writes data; calculate the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area based on the cyclic redundancy check algorithm; judge whether the first cyclic redundancy check code of the page data corresponding to each storage unit when the Flash writes data is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area; if the first cyclic redundancy check code of the page data corresponding to each storage unit when the Flash writes data is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area, the data written by the Flash memory is correct, otherwise, the data written by the Flash memory is wrong. The data verification method proposed in the present invention can accurately judge whether an error occurs during the Flash data write operation by comparing the first cyclic redundancy check code of the page data corresponding to each storage unit when the Flash writes data with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0041] Figure 1 A schematic diagram of a flow chart of a data verification method based on a Flash memory provided by an embodiment of the present invention;

[0042] Figure 2 A method provided by an embodiment of the present invention Figure 1 Schematic diagram of the process of step S20;

[0043] Figure 3 A method provided by an embodiment of the present invention Figure 1 Schematic diagram of the process of step S30;

[0044] Figure 4 A schematic diagram of the structure of a device for controlling memory access based on a CPU provided by an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of the structure of a computer device provided by an embodiment of the present invention;

[0046] Figure 6The present invention is a schematic diagram of a computer-readable storage medium structure. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] See also Figure 1 As shown, Figure 1 A schematic flow chart of a data verification method based on a Flash memory provided by an embodiment of the present invention, wherein the data verification method based on a Flash memory specifically comprises the following steps:

[0049] S10, sending a write data command to the Flash memory, and obtaining a first cyclic redundancy check code of the page data corresponding to each storage unit when the Flash memory writes data. Specifically, in an embodiment of the present invention, when the system needs to write data to the Flash memory, the Flash host sends a write data command to the Flash memory. After receiving the command, the Flash memory will calculate the first cyclic redundancy check code for the page data corresponding to each storage unit through a specific cyclic redundancy check algorithm.

[0050] S20, calculating the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area based on the cyclic redundancy check algorithm. Specifically, in the embodiment of the present invention, before the data is written into the Flash memory, the system will use the cyclic redundancy check algorithm to calculate the page data corresponding to each storage unit in the Flash cache area to generate a second cyclic redundancy check code, which will be used in subsequent verification steps to ensure that no error occurs in the data transmission process.

[0051] S30, judging whether the first cyclic redundancy check code of the page data corresponding to each storage unit when writing data to the Flash is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area. Specifically, in the embodiment of the present invention, by comparing the first cyclic redundancy check code with the second cyclic redundancy check code, it can be ensured that the data written into the Flash memory is consistent with the original data in the cache area, thereby ensuring the integrity and accuracy of the data.

[0052] S40. If the first cyclic redundancy check code of the page data corresponding to each storage unit is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area when Flash writes data, the data written by the Flash memory is correct, otherwise, the data written by the Flash memory is wrong. Specifically, in an embodiment of the present invention, after the data is written, the system will compare the first cyclic redundancy check code with the second cyclic redundancy check code. If the first cyclic redundancy check code and the second cyclic redundancy check code are consistent, it indicates that no error occurred during the data writing process and the data transmission is successful. If the first cyclic redundancy check code and the second cyclic redundancy check code are inconsistent, it indicates that an error may have occurred during the data writing process and further inspection and processing are required. If it is detected that the check codes are inconsistent, errors in data transmission can be discovered in time to avoid erroneous data from being continuously written into the Flash memory, effectively improving the reliability of the system and reducing the risks caused by data errors.

[0053] In some embodiments, a second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area is calculated based on a cyclic redundancy check algorithm. Figure 2 , Figure 2 A method provided by an embodiment of the present invention Figure 1 The schematic flow chart of step S20 in FIG. 1 includes:

[0054] Step S21: Determine a cyclic redundancy check algorithm for calculating a second cyclic redundancy check code based on the acquired first cyclic redundancy check code, and obtain corresponding generator polynomials according to the determined cyclic redundancy check algorithm. Specifically, the embodiment of the present invention can ensure that the calculation methods of the two check codes are consistent by determining the algorithm of the second cyclic redundancy check code based on the first cyclic redundancy check code, so as to avoid verification failure caused by algorithm mismatch. In addition, by obtaining the same generator polynomial as the first cyclic redundancy check code, it can be ensured that the calculation method of the second cyclic redundancy check code is completely consistent with the first cyclic redundancy check code, thereby improving the accuracy of the verification.

[0055] Step S22: Obtain page data corresponding to each storage unit in the Flash cache area, and initialize the cyclic redundancy check register according to the determined cyclic redundancy check algorithm. Specifically, in the embodiment of the present invention, the cyclic redundancy check register is initialized based on the determined cyclic redundancy check algorithm to ensure the accuracy of data preparation, improve the verification efficiency, and enhance the reliability of the verification.

[0056] Step S23: Based on the initialized cyclic redundancy check register, the page data corresponding to each storage unit in the Flash cache area is processed bit by bit to obtain a second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area. Specifically, in the embodiment of the present invention, during the storage or transmission of data, any change in one bit may affect its integrity and correctness, and the bit-by-bit processing can fully cover the page data corresponding to each storage unit in the Flash cache area.

[0057] In some embodiments, based on the initialized cyclic redundancy check register, the page data corresponding to each storage unit in the Flash cache area is processed bit by bit, including: S1, taking out the data bits of the page data corresponding to each storage unit in the Flash cache area bit by bit, and performing an XOR operation on the data bits of the page data corresponding to each storage unit in the Flash cache area taken out and the highest bit of the cyclic redundancy check register; S2, shifting the cyclic redundancy check register as a whole one bit to the right, and storing the result of the XOR operation in the highest bit of the cyclic redundancy check register; S3, judging whether the highest bit of the shifted cyclic redundancy check register is 1, if the highest bit of the cyclic redundancy check register is 1, performing an XOR operation on the cyclic redundancy check register and the corresponding generating polynomial; S4, repeating the above steps S1-S3 until all bits of the page data corresponding to each storage unit in the Flash cache area are processed. Specifically, in the embodiment of the present invention, during the bit-by-bit processing, the cyclic redundancy check register gradually accumulates characteristic information of the data by continuously performing XOR operations and shift operations with the data bits. Each bit of data affects the final check code, so that the generated check code can fully and accurately reflect the overall characteristics of the data. The bit-by-bit processing method has good modular characteristics in both hardware and software implementations, and can be easily integrated into the existing Flash storage system architecture.

[0058] In some embodiments, the first cyclic redundancy check code of the page data corresponding to each storage unit when the Flash writes data is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area. Figure 3 , Figure 3 A method provided by an embodiment of the present invention Figure 1 The flowchart of step S30 may include the following steps:

[0059] S31: Compare the first cyclic redundancy check code and the second cyclic redundancy check code bit by bit starting from the highest bit, and determine whether the values ​​of each bit of the first cyclic redundancy check code and the second cyclic redundancy check code are the same. Specifically, in the embodiment of the present invention, the first cyclic redundancy check code and the second cyclic redundancy check code are compared bit by bit starting from the highest bit, ensuring a comprehensive check of the entire check code. The cyclic redundancy check code is calculated by a specific algorithm on the data, and each bit contains relevant information of the data. By comprehensively comparing each bit of the check code, the data features carried by the check code can be fully utilized to verify the integrity of the data more comprehensively and reliably.

[0060] S32: If all bits of the first cyclic redundancy check code and the second cyclic redundancy check code are the same, then the first cyclic redundancy check code and the second cyclic redundancy check code are determined to be consistent, otherwise, they are inconsistent. Specifically, in the embodiment of the present invention, by comparing whether the first cyclic redundancy check code and the second cyclic redundancy check code are consistent, it can be detected whether an error occurs during data transmission or storage.

[0061] In some embodiments, after obtaining the first cyclic redundancy check code of the page data corresponding to each storage unit when the Flash memory is writing data, the data verification method further includes: obtaining the data length of the first cyclic redundancy check code of the page data corresponding to each storage unit when the Flash memory is writing data, increasing the programming cache of each storage unit of the Flash memory according to the data length of the obtained first cyclic redundancy check code; storing the data information of the first cyclic redundancy check code of the page data corresponding to each storage unit when the Flash memory is writing data into the increased programming cache of each storage unit. Specifically, in the embodiments of the present invention, the size of the programming cache is dynamically adjusted according to the data length of the first cyclic redundancy check code, so that the storage space can be used more effectively and the space waste or shortage caused by the fixed cache size can be avoided.

[0062] In some embodiments, before sending a write data command to the Flash memory, the data verification method further includes: sending an erase command to the Flash memory, and setting the cyclic redundancy check failure flag in the Flash memory to 0. Specifically, in an embodiment of the present invention, sending an erase command to the Flash memory can clear the residual data that may have existed in the storage unit. After multiple read and write operations, the Flash memory may have residual data or accumulated errors. The erase operation can ensure that the storage area is in a known, clean state before writing new data, avoiding interference of old erroneous data with the newly written data, thereby improving the accuracy and integrity of the newly written data.

[0063] In some embodiments, the data verification method further includes: if the data written to the Flash memory is erroneous, a rewrite data command is sent to the Flash memory; the Flash memory rewrites the data in each storage unit of the Flash memory according to the received rewrite data command. Specifically, in an embodiment of the present invention, when a write data error is detected, the system automatically sends a rewrite data command to the Flash memory, which provides an automatic error correction capability. During the data storage process, data write errors may occur due to factors such as hardware failures. Through the rewrite operation, these errors can be corrected to ensure that the data stored in the Flash memory is as accurate as possible, thereby improving the reliability of the data.

[0064] On the other hand, the present invention also provides a device for controlling memory access based on a CPU, please refer to Figure 4 , is a schematic diagram of a structure of a device for controlling memory access based on a CPU provided by an embodiment of the present invention, the device comprising:

[0065] The first acquisition module 41 is used to acquire the DMA controller and integrate the DMA controller into the CPU processor; the second acquisition module 42 is used to acquire the configuration information of the memory to be accessed, and classify the memory to be accessed according to the acquired configuration information of the memory to be accessed; the judgment module 43 is used to set the memory built-in self-test algorithm in the CPU processor integrated with the DMA controller, and judge whether the current state of the memory to be accessed enters the memory built-in self-test state through the first input and output pin of the CPU processor; the test module 44, if the current state of the memory to be accessed enters the memory built-in self-test state, the DMA controller performs data reading and writing and data verification tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor.

[0066] The device 40 for controlling memory access based on CPU provided in an embodiment of the present invention can execute the technical solution of the method for controlling memory access based on CPU in any of the above-mentioned embodiments, and its implementation principle and beneficial effects are similar to the implementation principle and beneficial effects of the method for controlling memory access based on CPU. Please refer to the implementation principle and beneficial effects of the device for controlling memory access based on CPU, which will not be repeated here.

[0067] Please refer to Figure 5, is a structural diagram of a computer device provided in an embodiment of the present invention, wherein the device includes a processor 501, which can be implemented by a general central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solution provided in the embodiment of the present application; a memory 502, which can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 502 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 502, and the processor 501 calls to execute the image compression method of the embodiment of the present application; the input / output interface 503 is used to realize information input and output; the communication interface 504 is used to realize the communication interaction between this device and other devices, and communication can be realized through wired methods (such as USB, network cables, etc.) or wireless methods (such as mobile networks, WIFI, Bluetooth, etc.); the bus 505 transmits information between the various components of the device (such as the processor 501, the memory 502, the input / output interface 503 and the communication interface 504); wherein the processor 501, the memory 502, the input / output interface 503 and the communication interface 504 realize communication connection with each other within the device through the bus 505.

[0068] Please refer to Figure 6 , which is a schematic diagram of the structure of a computer-readable storage medium in an embodiment of the present invention. The storage medium 60 in an embodiment of the present invention stores program instructions 61 that can implement the above-mentioned method of controlling memory access based on CPU, wherein the program instructions 61 can be stored in the above-mentioned storage medium in the form of a software product, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks or optical disks, or terminal devices such as computers, servers, mobile phones, and tablets.

[0069] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0070] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional units. The above is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present invention.

[0071] The above are only preferred embodiments of the present invention, and are not intended to limit the present invention in any form. Although the present invention has been disclosed as above in the form of preferred embodiments, it is not intended to limit the present invention. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A data verification method based on Flash memory, characterized in that: include: Sending a write data command to the Flash memory, and obtaining a first cyclic redundancy check code of page data corresponding to each storage unit when the Flash memory writes data; Calculate the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area based on the cyclic redundancy check algorithm; Determine whether the first cyclic redundancy check code of the page data corresponding to each storage unit is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area when writing data to the Flash; If the first cyclic redundancy check code of the page data corresponding to each storage unit when writing data to the Flash is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area, the data written to the Flash memory is correct, otherwise, the data written to the Flash memory is wrong.

2. The data verification method based on Flash memory according to claim 1, characterized in that: The method of calculating the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area based on the cyclic redundancy check algorithm includes: Determining a cyclic redundancy check algorithm for calculating a second cyclic redundancy check code based on the acquired first cyclic redundancy check code, and acquiring a corresponding generating polynomial according to the determined cyclic redundancy check algorithm; Obtaining page data corresponding to each storage unit in the Flash cache area, and initializing a cyclic redundancy check register according to a determined cyclic redundancy check algorithm; Based on the initialized cyclic redundancy check register, the page data corresponding to each storage unit in the Flash cache area is processed bit by bit to obtain a second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area.

3. The data verification method based on Flash memory according to claim 2, characterized in that: The bit-by-bit processing of the page data corresponding to each storage unit in the Flash cache area based on the initialized cyclic redundancy check register includes: S1, fetching the data bits of the page data corresponding to each storage unit in the Flash cache area bit by bit, and performing an XOR operation on the data bits of the page data corresponding to each storage unit in the Flash cache area fetched and the highest bit of the cyclic redundancy check register; S2, shifting the cyclic redundancy check register as a whole rightward by one bit, and storing the result of the XOR operation in the highest bit of the cyclic redundancy check register; S3, judging whether the highest bit of the shifted cyclic redundancy check register is 1, if the highest bit of the cyclic redundancy check register is 1, performing an XOR operation on the cyclic redundancy check register and the corresponding generating polynomial; S4. Repeat the above steps S1-S3 until all bits of the page data corresponding to each storage unit in the Flash cache area are processed.

4. The data verification method based on Flash memory according to claim 1, characterized in that: The determining whether the first cyclic redundancy check code of the page data corresponding to each storage unit when writing data to the Flash is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area includes: Compare the first cyclic redundancy check code and the second cyclic redundancy check code bit by bit starting from the highest bit, to determine whether the values ​​of each bit of the first cyclic redundancy check code and the second cyclic redundancy check code are the same; If all bits of the first cyclic redundancy check code and the second cyclic redundancy check code are the same, then it is determined that the first cyclic redundancy check code and the second cyclic redundancy check code are consistent, otherwise, they are inconsistent.

5. The data verification method based on Flash memory according to claim 1, characterized in that: After obtaining the first cyclic redundancy check code of the page data corresponding to each storage unit of the Flash memory when writing data, the data verification method further includes: Acquire the data length of the first cyclic redundancy check code of the page data corresponding to each storage unit of the Flash memory when writing data, and increase the programming cache of each storage unit of the Flash memory according to the acquired data length of the first cyclic redundancy check code; When the Flash memory is writing data, the data information of the first cyclic redundancy check code of the page data corresponding to each storage unit is stored in the increased programming cache of each storage unit.

6. The data verification method based on Flash memory according to claim 1, characterized in that: Before sending a write data command to the Flash memory, the data verification method further includes: Send an erase command to the Flash memory and set the cyclic redundancy check failure flag in the Flash memory to 0.

7. The data verification method based on Flash memory according to claim 1, characterized in that: The data verification method also includes: If the data written into the Flash memory is wrong, a data rewrite command is sent to the Flash memory; The Flash memory rewrites data in each storage unit of the Flash memory according to the received data rewriting command.

8. A data verification device based on Flash memory, characterized in that: The device comprises: An acquisition module, used for sending a write data command to the Flash memory, and acquiring a first cyclic redundancy check code of page data corresponding to each storage unit when the Flash memory writes data; A calculation module, used for calculating a second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area based on a cyclic redundancy check algorithm; A judgment module, judging whether a first cyclic redundancy check code of page data corresponding to each storage unit when writing data to the Flash is consistent with a second cyclic redundancy check code of page data corresponding to each storage unit in the Flash cache area; The verification module is configured to detect that if the first cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area is consistent with the second cyclic redundancy check code of the page data corresponding to each storage unit in the Flash cache area when the Flash writes data, the data written by the Flash memory is correct; otherwise, the data written by the Flash memory is wrong.

9. A computer device, characterized in that: The device includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; A processor, for implementing the steps of the Flash memory-based data verification method described in any one of claims 1 to 7 when executing a program stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the data verification method based on the Flash memory as described in any one of claims 1 to 7 are implemented.

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