A multi-channel flash memory array controller hardware system and method of implementing the same

Abstract

Aiming at the multi-channel storage array management problem faced by storage systems in high-performance computing, cloud storage and embedded systems, a multi-channel flash array controller hardware system and its implementation method are proposed. Through optimizing hardware design and management mechanism, the system uses parallel expansion DMA technology, multi-path logical channel design and optimized bus architecture to improve data transmission efficiency and improve resource allocation flexibility. Through the hardware-level management of command buffer and state processing mechanism, the invention solves the efficiency bottleneck of traditional storage array management scheme in large-scale data transmission, improves the overall performance and reliability of the system. The scheme can meet the demand of efficient and high-reliability storage array, especially suitable for large-scale data storage and processing scenarios.

Description

Technical Field

[0001] The present invention relates to a multi-channel flash memory array controller hardware system and an implementation method thereof, belonging to the technical field of high-speed storage. Background Art

[0002] Currently, with the rapid development of information technology and the popularization of big data applications, the requirements for storage systems in terms of capacity, speed and reliability are increasing. Especially in the fields of high-performance computing, cloud storage and embedded systems, how to efficiently manage multi-channel storage arrays has become a key issue in technological development. NAND flash memory is widely used in storage array systems due to its high storage density, low power consumption and high read and write speeds. However, due to the characteristics of NAND flash memory itself, such as limited erase and write times and low random write performance, traditional storage array management solutions face problems such as low efficiency and insufficient resource utilization when processing large-scale data transmission. In addition, the single-channel or low-bit-width DMA transmission method used in the existing technology, as well as the complexity of command and status entry management, lead to obvious performance bottlenecks when the system processes high-concurrency tasks, low bus utilization, and difficulty in meeting high-bandwidth and high-frequency storage requirements. Summary of the Invention

[0003] To address the above issues, the present invention proposes a multi-channel flash array controller hardware system and implementation method that addresses the shortcomings of the existing technology by optimizing hardware design and management mechanisms. Through parallel extended DMA technology, multi-path logical channel design, and an optimized bus architecture, data transmission efficiency is significantly improved, enhancing resource allocation flexibility. Furthermore, an efficient command buffer and status processing mechanism enable hardware-level management of command and status entries, helping to enhance overall system performance and reliability. This improvement meets the efficiency and reliability requirements of current storage array systems and provides a superior solution for large-scale data storage and processing.

[0004] The multi-channel flash array controller hardware system and its implementation method described in the present invention include a PCIE controller 1, a DMA controller 2, a message control unit 3, four flash array controllers 5 and an MCU 7.

[0005] For storage array management, the system is designed with four logical channels corresponding to NAC0 5-1, NAC1 5-2, NAC2 5-3, and NAC3 5-4. These channels correspond to NAC0's eight NAND Flash chips 6-1, NAC1's eight NAND Flash chips 6-2, NAC2's eight NAND Flash chips 6-3, and NAC3's eight NAND Flash chips 6-4. Each flash array has eight independent flash channels, labeled CH0 through CH7, operating in parallel. All channels in a flash array always perform the same operations unless one or more channels are blocked for certain operations. They receive the same control signals, but their block and page addresses can differ.

[0006] A DMA controller 2 is equipped to transfer data using DMA. By expanding the number of DMA controller channels and bit width, efficient matching with the flash memory configuration is achieved, thereby improving transfer rates. The DMA controller receives outbound read / write requests from on-chip DMA sources. It also receives inbound read / write requests from the PCE EP interface and converts them into read / write operations for on-chip memory or registers.

[0007] The message and control unit uses a 32-bit AHB data bus within the system as the transmission channel for core data and commands. This bus is responsible for connecting various functional modules and efficiently completing command distribution and processing, ensuring the consistency and stability of data flow.

[0008] The command buffer is a dual-port SRAM with a total of 96 command slots, a total size of 18KB, and each command slot can only accommodate one command entry. It also supports writing to the message unit and reading from the MCU.

[0009] The command buffer is used in a circular manner and implements management of the NAC command slot FIFO and the empty command FIFO to ensure efficient command processing and fast response. The command pool of NAC 0-3 is managed by two FIFOs: the free slot FIFO and the completion slot FIFO. Both are 12 levels deep to avoid overflow and ensure smooth command processing.

[0010] The array controller state processing method of the present invention comprises: the NAND array controller executes commands in a command pool, converts the commands into flash operations, notifies the DMAC to transmit data, and finally reports the state to the MCU.

[0011] Each physical channel integrates approximately 40KB of on-chip dual-port SRAM, which serves as a flash page buffer. Both ports are readable and writable. One port connects to the DMAC interface, operating at a 62.5MHz clock frequency. The other port connects to the NAC, NFI, and ECC. When contention occurs, priority is given, in descending order, to NFI, ECC, and NAC.

[0012] The CSI manages the exchange of command and status entries between the MCU and the NAC. It implements a 12-level command pool, written by the MCU and read by the NAC. The command queue specifies the exact order of command entries from the MCU, while the exchange of status entries is handled by the status FIFO. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a hardware system architecture diagram of a multi-channel flash array controller;

[0014] Figure 2 This is a diagram of the array controller and flash array structure;

[0015] Figure 3 It is the MCU command allocation flow chart;

[0016] Figure 4 It is the flow chart of command pool writing data;

[0017] Figure 5 It is a state frame combination flow chart; DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0019] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0021] Specific implementation method 1: Figures 1 to 5 Description of this embodiment

[0022] like Figure 1As shown in Figure 1, the controller in this system comprises a flash memory controller, RAM, and a PCIe and AHB bus architecture. This controller design supports multi-channel data transmission, using direct memory access (DMA) to efficiently move data. Parallel expansion of the DMA controller's bit width and number of channels allows it to accommodate existing flash memory configurations.

[0023] To manage the storage array, the system has designed four logical channels corresponding to NAC0 5-1, NAC1 5-2, NAC2 5-3, and NAC3 5-4. These channels correspond to NAC0's eight NAND Flash chips 6-1, NAC1's eight NAND Flash chips 6-2, NAC2's eight NAND Flash chips 6-3, and NAC3's eight NAND Flash chips 6-4. A DMA controller 2 is also included for data transfer.

[0024] The system architecture includes a PCIE controller 1 , a DMA controller 2 , a message control unit 3 , four flash array controllers 5 and an MCU 7 .

[0025] The system uses a 32-bit AHB bus as the primary data and command transmission channel, connecting various modules and implementing command distribution. In addition, the system is equipped with external DDR memory for use by the FPGA. For data transmission, the system utilizes a 256-bit bus with the same 78.125MHz frequency and adopts DMA for efficient data transfer.

[0026] Each flash array has eight independent flash channels, labeled CH0 to CH7, which operate in parallel. All channels of a flash array always perform the same operation unless one or more channels are masked for certain operations.

[0027] The host sends commands through the message unit and stores these commands in a dedicated command buffer. Figure 3 As shown, after receiving the command, the MCU distributes it to NAC 0-3 and stores the data in the registers and SRAM of the corresponding NAC as required.

[0028] The command buffer is designed with 96 command slots, totaling 18KB, and occupies all slots regardless of the actual command entry size. The buffer is built on a dual-port SRAM, supporting parallel writing of message units and simultaneous reading by CPU0. Because host commands may arrive continuously, the command buffer is managed in a circular manner and efficient scheduling is achieved through two FIFOs:

[0029] NAC command slot FIFO: The slot index where management commands are distributed to the NAC.

[0030] Empty command FIFO: maintains the index of free slots for subsequent commands.

[0031] Considering that there are four NACs in the system, four independent NAC command slot FIFOs are set.

[0032] The CSI manages the exchange of command and status entries between the MCU and the NAC. It implements a 12-level command pool, written by the MCU and read by the NAC. The command queue specifies the exact order of command entries from the MCU, while the exchange of status entries is handled by the status FIFO.

[0033] The main loop function monitors the hardware status and calls the dispatch function when a new command is detected, performing the following steps:

[0034] Pop CSI: New commands are written into the buffer by the message unit, and the firmware extracts the command information through the read interface of NAC 0-3, processing one request in the FIFO at a time.

[0035] Copy data: Determine the target slot for storing command data based on CSI information and write the data to the corresponding NAC command pool.

[0036] Distribution to NAC: Command data needs to be coordinated with the NAC hardware and firmware and then stored in registers and SRAM.

[0037] Release CSI: After command distribution is completed, the occupied slot is released, and the register of the empty command FIFO is written to mark the slot as idle.

[0038] Optimize command processing delay

[0039] To reduce MCU processing latency, the command dispatch process optimizes the handling of host address (HA) data. Each HA occupies 8 bytes, and each command can be associated with up to 14 HAs, requiring a total of 112 bytes. When transferring this data to the SRAM of NACs 0-3, the upper limit for a single transfer is 64 bytes, requiring multiple transfers.

[0040] To improve efficiency, a table lookup method was introduced. This method uses 14 tags (each 8 bytes) to pre-set the access table and combines it with the length parameter of the R2 register to achieve fast retrieval. Compared to traditional loop control, this method is more efficient when processing small data blocks (less than 112 bytes).

[0041] The NAC command pool consists of two parts: registers and SRAM:

[0042] Register section: stores the main parameters of the command entry (excluding HA0-HA14 and OOBA).

[0043] SRAM part: stores HA0-HA14 and OOBA data.

[0044] The command pool is managed by free slot FIFO and completion slot FIFO, both of which are 12 levels deep to ensure no overflow risk in high concurrency situations.

[0045] Ultimately, the collaborative design of the command buffer, FIFO mechanism, and command pool ensures efficient command distribution and stable system operation.

[0046] like Figure 4 As shown, when using the NAC 0-3 command pool, the firmware first steps in command processing to identify the currently available command slot. By querying the NAC's empty command slot FIFO and reading a specified register, the firmware obtains the command slot index, thereby determining the storage location of the new command data. After completing the data copy, the firmware signals the NAC through a specific register, indicating that it is ready to execute the command. Each time this register is written, the corresponding slot is locked by the FIFO, ensuring smooth command execution. After command execution is complete, the firmware writes the slot index to the completed command pool index register, thereby unlocking the slot.

[0047] The NAC firmware operates in the reverse order: first, the CPI (command slot index) is popped from the completion slot FIFO, and then the corresponding command is processed. After the command is executed, the CPI is written to the empty slot FIFO to release the relevant command slot, freeing up resources for subsequent command processing.

[0048] Return status processing such as Figure 5 As shown in the figure, after executing a command, the NAC generates corresponding status information, each of which occupies 8 bytes. This information is first transmitted to the MCU, which then sends it to the host via DMA. To implement this process, the NAC, MCU, and host all require dedicated storage space for managing status entries.

[0049] The MCU contains a 1KB internal status buffer that can hold up to 128 status entries. This buffer utilizes a dual-port SRAM design, allowing CPU0 writes and DMAC reads to proceed concurrently. The MCU firmware ensures that the buffer efficiently stores status information in a circular manner, avoiding wasted space.

[0050] The host also has a state buffer in memory, typically located in DRAM with sufficient capacity to prevent overflow. This buffer is also managed in a circular manner to receive and store state entries.

[0051] The MCU firmware extracts status entries from the NAC status FIFO and stores them in the MCU's status buffer. Each time data is read from the NAC status FIFO, a new status entry is popped out. When the accumulated number of status entries reaches a preset value, the firmware begins preparing for status frame transmission.

[0052] Status frames are variable in length and utilize a request FIFO mechanism for efficient management. A 1KB buffer can hold up to 128 status frames, eliminating the need to store offset addresses in the FIFO. By controlling the FIFO head pointer and counter, the status FIFO can be recycled, optimizing storage resource utilization and preventing buffer overflows.

[0053] After the status entries are extracted through the read port register of the NAC, they are stored in the MCU buffer and assembled into status frames for further transmission to the host.

[0054] Status DMA control: Status frames are transferred to the host via DMA. When initiating a DMA transfer, three key parameters are required: frame address, frame length, and host status buffer index (HSBI). These parameters are written to the write port register of the status frame request FIFO to trigger the DMA transfer operation.

[0055] When the DMA transfer is complete, the DMA operation status can be checked by reading the read port register of the status frame completion FIFO. If no error occurs, the request FIFO is popped to release the corresponding resources.

[0056] During a FIFO push operation, the counter increments by 1. When the frame parameters are written to the DMA register and the DMA transfer is initiated, the frame length is pushed to the end of the array. To prevent the status buffer from overflowing, the system dynamically calculates the available space in the 1KB buffer by subtracting the frame length. The maximum value of the FIFO counter is 128, ensuring stable buffer management.

[0057] During a FIFO pop operation, the head pointer moves to the next position and the counter decrements by 1. When the DMA transfer is complete, the system pops the stored frame length from the array and recalculates the number of bytes available in the buffer. If the head pointer reaches its maximum value of 128, a pop operation returns the head pointer to the beginning, allowing for circular use of the FIFO.

[0058] After the status entry is sent to the host, the MCU generates an interrupt signal to notify the host CPU by writing 0x80000000 to the Message Signaled Interrupt (MSI) control and status register. There are two merge processing strategies for triggering this interrupt signal:

[0059] Triggered when the number of status entries reaches the count threshold set by the register;

[0060] Triggered when the time since the latest status entry was added to the status FIFO exceeds the time threshold set by the register.

[0061] The DMA controller handles various transfer types, including inbound and outbound memory read and write requests and the processing of completion packets.

[0062] First, inbound memory read requests target PCIE memory-mapped registers. These requests are converted by the DMAC into completion requests and sent to the DMAC's internal arbiter. The DMAC TX logic reads the register data via the DMAC read bus, then encapsulates it in a PCIE completion packet with the data and ultimately sends it to the PCIE EP interface. Inbound memory write requests target memory-mapped registers directly, and the DMAC writes the data directly to the target register via the DMAC write bus.

[0063] For inbound completion packets with data packets, which are responses from the host to outbound memory read requests, the completion packets must match the pending request or they will be discarded. The destinations of these packets can be NAC0 to NAC3 and the MSG unit command frame FIFO. The DMAC writes data to these destination locations directly through the DMAC write bus.

[0064] Outbound memory write requests are sent to the DMAC by NAC0 through NAC3 and the MSG unit. Each request can process up to 4KB of data and is called a source memory write request. The DMAC reads the data sent by the requester via the DMAC read bus, packages it into one or more PCIE memory write request packets based on the PCIE maximum payload size, and sends these packets to the PCIE EP interface. After the transfer is complete, the DMAC returns the status to the requester.

[0065] Similarly, NAC0 to NAC3 and the MSG unit can also send outbound memory read requests to the DMAC. These requests are called source memory read requests. The DMAC packages these source requests into PCIE memory read request packets, sends them to the PCIE EP interface, and eventually returns the request status to the requester. The DMAC also manages the number of memory read request packets to avoid PCIE receive buffer overflow. Each pending memory read request starts a timer.

[0066] Finally, after receiving the completion data packet, DMAC will write the returned data to the requester through the DMAC write bus. Since the host may split a read request into multiple completion data packets, DMAC will return the completion status to the requester only after all data requested by the source are completed.

[0067] The DMAC is responsible for handling various types of transmissions, including inbound and outbound memory read and write requests and completing data packet processing. Its specific operations are as follows:

[0068] Inbound memory read requests: Inbound memory read requests target PCIE memory-mapped registers. The DMAC converts these requests into completion requests and sends them to the DMAC's internal arbiter. The DMAC TX logic then reads the register data via the DMAC read bus, encapsulates it into a PCIE completion packet containing the data, and ultimately sends it to the PCIE EP interface.

[0069] Inbound memory write requests: Inbound memory write requests are directly targeted at PCIE memory-mapped registers. The DMAC writes the data directly to the target register via the DMAC write bus without requiring additional encapsulation.

[0070] Inbound Completion Packets: Inbound Completion Packets are the host's response data to outbound memory read requests. These Completion Packets must match a pending memory read request; otherwise, they are discarded. The destination may be the command frame FIFO of NAC0 through NAC3 or the MSG unit. The DMAC writes the data to the specified location via the DMAC write bus.

[0071] Outbound memory write requests: These are issued by NAC0 to NAC3 or the MSG unit. Each request processes a maximum of 4KB of data and is referred to as a source memory write request. The DMAC reads the requester's data via the DMAC read bus and packages it into one or more PCIE memory write request packets, based on the PCIE maximum payload size, for transmission to the PCIE EP interface. Upon completion of the transmission, the DMAC returns the transmission status to the requester.

[0072] Outbound Memory Read Requests: NAC0 through NAC3 or MSG units can also issue source memory read requests. The DMAC encapsulates these requests into PCIE memory read request packets and sends them to the PCIE EP interface. The DMAC manages the number of pending memory read requests to prevent overflow of the PCIE receive buffer. Each pending memory read request also starts a timer to ensure timely completion.

[0073] Completion Packet Processing: When the DMAC receives a completion packet, it writes the data to the requester via the DMAC write bus. If the host splits a read request into multiple completion packets, the DMAC waits for all packets to be transmitted before returning a complete completion status to the requester, ensuring data consistency and integrity.

[0074] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A multi-channel flash array controller hardware system, characterized in that: The hardware structure of the array controller includes: a. It integrates a flash memory controller, random access memory (RAM), PCI Express, and advanced high-performance bus (AHB) architecture, supporting multi-channel parallel data transmission. The flash array controller converts formatting commands from the host into flash operations, then sends / receives data to the host and finally reports status to the host. It includes four flash arrays connected to the flash array controller, each with eight flash channels. b. The message and control unit performs the transmission of command entries and status entries, temperature detection, non-volatile memory (NVM) management, and exception handling. The NAND array controller (NAC) converts the command received from the message and control unit into a flash operation, executes the operation, sends a request to the direct memory access controller (DMAC), and returns the status to the message and control unit. c. Data transfer uses direct memory access (DMA) technology. By expanding the number of DMA controller channels and bit width, it can effectively match the flash memory configuration, thereby improving the transfer rate. The DMA controller receives outbound read / write requests from the on-chip DMA source and inbound read / write requests from the PCE EP interface, and converts them into read / write operations for on-chip memory or registers. d. During the transfer of command items and status items, the command buffer is a dual-port static random access memory (SRAM) with a total design of 96 command slots, totaling 18KB. Each command slot can only accommodate one command entry, supporting both writing to the message unit and reading from the microcontroller unit (MCU). The command buffer is used in a circular manner and implements management of the NAC command slot first-in, first-out queue (FIFO) and the empty command FIFO to ensure efficient command processing and fast response. The command pool of NAC 0-3 is managed by two FIFOs: the free slot FIFO and the completion slot FIFO. Both are 12 levels deep to avoid overflow and ensure smooth command processing.

2. The message and control unit according to claim 1, characterized in that The message and control unit uses a 32-bit wide AHB data bus within the system as the transmission channel for core data and commands. The bus is responsible for connecting various functional modules and efficiently completing the distribution and processing of commands to ensure the continuity and stability of data flow.

3. The flash memory array according to claim 1, wherein: Each flash array has 8 independent flash channels, labeled CH0 to CH7, which work in parallel. All channels of a flash array always perform the same operation unless one or more channels are masked by certain operations. The control signals they receive are the same, but their block and page addresses can be different.

4. The array controller status processing method in a system according to any one of claims 1, 2 and 3, characterized in that: The following steps are involved: a. The NAND array controller executes commands from the command pool, converts them into flash operations, notifies the DMAC to transfer data, and finally reports the status to the MCU; b. 40KB of on-chip dual-port SRAM is integrated on each physical channel and used as a flash page buffer. Both ports can be read and written. One port is connected to the DMAC interface with a clock frequency of 62.5MHz, and the other port is connected to the NAC, NAND Flash Interface (NFI), and Error Checking and Correction (ECC). When contention occurs, the priority is NFI, ECC, and NAC in descending order. c. The Command / Status Interface (CSI) manages the exchange of command and status table entries between the MCU and the NAC. It implements a 12-level command pool, which is written by the MCU and read by the NAC. The command queue is used to specify the exact order of command entries from the MCU. The exchange of status entries is completed by the status FIFO.

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