A PCIe retimer, a PCIe system, and an electronic device

Abstract

The present invention provides a PCIe retimer, a PCIe system and an electronic device. The decoding and descrambling module decodes and descrambles the output bitstream of the upstream device and outputs it backward. When the low-latency trigger condition is met, the control module modifies the second type of bitstream in the decoded and descrambled bitstream into the first type of bitstream and outputs it backward. The de-skew module performs de-skewing processing on the received bitstream and outputs it backward; the encoding and scrambling module performs encoding and scrambling processing on the received bitstream and outputs the encoded and scrambled bitstream backward; after the control module determines that the low-latency path is aligned with the main path, it controls the low-latency path to be the current working path. The state machine of the downstream device will not perform state transitions due to receiving a preset number of the second type of bitstreams, so that the state transition times of the upstream device and the downstream device can be delayed, achieving the purpose of delaying the state machine, and enabling the PCIe retimer to have more time for path switching without generating bit errors.

Description

Technical Field

[0001] The present invention relates to the field of chips, and more particularly, to a PCIe retimer, a PCIe system, and an electronic device. Background Art

[0002] After PCIe 4.0, the retimer specification was proposed, and the retimer specification can solve signal integrity problems and transmission distance problems in the link. The retimer can also ensure that data does not have errors during high-speed transmission, and the retimer can participate in the management of the PCIe link and other functions.

[0003] Adding a retimer in the PCIe system, although bringing the above advantages, also has some drawbacks: for example, the retimer will increase the system delay during the processes of retiming signals, data de-scrambling, data encoding / decoding, and equalization. In some specific scenarios, it is necessary to switch the link to a low-latency path, and how to ensure the smooth completion of the switching process has become a difficult problem that those skilled in the art are concerned about. Summary of the Invention

[0004] The purpose of the present invention is to provide a PCIe retimer, a PCIe system, and an electronic device to improve the above problems.

[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides a PCIe retimer, and the PCIe retimer includes: a de-skew module, a control module, a decoding and de-scrambling module, an encoding and scrambling module, and a low-latency path;

[0007] The input end of the decoding and de-scrambling module and the input end of the low-latency path are used to connect to the output end of the upstream device, the output end of the decoding and de-scrambling module, the input end of the de-skew module, and the control end of the low-latency path are connected to the control module, the output end of the de-skew module is connected to the encoding and scrambling module, and the output end of the encoding and scrambling module and the output end of the low-latency path are used to connect to the downstream device;

[0008] The decoding and de-scrambling module is used to perform decoding and de-scrambling processing on the output bit stream of the upstream device and output the decoded and de-scrambled bit stream to the control module;

[0009] The control module is used to determine whether the low-latency trigger condition is met according to the decoded and de-scrambled bit stream. If it is met, the second type of bit stream in the decoded and de-scrambled bit stream is modified to the first type of bit stream, and the modified bit stream is transmitted to the de-skew module. The second type of bit stream is the trigger bit stream for the downstream device to perform a state transition;

[0010] The skew removal module is used to perform skew removal processing on the received bitstream and transmit the skew-removed bitstream to the encoding and scrambling module;

[0011] The encoding and scrambling module is used to perform encoding and scrambling processing on the received bitstream and transmit the encoded and scrambled bitstream to the downstream device;

[0012] The control module is further configured to control the low-latency path as the current working path after determining that the low-latency path is aligned with the main path, where the main path is the path passing through the skew removal module.

[0013] The PCIe retimer can modify the second type of bitstream in the decoded and descrambled bitstream into the first type of bitstream, and the state machine of the downstream device will not perform state transitions due to receiving a preset number of the second type of bitstreams, thereby delaying the time for the state machines of the upstream device and the downstream device to jump from the receive-side configuration recovery state to the idle state (Recovery.Idle), achieving the purpose of delaying the state machine and enabling the PCIe retimer to have more time for path switching without bit errors.

[0014] Optionally, the control module includes a main control unit and a path switching module. The output end of the decoding and descrambling module and the input end of the skew removal module are connected to the main control unit. The low-latency path control end is connected to the path switching module, and the path switching module is connected to the main control unit;

[0015] The main control unit is configured to determine that the low-latency trigger condition is met when both the downstream device and the upstream device are in the receive-side configuration recovery state, the rate of the output bitstream of the upstream device is greater than a preset rate threshold, and a bitstream that meets the second type of bitstream determination condition is received;

[0016] Wherein, the second type of bitstream determination condition includes that the target symbol corresponding to the bitstream matches its corresponding target content;

[0017] The main control unit is configured to modify the second type of bitstream in the decoded and descrambled bitstream into the first type of bitstream and transmit the modified bitstream to the skew removal module when the low-latency trigger condition is met;

[0018] The path switching module is configured to control the low-latency path as the current working path after determining that the low-latency path is aligned with the main path and send a stop modification instruction to the main control unit to cause the main control unit to stop modifying the decoded and descrambled bitstream.

[0019] Through the above-mentioned second type of bitstream judgment condition, it is possible to accurately identify whether the low-latency trigger condition is met, so that the decoded and descrambled bitstream can be modified immediately, achieving the purpose of holding the state machine, and enabling the PCIe retimer to have more time for path switching without bit errors.

[0020] Optionally, the master control unit is further configured to determine that an abnormal signal is received when the abnormal monitoring symbol corresponding to the received bitstream does not match its corresponding target content;

[0021] The master control unit is further configured to send an exit instruction to the path switching module when an abnormal signal is received, so that the path switching module stops determining whether the low-latency path is aligned with the main path;

[0022] The master control unit is further configured to stop modifying the decoded and descrambled bitstream when an abnormal signal is received, or keep modifying the decoded and descrambled bitstream, and stop modifying the decoded and descrambled bitstream after a preset time length.

[0023] The master control unit is further configured to determine that an abnormal signal is received when it monitors that the rate of the output bitstream of the upstream device is less than a preset rate threshold;

[0024] The master control unit is further configured to determine that an abnormal signal is received when it monitors that the state machine of the upstream device or the state machine of the downstream device meets the state transition condition;

[0025] The state transition condition is the condition for the state machine to jump from the receive-end configuration recovery state to the abnormal state, or the state transition condition is for the state machine to jump from the idle state to the loopback state, the prohibited state, or the thermal reset state.

[0026] By monitoring the abnormal conditions of the device operation, in the case of receiving an abnormal signal, the low-latency mode is exited to avoid system crashes.

[0027] Optionally, the decoding and descrambling module is configured to provide a storage start signal to the master control unit when detecting the dock feature of the decoded and descrambled bitstream;

[0028] The decoding and descrambling module is configured to provide a high-level valid flag signal to the master control unit when detecting that the decoded and descrambled bitstream is valid data;

[0029] The master control unit is configured to determine whether the category identification symbol of the received bitstream matches its corresponding target content after receiving the storage start signal and when the valid flag signal is in the high-level state. If it matches, it determines that the current bitstream is the first type of bitstream and stores the current bitstream;

[0030] The master control unit is used to replace the second type of bitstream in the decoded and descrambled bitstream with the latest stored first type of bitstream, so as to complete the modification of the decoded and descrambled bitstream.

[0031] By replacing the second type of bitstream in the decoded and descrambled bitstream with the latest stored first type of bitstream, the problem of scrambled codes can be avoided.

[0032] Optionally, the path switching module is used to monitor the output bitstream of the de-skewing module in the main path. When the number of electrical idle exit sequences (EIE) output by the de-skewing module is greater than the monitoring threshold, it is determined that the low-latency path is aligned with the main path.

[0033] By accurately determining whether the low-latency path 15 is aligned with the main path, the timeliness of link switching can be ensured.

[0034] In a second aspect, an embodiment of the present invention provides a PCIe system, which includes an upstream device, a downstream device, and the above-mentioned PCIe retimer.

[0035] In a third aspect, an embodiment of the present invention provides an electronic device, which includes the above-mentioned PCIe system.

[0036] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, provides detailed descriptions as follows. Description of the Drawings

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0038] Figure 1 It is a schematic structural diagram of the PCIe retimer provided by the embodiment of the present invention.

[0039] Figure 2 It is a schematic structural diagram of the control module provided by the embodiment of the present invention.

[0040] Figure 3 It is a signal timing diagram provided by the embodiment of the present invention.

[0041] In the figure: 11 - decoded and descrambled module; 12 - control module; 13 - de-skewing module; 14 - encoding and scrambling module; 15 - low-latency path; 20 - upstream device; 30 - downstream device; 121 - master control unit; 122 - path switching module. Detailed Embodiments

[0042] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

[0043] Therefore, the detailed description of the embodiments of the present invention provided in the drawings below is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0044] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0045] Moreover, the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device.

[0046] The following will describe in detail some embodiments of the present invention with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0047] The embodiments of the present invention provide a PCIe retimer. The PCIe retimer can control the state machines of the upstream device and the downstream device to enter the hover state, and can delay the time for the state machines of the upstream device and the downstream device to jump from the receive-side configuration recovery state to the idle state (Recovery.Idle). The PCIe retimer can modify the second type of code stream (TS2 code stream) in the decoded and descrambled code stream to the first type of code stream (TS1 code stream), avoiding state jumps of the downstream device when receiving 8 second type of code streams (TS2 code streams), thereby achieving the purpose of delaying the state machine. This enables the PCIe retimer to have more time for path switching without generating bit errors.

[0048] It should be noted that when the upstream device of the PCIe retimer is a root complex (RC for short), the downstream device of the PCIe retimer is an endpoint device (EP for short); when the upstream device of the PCIe retimer is an endpoint device, the downstream device of the PCIe retimer is a root complex.

[0049] For the specific structure of the PCIe retimer, an alternative implementation manner is provided in an embodiment of the present invention. Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of the PCIe retimer provided in an embodiment of the present invention.

[0050] The PCIe retimer includes: a deskew module 13, a control module 12, a decoding and descrambling module 11, an encoding and scrambling module 14, and a low-latency path 15.

[0051] The input end of the decoding and descrambling module 11 and the input end of the low-latency path 15 are used to connect to the output end of the upstream device 20. The output end of the decoding and descrambling module 11, the input end of the deskew module 13, and the control end of the low-latency path 15 are connected to the control module 12. The output end of the deskew module 13 is connected to the encoding and scrambling module 14. The output end of the encoding and scrambling module 14 and the output end of the low-latency path 15 are used to connect to the downstream device 30.

[0052] The decoding and descrambling module 11 is used to perform decoding and descrambling processing on the output bitstream of the upstream device 20, and output the decoded and descrambled bitstream to the control module 12.

[0053] The control module 12 is used to determine whether the low-latency trigger condition is met according to the decoded and descrambled bitstream. If it is met, the second type of bitstream (TS2 bitstream) in the decoded and descrambled bitstream is modified to the first type of bitstream (TS1 bitstream), and the modified bitstream is transmitted to the deskew module 13. The second type of bitstream is the trigger bitstream for the state transition of the downstream device 30.

[0054] Among them, when the downstream device 30 receives a preset number of the second type of bitstreams, it will jump from the current state (receive-side configuration recovery state) corresponding to the low-latency trigger condition to the next state, and the next state is the idle state (Recovery.Idle).

[0055] The deskew module 13 is used to perform deskewing processing on the received bitstream, and transmit the deskewed bitstream to the encoding and scrambling module 14.

[0056] The encoding and scrambling module 14 is used to perform encoding and scrambling processing on the received bitstream, and transmit the encoded and scrambled bitstream to the downstream device 30.

[0057] The control module 12 is further configured to control the low-latency path 15 as the current working path after determining that the low-latency path 15 is aligned with the main path, where the main path is the path passing through the deskew module 13.

[0058] Optionally, the main path is the path passing through the decode and descramble module 11, the control module 12, the deskew module 13, and the encode and scramble module 14. It should be noted that the low-latency path 15 does not require decode and descramble processing, deskew processing, and encode and scramble out-of-library. The latency of the low-latency path 15 is lower than that of the main path. The low-latency path 15 can be a direct link.

[0059] In the PCIe retimer provided in the embodiment of the present invention, the second type of code stream (TS2 code stream) in the decoded and descrambled code stream can be modified into the first type of code stream (TS1 code stream). The state machine of the downstream device will not perform state transitions due to receiving a preset number of the second type of code streams. Thus, the time for the state machines of the upstream device and the downstream device to jump from the receive-side configuration recovery state to the idle state (Recovery.Idle) can be delayed, achieving the purpose of delaying the state machine, so that the PCIe retimer has more time for path switching without generating bit errors.

[0060] Optionally, after the low-latency path 15 is aligned with the main path, the control module 12 stops modifying the decoded and descrambled code stream.

[0061] On the Figure 1 basis, the embodiment of the present invention also provides an optional implementation manner for the specific structure of the control module. Please refer to Figure 2 Figure 2 which is the schematic structural diagram of the control module provided in the embodiment of the present invention.

[0062] The control module 12 includes a main control unit 121 and a path switching module 122. The output end of the decode and descramble module 11 and the input end of the deskew module 13 are connected to the main control unit 121. The control end of the low-latency path 15 is connected to the path switching module 122, and the path switching module 122 is connected to the main control unit 121.

[0063] The main control unit 121 is configured to determine that the low-latency trigger condition is met when both the downstream device 30 and the upstream device 20 are in the receive-side configuration recovery state (also referred to as Recovery.RcvrCfg), the rate of the output code stream of the upstream device 20 is greater than a preset rate threshold, and a code stream that meets the second type of code stream determination condition is received.

[0064] Wherein, the second type of code stream determination condition includes that the target symbol corresponding to the code stream matches its corresponding target content.

[0065] ​Optionally, the bitstream includes 16 symbols. The target symbols can be the speed_change field segment of symbol0, symbol4, symbol7, and the hot-reset / disable field segment of symbol5. The target content corresponding to symbol0 is 8’h2d, the target content corresponding to the speed_change field segment of symbol4 is 0: the speed_change field segment is 0, the target content corresponding to Symbol7 is 8’h45, and the target content corresponding to the hot-reset / disable field segment is 0.

[0066] Optionally, the rate threshold can be configured through a register module (not shown in the figure). By adjusting the rate threshold, it is possible to support entering the low-latency mode at different rates of the output bitstream.

[0067] After the PCIe retimer is powered on, when the rate of the output bitstream of the upstream device 20 is less than or equal to the preset rate threshold, since the low-latency trigger condition is not met, the main control unit 121 will be in the idle state (L1_Idle) and will not perform any processing on the received bitstream, but directly forward the bitstream to the de-skew module 13 at the back end.

[0068] In an alternative embodiment, the rate of the output bitstream of the upstream device 20 can be gen1, gen2, gen3, gen4, and gen5, and gen1, gen2, gen3, gen4, and gen5 increase in sequence. The rate threshold can be, but is not limited to, set to gen2.

[0069] The main control unit 121 is configured to modify the second type of bitstream (TS2 bitstream) in the decoded and de-scrambled bitstream to the first type of bitstream (TS1 bitstream) when the low-latency trigger condition is met, and transmit the modified bitstream to the de-skew module 13.

[0070] It should be noted that the PCIe retimer may have multiple main paths. One main path corresponds to one data path, and the direction of the data path may be different. Each data path independently modifies the bitstream. Moreover, when modifying the decoded and de-scrambled bitstream of a certain main path, only the second type of bitstream (TS2 bitstream) is modified, and other bitstreams (such as SKP bitstream, EIEOS bitstream, and EIOS bitstream, etc.) are not modified. Modifying the bitstream can be done seamlessly and cannot damage any bit and any compliant data (symbol data) in any bitstream.

[0071] The path switching module 122 is used to control the low-latency path 15 as the current working path after determining that the low-latency path 15 is aligned with the main path, and send a stop modification instruction to the main control unit 121, so that the main control unit 121 stops modifying the decoded and descrambled bitstream.

[0072] Through the above-mentioned second type of bitstream judgment condition, it is possible to accurately identify whether the low-latency trigger condition is met, so as to immediately modify the decoded and descrambled bitstream, achieve the purpose of holding the state machine, and enable the PCIe retimer to have more time for path switching without bit errors.

[0073] On the Figure 2 basis, regarding how to handle abnormal situations during device operation and avoid system crashes, the embodiment of the present invention also provides an optional implementation manner. Please refer to the following text.

[0074] The main control unit 121 is also used to determine that an abnormal signal is received when the abnormal monitoring symbol corresponding to the received bitstream does not match its corresponding target content.

[0075] Optionally, the abnormal monitoring symbol can be the speed_change field segment of symbol4 and symbol7. The target content corresponding to the speed_change field segment of symbol4 is 0: the speed_change field segment is 0, and the target content corresponding to Symbol7 is 8’h45.

[0076] When the target content corresponding to the speed_change field segment of symbol4 is 1, it means that the PCIe system may need to switch speeds, so it is necessary to exit the low-latency mode; when the target content corresponding to Symbol7 is not 8’h45, it means that the PCIe system may re-perform equalization (abbreviation: EQ), so it is necessary to exit the low-latency mode.

[0077] The main control unit 121 is also used to send an exit instruction to the path switching module 122 when an abnormal signal is received, so that the path switching module 122 stops judging whether the low-latency path 15 is aligned with the main path.

[0078] The main control unit 121 is also used to stop modifying the decoded and descrambled bitstream when an abnormal signal is received, or keep modifying the decoded and descrambled bitstream, and stop modifying the decoded and descrambled bitstream after a preset time length. Flexibly wait for both ends of the device to time out and enter the abnormal state (Exit to Detect), so that the situation where the entire system cannot re-establish a link due to rate mismatch caused by an abnormality will not occur.

[0079] The master control unit 121 is further configured to determine that an abnormal signal is received when it monitors that the rate of the output bitstream of the upstream device 20 is less than a preset rate threshold.

[0080] The master control unit 121 is further configured to determine that an abnormal signal is received when it monitors that the state machine of the upstream device 20 or the state machine of the downstream device 30 meets the state transition condition.

[0081] The state transition condition is the condition for the state machine to jump from the receiver configuration recovery state to the abnormal state (Exit to Detect), indicating that the current PCIe system needs to restart link establishment. Or, the state transition condition is that the state machine jumps from the idle state (Recovery.Idle) to the loopback state (Exit to Loopback), the disabled state (Exit to Disable), or the hot reset state (Exit to Hot Reset), indicating that the current PCIe system needs to enter some test modes, so it also needs to exit the low-latency mode.

[0082] In an optional implementation manner, when the low-latency trigger condition is satisfied, the master control unit 121 can pull up the datapath_modify_enh signal, so that the master control unit 121 jumps to the L1_NORMAL_MODIF state, indicating that it enters the low-latency mode and modifies the decoded and descrambled bitstream, that is, modifies the second type of bitstream (TS2 bitstream) in the decoded and descrambled bitstream to the first type of bitstream (TS1 bitstream).

[0083] After the master control unit 121 jumps to the L1_NORMAL_MODIF state, the master control unit 121 starts to monitor whether an abnormal signal is received. If the master control unit 121 receives an abnormal signal, the master control unit 121 jumps to the NO_L2_STOP_MODIF state. At this time, the master control unit 121 continues to modify the decoded and descrambled bitstream. After a preset time length, it stops modifying the decoded and descrambled bitstream, and the master control unit 121 jumps to the exit state (L1_EXIT), indicating that it exits the low-latency mode.

[0084] In an alternative embodiment, after the path switching module 122 determines that the low-latency path 15 is aligned with the main path, the stop modification instruction sent to the main control unit 121 is a continuous high-level signal. When the main control unit 121 detects the rising edge of the stop modification instruction pair, the main control unit 121 jumps to the L2_STOP_MODIF state. At this time, the modification of the decoded and descrambled stream is stopped, but the main control unit 121 still monitors the abnormal signal. If the main control unit 121 receives an abnormal signal before detecting the falling edge of the stop modification instruction pair, the main control unit 121 jumps to the L2_UNOR_MODIF state, resumes modifying the decoded and descrambled stream, and after a preset time length, stops modifying the decoded and descrambled stream, and the main control unit 121 jumps to the exit state (L1_EXIT).

[0085] When the main control unit 121 is in the exit state (L1_EXIT), if both the downstream device 30 and the upstream device 20 are in the receiving-end configuration recovery state, and the rate of the output stream of the upstream device 20 is greater than the preset rate threshold, and a stream that meets the second type of stream judgment condition is received, it is determined that the low-latency trigger condition is met, and the main control unit 121 jumps back to the L1_NORMAL_MODIF state again.

[0086] In an alternative embodiment, the preset time length can be configured through the register module.

[0087] On the basis of the foregoing, regarding how to modify the decoded and descrambled stream, the embodiment of the present invention further provides an alternative embodiment to replace the second type of stream (TS2 stream) in the decoded and descrambled stream with the latest stored first type of stream (TS1 stream), so as to avoid the problem of scrambled codes. For details, please refer to the following text.

[0088] The decoding and descrambling module 11 is used to provide a storage start signal (k_start_block) to the main control unit 121 when detecting the dock feature of the decoded and descrambled stream.

[0089] The decoding and descrambling module 11 is used to provide a high-level valid flag signal (k_valid) to the main control unit 121 when detecting that the decoded and descrambled stream is valid data.

[0090] The main control unit 121 is used to determine whether the class identification symbol of the received stream matches its corresponding target content after receiving the storage start signal and when the valid flag signal is in the high-level state. If it matches, it is determined that the current stream is the first type of stream (TS1 stream), and the current stream is stored.

[0091] Among them, the category identification symbol can be symbol0, and the target content corresponding to symbol0 is 8’h1e. When the two match, it indicates that the recognized bitstream is the first type of bitstream (TS1 bitstream).

[0092] In an alternative embodiment, the main control unit 121 will store the current bitstream only when the rate of the output bitstream of the upstream device 20 is greater than a preset rate threshold.

[0093] The main control unit 121 is used to replace the second type of bitstream (TS2 bitstream) in the decoded and descrambled bitstream with the latest stored first type of bitstream (TS1 bitstream) to complete the modification of the decoded and descrambled bitstream.

[0094] Please refer to Figure 3 , Figure 3 , which is the signal timing diagram provided by the embodiment of the present invention. Since the PIPE interface of the PCIe retimer uses 4 symbols for transmission, it takes four beats (cycles) to store 1 complete first type of bitstream (TS1 bitstream). When the rate (gen3 / 4 / 5) of the output bitstream of the upstream device 20 is greater than the preset rate threshold, the upstream device 20 adopts the 128b / 130b encoding method. Therefore, during the normal data transmission process, the sync header will be compensated. So the main control unit 121 will store the current bitstream only when the valid flag signal (k_valid) is pulled high and valid. The start storage timing is when the storage start signal (k_start_block) is pulled high, the valid flag signal (k_valid) is at a high level, and the category identification symbol matches its corresponding target content, and then the storage is performed. That is, the first type of bitstream during the T period in the figure is stored.

[0095] Based on the above, regarding how to accurately determine whether the low-latency path 15 is aligned with the main path to ensure the timeliness of link switching, the embodiment of the present invention also provides an alternative embodiment. Please refer to the following text.

[0096] The path switching module 122 is used to monitor the output bitstream of the de-skew module 13 in the main path. When the number of electrical idle exit sequences (EIE) output by the de-skew module 13 is greater than the monitoring threshold, it is determined that the low-latency path 15 is aligned with the main path.

[0097] Regarding how to further monitor the operating status of the PCIe system, ensure the accuracy of the system operation, and ensure the operation effect, the embodiment of the present invention also provides an alternative embodiment. Please refer to the following text.

[0098] The main control unit 121 is further configured to count the number of times the main path enters or exits the low-latency mode. The number data includes the entry count of entering the low-latency mode and the exit count of exiting the low-latency mode.

[0099] The main control unit 121 is further configured to compare the number data of the main path with the number data of the opposite path corresponding to the main path to determine whether there is an abnormality in the operation.

[0100] Optionally, the upstream device of the main path is the downstream device of the opposite path, and the downstream device of the main path is the upstream device of the opposite path.

[0101] In an alternative embodiment, the low-latency enable signal can be configured through the register module. When the low-latency enable signal is not configured, the control module 12 only forwards the received bitstream and does not need to perform other processing. When the low-latency enable signal is configured, the control module 12 performs the above functions.

[0102] The embodiment of the present invention further provides a PCIe system, which includes an upstream device, a downstream device, and the above-mentioned PCIe retimer.

[0103] The embodiment of the present invention further provides an electronic device, which includes the above-mentioned PCIe system.

[0104] In summary, a PCIe retimer, a PCIe system, and an electronic device provided by the embodiment of the present invention. The decoding and descrambling module decodes and descrambles the output bitstream of the upstream device and outputs the decoded and descrambled bitstream to the control module. When the low-latency trigger condition is met, the control module modifies the second type of bitstream (TS2 bitstream) in the decoded and descrambled bitstream to the first type of bitstream (TS1 bitstream), and transmits the modified bitstream to the de-skew module. The de-skew module performs de-skew processing on the received bitstream and transmits the de-skewed bitstream to the encoding and scrambling module; the encoding and scrambling module performs encoding and scrambling processing on the received bitstream and transmits the encoded and scrambled bitstream to the downstream device; after the control module determines that the low-latency path is aligned with the main path, it controls the low-latency path to be the current working path. The state machine of the downstream device will not perform a state transition due to receiving a preset number of second-type bitstreams, thereby dragging the state transition time of the upstream device and the downstream device, achieving the purpose of dragging the state machine, and enabling the PCIe retimer to have more time for path switching without generating bit errors.

[0105] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0106] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and without departing from the spirit or essential characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, in any regard, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Accordingly, all changes that fall within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. A PCIe retimer, characterized in that, The PCIe retimer includes: a deskew module, a control module, a decoding and descrambling module, an encoding and scrambling module, and a low-latency path. The control module includes a main control unit and a path switching module. The output end of the decoding and descrambling module and the input end of the deskew module are connected to the main control unit. The control end of the low-latency path is connected to the path switching module, and the path switching module is connected to the main control unit; The input end of the decoding and descrambling module and the input end of the low-latency path are used to connect to the output end of the upstream device. The output end of the deskew module is connected to the encoding and scrambling module. The output end of the encoding and scrambling module and the output end of the low-latency path are used to connect to the downstream device; The decoding and descrambling module is used to perform decoding and descrambling processing on the output bitstream of the upstream device and output the decoded and descrambled bitstream to the control module; The main control unit is used to determine that the low-latency trigger condition is met when both the downstream device and the upstream device are in the receive-end configuration recovery state, the rate of the output bitstream of the upstream device is greater than a preset rate threshold, and a bitstream that meets the second type of bitstream judgment condition is received. Among them, the second type of bitstream judgment condition includes that the target symbol corresponding to the bitstream matches its corresponding target content; The main control unit is used to modify the second type of bitstream in the decoded and descrambled bitstream into the first type of bitstream and transmit the modified bitstream to the deskew module when the low-latency trigger condition is met. The second type of bitstream is the trigger bitstream for the downstream device to perform a state transition; The deskew module is used to perform deskewing processing on the received bitstream and transmit the deskewed bitstream to the encoding and scrambling module; The encoding and scrambling module is used to perform encoding and scrambling processing on the received bitstream and transmit the encoded and scrambled bitstream to the downstream device; The path switching module is used to control the low-latency path as the current working path and send a stop modification instruction to the main control unit after determining that the low-latency path is aligned with the main path, so that the main control unit stops modifying the decoded and descrambled bitstream. Among them, the main path is the path passing through the deskew module.

2. The PCIe retimer according to claim 1, wherein After the low-latency path is aligned with the main path, the control module stops modifying the decoded and descrambled bitstream.

3. The PCIe retimer according to claim 1, wherein The main control unit is further used to determine that an abnormal signal is received when the abnormal monitoring symbol corresponding to the received bitstream does not match its corresponding target content; The main control unit is further used to send an exit instruction to the path switching module when an abnormal signal is received, so that the path switching module stops judging whether the low-latency path is aligned with the main path; The main control unit is further used to stop modifying the decoded and descrambled bitstream when an abnormal signal is received, or keep modifying the decoded and descrambled bitstream and stop modifying the decoded and descrambled bitstream after a preset time length.

4. The PCIe retimer according to claim 3, wherein The master control unit is further configured to determine that an abnormal signal is received when it monitors that the rate of the output bitstream of the upstream device is less than a preset rate threshold; The master control unit is further configured to determine that an abnormal signal is received when it monitors that the state machine of the upstream device or the state machine of the downstream device meets the state transition condition; The state transition condition is the condition for the state machine to jump from the receive - end configured recovery state to the abnormal state, or the state transition condition is for the state machine to jump from the idle state to the loopback state, the prohibited state, or the thermal reset state.

5. The PCIe retimer according to claim 1, wherein The decoding and descrambling module is configured to provide a storage start signal to the master control unit when it detects the dock characteristics of the decoded and descrambled bitstream; The decoding and descrambling module is configured to provide a high - level valid flag signal to the master control unit when it detects that the decoded and descrambled bitstream is valid data; The master control unit is configured to determine whether the class identification symbol of the received bitstream matches its corresponding target content after receiving the storage start signal and when the valid flag signal is in the high - level state. If they match, it determines that the current bitstream is the first - type bitstream and stores the current bitstream; The master control unit is configured to replace the second - type bitstream in the decoded and descrambled bitstream with the latest stored first - type bitstream to complete the modification of the decoded and descrambled bitstream.

6. The PCIe retimer according to claim 1, wherein The path switching module is configured to monitor the output bitstream of the de - skew module in the main path. When the number of electrical idle exit sequences output by the de - skew module is greater than the monitoring threshold, it determines that the low - latency path is aligned with the main path.

7. The PCIe retimer according to claim 1, wherein The master control unit is further configured to count the number of times the main path enters or exits the low - latency mode. The number data includes the entry times of entering the low - latency mode and the exit times of exiting the low - latency mode; The master control unit is further configured to compare the number data of the main path with the number data of the opposite path corresponding to the main path to determine whether there is an abnormality in the operation.

8. A PCIe system, characterized in that, The PCIe system includes an upstream device, a downstream device, and the PCIe retimer according to any one of claims 1 - 7.

9. An electronic device, characterized in that, Including the PCIe system according to claim 8.

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