Square Euclidean distance calculation method based on split gate flash memory

Abstract

The invention discloses a square Euclidean distance calculation method based on a split gate flash memory, and belongs to the technical field of microelectronics and integrated circuits. According to the method, the square Euclidean distance is used as a quadratic polynomial function of a feature vector coordinate and is mapped to a separation gate flash memory weight array for calculation, and hardware is used for realizing acceleration of calculation of the square Euclidean distance. Square Euclidean distance calculation is achieved based on the split gate flash memory, the calculation time can be effectively shortened, the system energy efficiency is improved, and the operation efficiency of related algorithms is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of microelectronics and integrated circuits, and in particular relates to a method for calculating squared Euclidean distance based on a split-gate flash memory. Background Art

[0002] Euclidean distance is the most direct distance measurement method, which is mathematically expressed as the straight-line distance between two points in space. Euclidean distance has the advantages of being intuitive, easy to understand, and highly interpretable, and is widely used in machine learning fields such as cluster analysis, anomaly detection, recommendation systems, and regression algorithms. Euclidean distance can be used to design loss functions to measure the difference between predicted values ​​and true values; it can be used to optimize gradient descent algorithms to calculate the length of the gradient to control the learning rate; it can be used for feature extraction to calculate the distance between feature vectors to measure the similarity between samples. When executing algorithms involving Euclidean distance, a common task is to calculate the Euclidean distance between a test point and all other data points in the data set, so the calculation process of the Euclidean distance is a key factor affecting the performance of the algorithm. The calculation of the Euclidean distance involves summing the square root of the difference of each dimension of the feature vector. In many cases, calculating the squared Euclidean distance and calculating the Euclidean distance can achieve the same effect for the algorithm.

[0003] The calculation of squared Euclidean distance is relatively simple when the amount of data is small or the dimension is low, but as the dimension of the data increases or the total amount of data increases, the complexity of the calculation will increase significantly, and the required calculation time will also increase significantly. In the case of huge amounts of data, the requirements for the memory and processor required to complete the calculation of squared Euclidean distance are also higher, and the calculation process will be limited by bandwidth, which further increases the complexity of squared Euclidean distance calculation. Summary of the invention

[0004] The purpose of the present invention is to propose a method for calculating the squared Euclidean distance based on a split-gate flash memory array, use hardware to accelerate the calculation of the squared Euclidean distance, improve the operating efficiency of related algorithms, and enhance system energy efficiency.

[0005] The technical solution of the present invention is as follows:

[0006] A method for calculating squared Euclidean distance based on split-gate flash memory, characterized in that the squared Euclidean distance is mapped as a quadratic polynomial function of feature vector coordinates to a split-gate flash memory weight array for calculation, comprising the following steps:

[0007] 1) Determine the array weight and input voltage vector according to the function expression of the squared Euclidean distance;

[0008] 2) writing the weights into the split-gate flash memory weight array respectively;

[0009] 3) Applying an input voltage to the split-gate flash memory weight array, performing a matrix-two-vector multiplication calculation on the split-gate flash memory weight array, wherein the output current of the split-gate flash memory weight array is equivalent to the squared Euclidean distance between two points, thereby completing the calculation of the squared Euclidean distance.

[0010] Furthermore, the split gate flash memory weight array is composed of an arrangement of split gate flash memory devices, and the split gate flash memory devices include a floating gate, a selection gate, a coupling gate, an erase gate, a source and a drain, wherein the selection gate is separated from the floating gate and is located between the drain and the source; the coupling gate is located above the floating gate to assist the source in regulating the floating gate; the erase gate is located above the source and is adjacent to the floating gate, and the drain and erase gate of the split gate flash memory devices in the same column in the split gate flash memory array are respectively connected by a bit line BL and an erase line EG, and the bit line BL and the erase line EG are parallel; the selection gate and the coupling gate of the split gate flash memory devices in the same row are respectively connected by a word line WL and a coupling line CG; the source of the split gate flash memory device is connected by a source line SL, and the word line WL, the coupling line CG and the source line SL are parallel.

[0011] Furthermore, if the function expression of the squared Euclidean distance is a positive weight matrix W + and the negative weight matrix

[0012] in The "1" and "0" in the matrix represent the high transconductance state and the low transconductance state of the split-gate flash memory device in the array, respectively. The specific steps include:

[0013] 1) The positive weight matrix W + Write the positive weight array of the split-gate flash memory and the negative weight matrix W - Writing to a split-gate flash memory negative weight array;

[0014] 2) The two split-gate flash memory weight arrays share the same input voltage vector, namely, the bit line input voltage vector of the positive split-gate flash memory weight array and the negative split-gate flash memory weight array and word line input voltage vector same;

[0015] 3) When calculating the squared Euclidean distance, all source lines of the two split-gate flash memory weight arrays are connected and their levels are 0V, all erase lines are grounded, and all coupling line levels are set to the same fixed value;

[0016] 4) Apply bit line voltage input vector to positive and negative split gate flash memory positive weight array and word line voltage input vector Perform parallel read operation, the read current is the calculation result of the positive and negative weight array current of the split gate flash memory, that is:

[0017]

[0018] 5) Will I p with I n Subtract and get the total output current I out , I out Represents the squared Euclidean distance between two points:

[0019]

[0020] Furthermore, if the function expression of the squared Euclidean distance is a positive weight matrix

[0021] in, The "1" and "0" in the matrix represent the high transconductance state and the low transconductance state of the split-gate flash memory device in the array respectively; the specific steps include:

[0022] 1) The positive weight matrix W + writing to a split-gate flash memory weight array;

[0023] 2) When calculating the squared Euclidean distance, all source lines of the split-gate flash memory weight array are connected and their levels are 0V, all erase lines are grounded, and all coupling line levels are set to the same fixed value;

[0024] 3) Apply bit line voltage input vector to split gate flash memory weight array and word line voltage input vector Perform a parallel read operation, and the read current is the calculation result of the positive array current, that is:

[0025] 4) Apply bit line voltage input vector to split gate flash memory weight array and word line voltage input vector Perform a parallel read operation, and the read current is the calculated result of the negative array current, that is:

[0026] 5) Will I p with I n Subtract and get the total output current I out , I out Represents the squared Euclidean distance between two points:

[0027]

[0028] Furthermore, if the function expression of the Euclidean distance is a positive weight matrix

[0029] Wherein, “1” indicates a high transconductance state of the split-gate flash memory device; the specific steps include:

[0030] 1) The positive weight matrix Writing to a single-rank device in a split-gate flash memory array;

[0031] 2) When calculating the squared Euclidean distance, all source lines of the devices in the column are grounded, all erase lines are grounded, and the bit line level of the column is set to a fixed value;

[0032] 3) Applying the coupled gate voltage input vector to the single-row device and word line voltage input vector Perform a parallel read operation, and the read current is the calculation result of the positive current, that is:

[0033] 4) Apply the bit line voltage input vector to the single column device and word line voltage input vector Perform a parallel read operation, and the read current is the calculation result of the negative current, that is:

[0034] 5) Will I p with I n Subtract and get the total output current I out , I out Represents the squared Euclidean distance between two points:

[0035]

[0036] The present invention has the following advantages:

[0037] The present invention realizes squared Euclidean distance calculation based on split-gate flash memory, which can effectively reduce calculation time, improve system energy efficiency, and improve the operating efficiency of related algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the structure of a split-gate flash memory device;

[0039] Figure 2 It is a schematic diagram of the structure of the split-gate flash memory weight array;

[0040] Figure 3 A schematic diagram of calculating the squared Euclidean distance using the positive and negative split-gate flash memory weight arrays according to the first embodiment;

[0041] Figure 4 is a flow chart of the calculation method of embodiment 1;

[0042] Figure 5 A schematic diagram of calculating the squared Euclidean distance of a multiplexed split-gate flash memory weight array according to the second embodiment;

[0043] Figure 6 is a flow chart of the calculation method of Example 2;

[0044] Figure 7 A schematic diagram of a single column of split-gate flash memory devices in a split-gate flash memory weight array in Embodiment 3;

[0045] Figure 8 This is a flow chart of the calculation method of Example 3. DETAILED DESCRIPTION

[0046] The following further describes the implementation of the present invention through specific examples in conjunction with the accompanying drawings.

[0047] It should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

[0048] The structure of a split-gate flash memory device is as follows Figure 1 As shown in the figure, the device has five ports: select gate, coupling gate, erase gate, source and drain. The select gate is separated from the floating gate and located between the drain and the source. The coupling gate is located above the floating gate to assist the source in regulating the floating gate. The erase gate is located above the source and adjacent to the floating gate. When the erase gate and source are grounded, the transconductance g of the coupling gate of the split-gate flash memory device is m =W g ×V BL Among them, V BL is the device drain voltage; W g It is the gate control factor of the device selection gate, which reflects the control ability of the selection gate on the channel. g The floating gate charge state W and the coupled gate voltage V GG Two factors determine the g =W×V CG Therefore, the expression of the device coupled gate transconductance is g m =W×V CG ×V BL The device drain current can be expressed by the product of the select gate transconductance and the select gate voltage, that is, I BL =g m ×V WL =W×V CG ×V BL ×V WL .

[0049] The above split-gate flash memory devices are arranged to form a split-gate flash memory array, such as Figure 2As shown. The drain and erase gate of the split-gate flash memory transistors in the same column are connected by the bit line (BL) and the erase line (EG), respectively, and the bit line and the erase line are parallel; the select gate and the coupling gate of the split-gate flash memory transistors in the same row are connected by the word line (WL) and the coupling line (CG), respectively; the source of the split-gate flash memory transistor is connected by the source line (SL), and the word line, the coupling line and the source line are parallel. The split-gate flash memory array can realize matrix-multi-vector multiplication operations. The storage matrix W is first connected with the bit line input voltage vector Do the inner product and add the result to the coupled line input voltage vector and word line input voltage vector Do the element product and finally get the source line output current vector Right now:

[0050]

[0051] When one of the input vectors is fixed, the split-gate flash weight array performs a matrix-two-vector multiplication. For a specific value, the storage matrix W can be combined with Merge into the gate control factor matrix W g , we can get:

[0052]

[0053] The source current vector represents the multiplication result of the gating factor matrix with the bit line voltage vector and the word line voltage vector.

[0054] For two points P(p1,…,p n ) and Q(q1,…,q n ), the squared Euclidean distance is:

[0055]

[0056] According to the above calculation method, the total output current can be obtained as follows:

[0057]

[0058] The total output current is equivalent to the squared Euclidean distance between two points, indicating that the split-gate flash memory weight array can complete the calculation of the squared Euclidean distance.

[0059] Embodiment 1:

[0060] Figure 3A method of array mapping based on squared Euclidean distance calculation of split-gate flash memory is presented. The gate control factor matrix W is realized by using two complementary split-gate flash memory weight arrays. g The two split-gate flash memory weight arrays share the same input voltage vector, namely the bit line input voltage vector of the positive split-gate flash memory weight array and the negative split-gate flash memory weight array. and word line input voltage vector Respectively the same.

[0061] For two points P(p1,…,p n ) and Q(q1,…,q n ), where the coordinate values ​​of P and Q have been normalized according to the linear region voltage input range of the split-gate flash memory, and are set W g as follows:

[0062]

[0063]

[0064] in The "1" and "0" in the matrix represent the high transconductance state and the low transconductance state of the split-gate flash memory device in the array, respectively. g The scale is 2n*2n.

[0065] Define the source line output current vector of the positive split-gate flash memory weight array as the positive array current The source line output current vector of the negative split-gate flash memory weight array is the negative array current When calculating the squared Euclidean distance, all source lines of the two split-gate flash memory weight arrays are connected and their levels are 0V, all erase lines are grounded, and all coupling line levels are set to the same fixed value.

[0066] The squared Euclidean distance calculation method based on the above split-gate flash memory weight array is as follows: Figure 4 As shown:

[0067] 1) The positive weight matrix W + Write the positive weight array of the split gate flash memory; write the negative weight matrix W - Writing to a split-gate flash memory negative weight array;

[0068] 2) The two split-gate flash memory weight arrays share the same input voltage vector, namely, the bit line input voltage vector of the positive split-gate flash memory weight array and the negative split-gate flash memory weight array and word line input voltage vector same;

[0069] 3) When calculating the squared Euclidean distance, all source lines of the two split-gate flash memory weight arrays are connected and their levels are 0V, all erase lines are grounded, and all coupling line levels are set to the same fixed value;

[0070] 4) Apply the bit line voltage input vector to the positive and negative weight arrays and word line voltage input vector Perform parallel read operation, and the read current is the calculation result of positive and negative array current, that is:

[0071]

[0072] 5) Will I p with I n Subtract and get the total output current I out , I out Represents the squared Euclidean distance between two points:

[0073]

[0074] Embodiment 2:

[0075] Based on the same inventive concept of embodiment 1, Figure 5 Another array mapping method is given. That is, the split gate flash memory weight array is reused to complete the positive split gate flash memory weight array source line output current and negative-positive split-gate flash memory weight array source line output current Calculation.

[0076] When calculating the squared Euclidean distance, all source lines of the split-gate flash memory weight array are connected and their levels are 0V, all erase lines are grounded, and all coupling line levels are set to the same fixed value.

[0077] For two points P(p1,…,p n ) and Q(q1,…,q n ), where the coordinate values ​​of P and Q have been normalized according to the linear region voltage input range of the split-gate flash memory. of as follows:

[0078]

[0079] Setting calculation of as follows:

[0080]

[0081] or:

[0082]

[0083] Set W + as follows:

[0084]

[0085] in, The "1" and "0" in the matrix represent the high transconductance state and the low transconductance state of the split-gate flash memory device in the array, respectively. + The scale is 2n*2n.

[0086] The squared Euclidean distance calculation method based on the above split-gate flash memory weight array is as follows: Figure 6 As shown:

[0087] 1) The positive weight matrix W + Writing to a split-gate flash memory array;

[0088] 2) When calculating the squared Euclidean distance, all source lines of the split-gate flash memory weight array are connected and their levels are 0V, all erase lines are grounded, and all coupling line levels are set to the same fixed value;

[0089] 3) Apply the bit line voltage input vector to the array and word line voltage input vector Perform a parallel read operation, and the read current is the calculation result of the positive array current, that is:

[0090] 4) Apply the bit line voltage input vector to the array and word line voltage input vector Perform a parallel read operation, and the read current is the calculated result of the negative array current, that is:

[0091] 5) Will I p with I n Subtract and get the total output current I out , I out Represents the squared Euclidean distance between two points:

[0092]

[0093] Embodiment three:

[0094] Figure 7 The schematic diagram of a single-column split-gate flash memory device. The positive current is defined as Negative current The bit line output current of a single column device is shown in Figure 2. Multiplexing a single column split gate flash memory positive weight device is completed. and When calculating the squared Euclidean distance, all source lines of a single column of devices are grounded, all erase lines are grounded, and the bit line level of the column is set to a fixed value.

[0095] For two points P(p1,…,p n ) and Q(q1,…,q n ), where the coordinate values ​​of P and Q have been normalized according to the linear region voltage input range of the split-gate flash memory. of as follows:

[0096]

[0097] Setting calculation of as follows:

[0098]

[0099] or:

[0100]

[0101] set up As shown below, "1" indicates a high transconductance state of a split-gate flash memory device:

[0102]

[0103] The squared Euclidean distance calculation method for a column of devices in a split-gate flash memory weight array is as follows: Figure 8 As shown:

[0104] 1) The positive weight Writing to a split-gate flash memory single-rank device;

[0105] 2) When calculating the squared Euclidean distance, all source lines of the devices in the column are grounded, all erase lines are grounded, and the bit line level of the column is set to a fixed value;

[0106] 3) Applying the coupled gate voltage input vector to the single-row device and word line voltage input vector Perform a parallel read operation, and the read current is the calculation result of the positive current, that is:

[0107] 4) Apply the bit line voltage input vector to the single column device and word line voltage input vector Perform a parallel read operation, and the read current is the calculation result of the negative current, that is:

[0108] 5) Will I pwith I n Subtract and get the total output current I out , I out Represents the squared Euclidean distance between two points:

[0109]

[0110] Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for calculating squared Euclidean distance based on split-gate flash memory, characterized in that: The squared Euclidean distance is calculated as a quadratic polynomial function of the feature vector coordinates mapped to the split-gate flash memory weight array, which includes the following steps: 1) Determine the array weight and input voltage vector according to the function expression of the squared Euclidean distance; 2) writing the weights into the split-gate flash memory weight array respectively; 3) Applying an input voltage to the split-gate flash memory weight array, the split-gate flash memory weight array performs a matrix-two-vector multiplication calculation, and the output current of the split-gate flash memory weight array is equivalent to the squared Euclidean distance between two points, thereby completing the calculation of the squared Euclidean distance.

2. The method for calculating squared Euclidean distance based on split-gate flash memory according to claim 1, characterized in that: The split gate flash memory weight array is composed of an arrangement of split gate flash memory devices, wherein the split gate flash memory device includes a floating gate, a selection gate, a coupling gate, an erase gate, a source and a drain, wherein the selection gate is separated from the floating gate and is located between the drain and the source; the coupling gate is located above the floating gate and assists the source in regulating the floating gate; the erase gate is located above the source and is adjacent to the floating gate; the drain and the erase gate of the split gate flash memory device in the same column in the split gate flash memory array are respectively connected by a bit line BL and an erase line EG, and the bit line BL and the erase line EG are parallel; the selection gate and the coupling gate of the split gate flash memory device in the same row are respectively connected by a word line WL and a coupling line CG; the source of the split gate flash memory device is connected by a source line SL, and the word line WL, the coupling line CG and the source line SL are parallel.

3. The method for calculating squared Euclidean distance based on split-gate flash memory according to claim 2, characterized in that: If the function expression of the squared Euclidean distance is a positive weight matrix W + and the negative weight matrix W - , in The "1" and "0" in the matrix represent the high transconductance state and the low transconductance state of the split-gate flash memory device in the array, respectively. The specific steps include: 1) The positive weight matrix W + Write the positive weight array of the split-gate flash memory and the negative weight matrix W - Writing split-gate flash memory negative weight arrays; 2) The two split-gate flash memory weight arrays share the same input voltage vector, namely, the bit line input voltage vector of the positive split-gate flash memory weight array and the negative split-gate flash memory weight array and word line input voltage vector same; 3) When calculating the squared Euclidean distance, all source lines of the two split-gate flash memory weight arrays are connected and their levels are 0V, all erase lines are grounded, and all coupling line levels are set to the same fixed value; 4) Apply bit line voltage input vector to positive and negative split gate flash memory positive weight array and word line voltage input vector Perform parallel read operation, the read current is the calculation result of the positive and negative weight array current of the split gate flash memory, that is: 5) Will I p with I n Subtract and get the total output current I out , I out Represents the squared Euclidean distance between two points:

4. The method for calculating squared Euclidean distance based on split-gate flash memory according to claim 2, characterized in that: If the function expression of the squared Euclidean distance is the weight matrix W + , in, The "1" and "0" in the matrix represent the high transconductance state and the low transconductance state of the split-gate flash memory device in the array respectively; the specific steps include: 1) The positive weight matrix W + writing to a split-gate flash memory weight array; 2) When calculating the squared Euclidean distance, all source lines of the split-gate flash memory weight array are connected and their levels are 0V, all erase lines are grounded, and all coupling line levels are set to the same fixed value; 3) Apply bit line voltage input vector to split gate flash memory weight array and word line voltage input vector Perform a parallel read operation, and the read current is the calculation result of the positive array current, that is: 4) Apply bit line voltage input vector to split gate flash memory weight array and word line voltage input vector Perform a parallel read operation, and the read current is the calculated result of the negative array current, that is: 5) Will I p with I n Subtract and get the total output current I out , I out Represents the squared Euclidean distance between two points:

5. The method for calculating squared Euclidean distance based on split-gate flash memory according to claim 2, characterized in that: If the function expression of the Euclidean distance is a positive weight matrix Wherein, "1" indicates a high transconductance state of the split-gate flash memory device; the specific steps include: 1) The positive weight matrix Writing to a single-rank device in a split-gate flash memory array; 2) When calculating the squared Euclidean distance, all source lines of the devices in the column are grounded, all erase lines are grounded, and the bit line level of the column is set to a fixed value; 3) Applying the coupled gate voltage input vector to the single-row device and word line voltage input vector Perform a parallel read operation, and the read current is the calculation result of the positive current, that is: 4) Apply the bit line voltage input vector to the single column device and word line voltage input vector Perform a parallel read operation, and the read current is the calculation result of the negative current, that is: 5) Will I p with I n Subtract and get the total output current I out , I out Represents the squared Euclidean distance between two points:

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