High-reliability circuit low-power-consumption design method

Abstract

The invention discloses a low-power-consumption design method for a digital integrated circuit. According to the design method, the low-power-consumption design target of the digital integrated circuit is achieved by adjusting the input signal probability of the digital integrated circuit. According to the power supply voltage of the digital integrated circuit and the input signal probability, and the combined effect of the power supply voltage and the input signal probability on the aging delay of the digital integrated circuit, the low-power-consumption design target of the digital integrated circuit is achieved. The design method comprises the following steps: establishing an input signal probability propagation model of the critical path of the digital integrated circuit, and measuring and calculating the input signal probability of each logic gate standard unit on the critical path. And constructing an aging delay prediction model of the digital integrated circuit, and predicting the aging delay of the digital integrated circuit according to the input signal probability of the standard unit on the critical path.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device reliability and integrated circuit design, and in particular to a high-reliability circuit low-power design method, and a digital integrated circuit designed by the design method. Background Art

[0002] In the field of integrated circuit design and semiconductor device reliability issues, low-power design has become the latest technical target to be focused on, including how to reduce the dynamic and static power consumption of circuits. Voltage scaling has been considered an effective method to solve this problem. This method uses the lowest possible voltage to run the circuit while ensuring performance, thereby reducing power consumption. In addition, dynamic voltage and frequency adjustment technology significantly improves the energy efficiency of the circuit by adjusting voltage and frequency to balance performance and power consumption. However, voltage scaling requires fine control and delicate balance to avoid accelerating circuit aging, which may reduce system reliability over time. Therefore, when implementing these low-power technologies, their impact on long-term stability needs to be carefully considered.

[0003] In terms of low-power design of integrated circuits, clock gating is another method used. It reduces dynamic power consumption by disabling the clock signals of inactive circuit components. It has been proven that this method can effectively reduce unnecessary switching activities, thereby reducing power consumption. On the other hand, the gating method for power circuits is to reduce static power consumption by completely turning off the power supply of inactive circuit blocks. This method is particularly effective in minimizing leakage power during idle periods, which helps save the overall power consumption of systolic arrays. In practical applications, the design and implementation of clock gating also need to consider multiple factors, including timing, power consumption, area, and design complexity. For example, designers need to decide when and how to introduce clock gating in the design, and how to balance the number of gating units and the effect of power saving.

[0004] In addition, the use of approximate computing techniques in circuits has become a promising strategy to improve energy efficiency, especially in applications where there is a trade-off between computational accuracy and power consumption. Approximate computing (AC) is a technique used in circuit design to improve energy efficiency. It significantly reduces the energy consumption of circuits by allowing a certain degree of controlled loss of accuracy. This technique is particularly suitable for applications that can tolerate a certain degree of error, such as machine learning, image processing, signal processing, etc. The principle of approximate computing is to deliberately introduce acceptable errors in the calculation process to reduce the use of computing resources and thus reduce energy consumption. For example, in digital circuits, approximate computing is achieved by simplifying the calculation logic, reducing data accuracy, or reducing the number of calculation steps, thereby reducing the amount of calculation and power consumption without significantly affecting the final result. Summary of the invention

[0005] One of the embodiments of the present disclosure is a method for low power consumption design of a high-reliability digital integrated circuit, which realizes low power consumption design by adjusting the probability of an input signal, including:

[0006] By establishing a new framework for aging delays that are jointly influenced by power supply voltage and input signal probability, we introduce a method that can reduce the voltage by about 10% and maintain the same computing speed after circuit aging, thereby significantly improving energy efficiency;

[0007] Construct a critical path signal probability propagation model, and accurately calculate the signal probability at the critical path unit based on the input signal probability through careful analysis of the netlist;

[0008] Two strategies are proposed to enhance the sensitivity of the path to signal probability changes, thereby expanding the voltage adjustment space and improving the effectiveness of the method of the present invention.

[0009] By adjusting the signal input probability, the circuit calculation speed can be kept unchanged while reducing the operating voltage.

[0010] One of the beneficial effects of the embodiments of the present disclosure is to achieve low power consumption circuit design by changing the probability of input signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, in which:

[0012] Figure 1 A schematic diagram of a curve showing the relationship between circuit aging delay and operating voltage according to one embodiment of the present invention.

[0013] Figure 2 Schematic diagram of fluctuation of aging delay around a baseline caused by input signal probability according to one embodiment of the present invention.

[0014] Figure 3 A schematic diagram of the relationship between basic logic gates, truth tables and signal probability transmission according to one embodiment of the present invention.

[0015] Figure 4 A schematic diagram of a critical path of a systolic array multiply-add unit at 0.9V according to one embodiment of the present invention.

[0016] Figure 5 A schematic diagram of a curve showing the relationship between the aging delay of a systolic array multiplication-addition unit circuit and the operating voltage and the input signal probability according to one embodiment of the present invention. DETAILED DESCRIPTION

[0017] Although existing design solutions have advanced the development of low-power integrated circuit technology, these designs still have some problems. For example, voltage scaling must address the trade-off between reduced power consumption and increased sensitivity to aging effects and delay variations. Clock gating requires precise control to avoid timing issues, while power gating must manage conversion overhead and potential impact on system stability.

[0018] For AI chips that are currently undergoing rapid technological iterations, it is particularly important to reduce power consumption as much as possible while ensuring reliability. Although significant progress has been made in optimizing the energy efficiency of systolic arrays and their multiplication and addition units in AI chips through various hardware and algorithm innovations, these studies have overlooked the key role of signal probability adjustment in reducing power consumption. This shows that further improving the energy efficiency of computing systems through signal probability manipulation would be a technological development direction with great development potential.

[0019] The systolic array mentioned here is a parallel computing architecture. The multiply-accumulate unit (MAC) is a unit that performs multiplication and addition operations and is a processing unit in the systolic array. In the systolic array, the multiply-accumulate unit usually performs matrix multiplication operations, which is a basic operation in numerical and machine learning applications. The multiply-accumulate units can work in parallel to improve computing speed and efficiency.

[0020] For example, in Google's TPU (Tensor Processing Unit), the systolic array is used as the core structure for performing matrix multiplication acceleration. TPU accelerates matrix multiplication through the MAC module in the systolic array, where the elements of the two matrices flow into the MAC calculation array in a specific arrangement, and each step can get an intermediate result in the MAC calculation unit. When all elements flow through the MAC calculation array, the complete matrix multiplication result is obtained.

[0021] Therefore, the present disclosure proposes a method for optimizing circuit energy efficiency by adjusting the probability of input signals, utilizing the optimal signal probability and borrowing timing margin to reduce the operating voltage while maintaining the operating frequency and reliability of the circuit, thereby improving energy efficiency and providing a new idea for achieving low-power design.

[0022] According to one or more embodiments, a method for designing a high-reliability circuit with low power consumption is based on adjusting the signal probability (SP) to affect the circuit aging rate, thereby providing operating space for voltage regulation. Here, the signal probability is the probability that the signal is in a high or low state within a certain time. A high signal probability means that the signal is in a high or low state most of the time, while a low signal probability means that the signal switches frequently between these two states. This switching frequency has a direct impact on the aging of the circuit, because each state switch may cause wear and tear of the circuit elements. Adjusting the signal probability can affect the aging rate of the circuit, and by reducing unnecessary signal switching, the impact of the circuit aging mechanism can be slowed down, thereby extending the service life of the circuit.

[0023] In the disclosed embodiment, the setup time and hold time of the signal are considered constant, while the signal propagation time when the circuit is not aged is affected by the voltage. This is because by increasing the voltage, the charging and discharging speed of the capacitor changes, resulting in the adjustment of the signal propagation time when the circuit is not aged.

[0024] On the other hand, circuit aging is affected by voltage and signal probability. Higher voltage accelerates the aging process, while input signal probability interacts with the aging rate in a complex way due to different propagation modes in various logic gates. However, adjusting the signal probability reduces the degree of aging, allowing the adjusted voltage to achieve the same margin as the original voltage.

[0025] Therefore, the disclosed embodiments can achieve voltage regulation and reduce energy consumption while keeping the circuit running at the same speed. The essence of the disclosed embodiments is to use a portion of the timing margin allocated to aging at the original voltage of the circuit and return it as the aging process proceeds, thereby maintaining the same timing margin and improving energy efficiency through voltage regulation.

[0026] Since bias temperature instability (BTI) effects play a key role in the aging process in digital circuits, leading to changes in transistor threshold voltages. This phenomenon is intricately linked to the signal probabilities of different transistors within the circuit. Transistors subject to different signal probabilities experience different BTI-induced threshold voltage shifts, ultimately leading to uneven degradation. As a result, this uneven degradation can lead to uneven rise and fall delays of logic gates, especially at the end of their expected lifetime.

[0027] The detailed analysis of signal propagation within critical paths of different logic cells under various voltage conditions in the disclosed embodiments reveals a noteworthy observation. When the probability of input signals to the circuit is systematically adjusted, the signal probabilities on the critical paths exhibit an uneven distribution. This distribution reflects the complex interaction between input probabilities and operating voltage levels, which is summarized by the following general equation:

[0028] Δt aging =f( V DD ,SP in ) (1)

[0029] Here, SP in represents the probability of the input signal, V DD Indicates the operating voltage of the circuit, Δt aging represents the delay time due to circuit aging. This equation (1) summarizes the relationship between voltage, input signal probability and the resulting aging delay, highlighting the sensitivity of aging delay changes to changes in circuit input signal probability.

[0030] The disclosed embodiments further study the effect of input signal probability on aging delay under different voltage conditions, revealing the tendency of aging delay to fluctuate around its baseline value. The amplitude of these fluctuations is significantly affected by the input signal probability:

[0031] σ Δt =g(sensity,SP in ) (2)

[0032] Among them, sensitivity represents the sensitivity of the critical path of the circuit to the probability response of the input signal, SP in (signal probability of input) represents the input signal probability of the entire circuit. Δt Indicates the amplitude of the fluctuation of the aging delay around its baseline value. It quantifies the variability or uncertainty of the aging delay and reflects the degree of performance change of the circuit during the aging process. That is, the signal probability of the unit in the critical path is affected by the probability of the input signal. If the circuit is more sensitive to the probability of the input signal, the delay range floating around the baseline after aging will be larger when the probability of the input signal changes. This will help bring more operating space for adjusting the operating voltage.

[0033] This equation (2) emphasizes the key role of signal probability management in mitigating the adverse effects of aging, thereby improving circuit reliability and operational life. The results of the disclosed embodiments show the importance of incorporating signal probability considerations into the design and optimization process of digital circuits.

[0034] Therefore, based on the above findings, the operating domain of the integrated circuit power reduction design of the embodiment of the present disclosure can be determined. Although the overall trend shows that the circuit aging delay increases with voltage scaling, the curve presents a moderately changing area, such as Figure 1 As shown. The Delay Increase in the figure is the delay increase, in %. Voltage(V) is the voltage in volts. The horizontal axis in the figure represents voltage, and the vertical axis represents delay increase. The curve in the figure represents the changing trend of delay increase as the voltage increases. The voltage starts from 0.7V and ends at 1.2V. The value of delay increase starts from 0 and increases to more than 200%. In the curve in the figure, as the voltage increases from 0.7V to 1.2V, the value of delay increase decreases from the peak value to 0.

[0035] Figure 1 This modest change in the aging delay curve can be attributed to the interaction between voltage scaling and its BTI effect. At each voltage level, the adjustment of the input signal probability causes the aging delay of the critical path to fluctuate around the baseline value established before the adjustment. Therefore, within the curve segment where the aging delay responds weakly to voltage changes, the fluctuation ranges of the aging delays corresponding to adjacent voltages show considerable overlap, as shown in Figure 2. Figure 2 As shown in the figure, the Overlap Area in the figure refers to the overlapping area. When the input signal probability of the circuit is modified at a given voltage, the aging delay will fluctuate around its initial value and be highlighted in different colors. At the same time, the sensitivity of the aging delay to voltage changes has a smoother platform, Figure 2 Taking the multiply-add unit in the systolic array as an example, the aging delay is less sensitive to voltage changes around 0.9V to 1.0V. Therefore, the intersection of these fluctuations forms Figure 2 The overlapping area is shown.

[0036] The importance of the overlap region lies in its impact on circuit optimization. Within this region, signal probabilities can be adjusted to align the aging delay of a circuit running at a lower voltage with the aging delay of a circuit running at a higher voltage, effectively maintaining a consistent aging delay level across voltage conditions. This adjustment means that by fine-tuning the input signal probabilities, the circuit can achieve lower voltages and power consumption without sacrificing computational power. Essentially, the overlap region provides an opportunity to optimize energy efficiency through signal probability adjustments, thereby mitigating the impact of aging delays on circuit performance while reducing overall energy consumption.

[0037] Furthermore, the larger overlap helps to scale the circuit voltage at the same aging level by adjusting the signal probability, thus emphasizing a feasible approach to maintain consistent aging delay characteristics during voltage scaling. It can be concluded that the aging delay of the circuit is determined by both the operating voltage and the input signal probability.

[0038] In the embodiment of the present disclosure, an input signal probability propagation model is established. Considering the complex relationship between the probability of circuit input signals and the probability of input terminal signals of each unit in the critical path to control data transmission, the signal probability propagation model introduced in the present disclosure is intended to accurately calculate the input terminal signal probability of standard units along the critical path (the signal probability originating from the circuit input port), thereby solving the inherent complexity in data transmission dynamics.

[0039] Taking basic gates such as AND, NOT, OR, and XOR gates as examples, their output signal probabilities can be systematically derived from the input signal probabilities by using their respective truth tables, such as Figure 3 , Figure 4 This basic approach helps to formulate logical expressions that encapsulate the relationship between the input and output signal probabilities for each gate type.

[0040] Figure 3 -a includes a schematic diagram of a logical AND gate and its truth table. Logical expression:

[0041] SP OUT =(SP A +SP B -SP A ×SP B )

[0042] Among them, SP A The probability of input signal A, SP B The probability of input signal B, SP OUT is the probability of the output.

[0043] Figure 3 -b is the probability transmission calculation of the output signal of the logic NOT gate.

[0044] SP OUT =1-SP A

[0045] Figure 4This is a critical path diagram of a pulsating array multiply-add unit at 0.9V. The pulsating array multiply-add unit (PulsedArray Multiplier) is used to perform multiplication and addition operations. The pulsating array multiply-add unit is composed of multiple multipliers and adders. The critical path here refers to the signal path that determines the slowest operation speed of the digital circuit. For the pulsating array multiply-add unit, it may include an input register, a multiplier, an adder, an output register, or a full adder FA, a D flip-flop DFF.

[0046] On this basis, the logical expressions of more complex standard cells can be inferred from the combination of these basic gate circuits.

[0047] In order to establish an input signal probability propagation model, the present disclosure has written a Python program to measure the signal probability of each standard cell on the critical path of the circuit. The program implements the calculation of the critical path signal probability through the following two steps: First, each standard cell on the critical path is "traced to the source", that is, the input signal source of each standard cell is tracked until the circuit input end. In this process, the program records the signal propagation path from the circuit input end to the critical path, and clarifies which standard cells the circuit input end passes through to reach the critical path. Then, based on the standard cell model in the pdk library, a mathematical expression is used to quantify the signal propagation probability relationship of each type of standard cell. The signal propagation probability of each standard cell is determined by its logical characteristics. In the main program, the signal probability of the circuit input end is first substituted into the signal propagation path, and the signal propagation probability relationship expression of these paths is used to calculate the signal probability of each standard cell on the critical path. These calculation results are input into the subsequent circuit aging prediction model to help accurately evaluate the reliability of the circuit in actual operation.

[0048] At the same time, in the present disclosure, the aging prediction model requires information such as the critical path after circuit aging and the signal probability of each standard cell input on the critical path to make accurate aging predictions. That is, the output result of the input signal probability model is input into the circuit aging prediction model to help accurately evaluate the reliability of the circuit in actual operation. In constructing the circuit aging prediction model, the present disclosure analyzes the synthetically generated timing report file and netlist file, and extracts the critical path and data transmission relationship between each standard cell input and the circuit input at a specific voltage after aging. Subsequently, by establishing input and output signal probability transmission logic for the standard cells in the standard cell library, the program derives the input signal probability of each standard cell on the critical path, and inputs it into the aging prediction model together with the original signal probability, and obtains the aging delay of the circuit under a specific input probability and the baseline delay before the circuit is adjusted.

[0049] The program dynamically calculates the response of each node signal probability to the circuit input signal probability, outputs the input signal probability of each unit in the critical path, and uses the aging prediction model to predict the delay of the circuit after aging. Combined with the aging delay prediction model, the present disclosure uses the calculated signal probability to evaluate the performance degradation over time.

[0050] According to one or more embodiments, in a low-power design of an integrated circuit, a solution is proposed for enhancing the sensitivity of a circuit critical path and reducing power consumption.

[0051] In order to optimize circuit energy efficiency through signal probability modulation, the sensitivity of the critical path to the change of input signal probability becomes an important concern. This sensitivity describes the degree of response of the unit input along the critical path to the change of input signal probability, which directly affects the aging delay. The improvement of sensitivity is conducive to expanding the overlapping area of ​​aging delay curves under different voltages, thereby expanding the voltage adjustment space. The sensitivity here refers to the drastic degree of aging delay change with signal probability.

[0052] Given that large-scale digital circuits usually have multiple input ports, it is computationally impractical to explore the probability distribution of all possible input signals on all input bits of the digital circuit. Therefore, the disclosed embodiment adopts a more targeted approach by calculating the impact factor of each bit and preferentially exploring the bits that have the most significant impact on the aging delay, thereby simplifying the calculation process. The theoretical basis for this is that not all bits contribute equally to the circuit delay after aging. By conducting a detailed analysis to identify these key parts, the disclosed embodiment can ensure that the optimization work is focused on where the greatest improvement in energy efficiency can be achieved.

[0053] Here, signal probability modulation optimizes the energy efficiency of the circuit by changing the probability distribution of the input signal in the digital circuit (i.e., the probability that the signal is high or low). Critical paths refer to those signal paths that determine the minimum delay of the digital circuit. Sensitivity is the sensitivity of the critical path to the change in the probability of the input signal. If the critical path reacts significantly to the change in the input signal, then by adjusting the probability distribution of these signals, the aging delay can be effectively reduced. Aging delay means that with the passage of time and the use of the circuit, the performance of the circuit elements will gradually decline and age. Aging may cause an increase in signal propagation delay, i.e., aging delay, which affects the performance of the circuit. The operational flexibility of the circuit means that by adjusting the probability of the input signal, the performance of the circuit can be maintained under different working conditions, thereby achieving the operational flexibility of the circuit. The overlapping area of ​​the aging delay curve refers to the area where the aging delay is similar under different voltage conditions. Expanding this overlapping area means that the circuit can be operated in a wider voltage range while maintaining similar performance. Improving sensitivity helps to expand the voltage adjustment space, that is, the circuit can be operated in a wider voltage range without significantly increasing the aging delay.

[0054] The impact factor is an indicator that measures the impact of each input bit on the aging delay. By calculating the impact factor, it is possible to determine which input bits have the most significant impact on the aging delay.

[0055] Therefore, the optimization strategy of the present disclosure does not simply test all possible input signal probability distributions, but rather prioritizes those bits that have the greatest impact on aging delay by calculating the impact factor of each bit. This reduces the amount of calculation while ensuring that the optimization work is focused on the areas most likely to improve energy efficiency. Through careful analysis, the circuit parts that contribute the most to aging delay can be identified to achieve the greatest energy efficiency improvement.

[0056] However, this method is not without limitations. Focusing only on the signal probability changes of individual bits may limit the impact on the signal probability of standard cells on the critical path, which may limit the overlap area and further limit the voltage adjustment space. To solve this problem, the embodiments of the present disclosure propose two methods to enhance the sensitivity of the critical path.

[0057] The first is that for the critical path under a given voltage, it can be found through calculation that the signal probability of certain bits has a particularly significant impact on the path aging delay. The present disclosure analyzes the impact of the signal probability of different bits on each standard cell on the path. For example, assuming that the multiplication and addition unit circuit of the pulsating array is at 0.9V, the impact of the third and fourth inputs is the most significant. The analysis found that a specific bit that has a greater impact on the critical path of the circuit may only affect some standard cells, while the signal probability of the bit that has the second greatest impact affects other standard cells, and the range of standard cells affected by the two does not overlap. This shows that the impact of the input signal probability of many specific bits is limited to certain standard cells.

[0058] Therefore, this method can iteratively adjust specific bits whose impact ranges do not overlap, while other bits remain unchanged, thereby generating a relationship between the signal probability change and the aging delay of the two bits that have the greatest impact on the circuit. For example, the signal probability of the third bit of the affected standard unit in the multiplication and addition unit circuit of the systolic array is iterated, while other bits are kept unchanged, to generate an aging delay relationship that changes with the signal probability of the third bit. Similarly, the signal probability of the fourth bit is iterated to generate an aging delay curve that responds to the change in the signal probability of the fourth bit. By merging these aging delay relationships, the range of changes in the delay after critical path aging caused by changes in the signal probabilities of the third and fourth bits can be obtained.

[0059] This method provides a larger variation range for the aging delay of the critical path by adjusting the input signal probability, thereby optimizing the performance and energy efficiency of the circuit. This method is applicable to various voltage and circuit environments, especially complex logic circuits in high-performance computing systems.

[0060] The second method is to enhance the sensitivity of the critical path to the probability of the input signal, which is achieved by discarding the value of the bit that has a small impact on the accuracy. When the influence ranges of the two bits that have the greatest impact on the circuit overlap, the first method is no longer effective. At this time, if the critical path is in a deeper pipeline, the analysis shows that the signal probability of the critical path unit has been fluctuating around 0.5, which indicates that the circuit critical path is less sensitive to the input probability at this time. This phenomenon is attributed to the critical path being located in a deeper pipeline stage in the circuit. This means that the input data must first pass through multiple logic gates before reaching the critical path. If the probability of each bit being "1" is high, the data transmitted to the critical path will experience multiple "collisions", which is closely consistent with the statistical specification, making the impact of the input signal probability on the critical path negligible. On the contrary, if the probability of each bit being "0" is high, the data after being transmitted through multiple logic gates is more likely to retain its original state (for example, "0" remains as "0", and "1' remains as '1' after passing through these logic gates), thereby enhancing the direct transmission of the first bit of data to the critical path unit, thereby enhancing its sensitivity.

[0061] Therefore, the embodiment of the present disclosure proposes a method to amplify the impact of the input signal probability on the critical path of the circuit by sacrificing the data of the bits that have less impact on the precision. Taking the multiplication and addition unit of the pulsating array at 1.0V as an example, the input signal probability of the 2nd to 7th bits of fp16 is adjusted to SPin=0.999 (that is, the data of these bits are almost always 0), thereby enhancing the sensitivity of the 1.0V critical path to the input signal probability. This adjustment is more beneficial to data in fp16 format than 8-bit int because it has the least impact on precision. Compared with 8-bit integer (int8), fp16 provides a larger numerical range and precision. The implementation results show that this significantly improves the sensitivity, which also verifies the viewpoint of the embodiment of the present disclosure.

[0062] Here, "fp16" stands for half-precision floating-point, which follows the binary16 format in the IEEE754 standard and uses 16 bits of binary to represent floating-point numbers, including 1 sign bit, 5 exponent bits, and 10 decimal places (mantissa bits). "int" usually refers to the integer data type.

[0063] Therefore, the embodiment of the present disclosure proposes a method for enhancing the impact of key bits on the key path by setting the bit data with the smallest impact on accuracy to 0. This method highlights the role of data simplification in enhancing input probability sensitivity.

[0064] In summary, in view of the inherent correlation between the signal probability enhancement strategy and the location and structure of the critical path, the embodiments of the present disclosure propose the above two different input probability sensitivity enhancement strategies.

[0065] According to one or more embodiments, in an integrated circuit low power design, the disclosed embodiments are dedicated to determining which bits of input data have a significant impact on the signal probability of units within the critical path, thereby promoting targeted voltage reduction through strategic bit operations. To this end, a computational framework is designed to quantitatively evaluate the impact of the signal probability of each bit on the signal probability of the critical path. The method requires iteratively adjusting the signal probability of each input bit from 0.1 to 0.9 while maintaining the signal probability of all other bits. The input bit is at its baseline value. For each iteration, the absolute deviation of the signal probability of the critical path unit from its initial state is calculated and summarized. The cumulative deviation obtained through multiple, or 9 iterations, can be used as an influencing factor to quantify the impact of each bit on the critical path signal probability.

[0066] Therefore, the computational framework here includes the following steps:

[0067] (1) First, identify the critical paths in the digital circuit.

[0068] (2) Determine which input data bits may have a significant impact on the signal probability within the critical path.

[0069] (3) For each input bit, the signal probability is adjusted iteratively separately. In each iteration, the signal probability of the selected input bit is adjusted from 0.1 to 0.9, while the signal probabilities of other bits remain unchanged.

[0070] (4) For each iteration, the change in the critical path unit signal probability is calculated and compared with the initial state, and the absolute deviation of the critical path unit signal probability from its initial state is summarized.

[0071] (5) Cumulative deviation obtained through 9 iterations (because the signal probability is adjusted from 0.1 to 0.9, there are 9 possible values: 0.1, 0.2, ..., 0.9).

[0072] (6) Use the cumulative deviation as the influencing factor to quantify the impact of each bit on the critical path signal probability.

[0073] The baseline value refers to the original signal probability value of the input bit before any adjustment is made. The input bit is at its baseline value, which means that during the iteration process, except for the input bit currently being adjusted, all other input bits remain at their original signal probability values, that is, they do not change.

[0074] Therefore, the purpose of this computational framework is to find out which input bits’ signal probability changes have the greatest impact on the critical path of the circuit, so that the signal probabilities of these bits can be adjusted in a targeted manner to achieve the purpose of reducing the operating voltage while minimizing the impact on circuit performance.

[0075] Taking the multiplication and addition unit circuit of the systolic array as an example, after experiments, the present disclosure found that the 3rd and 4th bits have the greatest impact on the critical path at 0.9V; at 1.0V, it is the 0th and 1st bits. This analysis process is systematically applied to all input ports of the digital circuit, and finally the impact factors of all bits are calculated and compared. Subsequently, the bits with the highest impact factors will be designated for adjustment to optimize the voltage reduction work. This strategic approach not only emphasizes the key role of input signal probability variability in promoting voltage scaling, but also enhances the importance of interventions aimed at mitigating aging-induced performance degradation. In pursuit of optimizing voltage reduction, the signal probability of the identified target bits is systematically varied from 0.1 to 0.9. At the same time, for each iteration, the signal probability calculation tool is used to determine the input signal probability of each unit on the critical path, and these calculated signal probability values ​​are then input into the machine learning model to predict its corresponding aging delay.

[0076] The disclosed embodiment adopts the above-mentioned signal probability sensitivity enhancement method to obtain a significant relationship between aging delay, voltage and input signal probability. And there is a significant overlap area in the aging delay fluctuations near the normal operating voltage. This overlap means that the voltage and aging delay can be effectively modulated by adjusting the input signal probability. Detailed analysis of the curves under these voltages shows the behavior of the critical path aging delay in response to changes in the input signal probability.

[0077] Next, taking the multiplication and addition unit circuit of the systolic array as an example, by applying the method proposed in the embodiment of the present disclosure, the following is obtained: Figure 5The curve shown is the relationship curve between the delay of the circuit after aging of the systolic array multiplication and addition unit and the operating voltage and input signal probability. At 1.0V, the aging delay fluctuates around the initial value of 317.43ps, where the delay is the lowest (316.48ps) when SP=0.05 and the delay is the highest (321.98ps) when SP=0.95. At 0.9V, the aging delay fluctuates around the initial value of 320.40ps, and the delay is the lowest (316.59ps) and the highest delay is 321.88ps when the signal probabilities of the 3rd and 4th bits are SP=0.55 and SP4=0.8 respectively.

[0078] According to the method of the embodiment of the present disclosure, by changing the working state of the circuit from the initial point where the signal probability has not been adjusted to the lowest point of the curve at 0.9V, that is, from the initial signal probability of 1.0V to 0.9V, the 3rd and 4th signal probabilities are SP=0.55 and SP=0.8 respectively, the working voltage is reduced by 0.1V and the aging delay is optimized by 1ps, thereby reducing power consumption and optimizing performance.

[0079] Figure 5 The relationship between the aging delay of the systolic array multiplication-addition unit circuit and the operating voltage and signal probability (SP) is shown. The curves and data points in the figure represent the delay performance of the circuit after aging under different operating voltages and signal probabilities. Figure 5 The vertical axis is Delay after aging, and its unit is picosecond (PS). The horizontal axis is Voltage, and its unit is volt (V).

[0080] Figure 5 It is shown that by adjusting the signal probability and the operating voltage, the performance of the circuit can be optimized while reducing power consumption, especially in terms of aging delay. This optimization is of great significance for improving the energy efficiency and reliability of digital circuits.

[0081] In summary, the present disclosure introduces a groundbreaking integrated circuit low power design method to improve energy efficiency and ensure circuit performance. The main contents of the present disclosure and the corresponding beneficial effects include:

[0082] 1) A new computational framework is established to collaboratively determine the aging delay via the operating voltage and input signal probability, resulting in an efficient method to reduce the voltage and thus significantly reduce the circuit power consumption.

[0083] 2) By adjusting the signal input probability, the circuit calculation speed remains unchanged while reducing the operating voltage.

[0084] 3) An innovative critical path signal probability propagation model is proposed, which can accurately calculate the signal probability of the critical path unit based on the input signal probability, and ensure the accuracy of the calculation by in-depth analysis of the data transmission relationship in the netlist.

[0085] 4) Two strategies are proposed to enhance the sensitivity of the path to signal probability changes, expand the voltage adjustment space and optimize the effectiveness of the proposed method, while also providing insights for future circuit design optimization.

[0086] Therefore, the present disclosure provides a comprehensive method for optimizing circuit design by strategically adjusting input signal probability and critical path sensitivity enhancement strategy, and proposes a new idea for low-power and energy-saving circuit design.

[0087] It should be understood that in the embodiments of the present invention, the term "and / or" is only a description of the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0088] It is worth noting that, although the foregoing content has described the spirit and principle of the invention with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of various aspects does not mean that the features in these aspects cannot be combined, and such division is only for the convenience of expression. The invention is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the appended claims.

Claims

1. A low power consumption design method for digital integrated circuits, characterized in that: The design method realizes the low power consumption design target of the digital integrated circuit by adjusting the input signal probability of the digital integrated circuit.

2. The design method according to claim 1, characterized in that: The design method also includes achieving a low power consumption design goal of the digital integrated circuit based on the combined effect of the power supply voltage of the digital integrated circuit and the input signal probability on the aging delay of the digital integrated circuit.

3. The design method according to claim 2, characterized in that: While achieving the low power consumption design goal, it is ensured that the initial calculation speed index of the digital integrated circuit remains unchanged.

4. The design method according to claim 2, characterized in that: The design method includes establishing an input signal probability propagation model of a critical path of the digital integrated circuit, and measuring and calculating the input signal probability of each logic gate standard unit on the critical path.

5. The design method according to claim 4, characterized in that: An aging delay prediction model of the digital integrated circuit is constructed, and the aging delay of the digital integrated circuit is predicted according to the input signal probability of the standard cells on the critical path.

6. The design method according to claim 5, characterized in that: In the process of constructing the aging delay prediction model, the following steps are also included: Analyze the timing report file and netlist file generated by the digital integrated circuit synthesis, extracting the key path and data transmission relationship between each standard cell input terminal and the digital circuit input terminal at a preset specific voltage after aging, By establishing the probability transmission logic of input and output signals of standard cells, the input signal probability of each standard cell on the critical path is calculated.

7. The design method according to claim 4, characterized in that: The sensitivity of the critical path is enhanced to expand the overlapping area of ​​the aging delay curves of the digital integrated circuit under different power supply voltages, thereby expanding the power supply voltage adjustment space.

8. The design method according to claim 7, characterized in that: The method for enhancing the sensitivity of the critical path includes analyzing and comparing the effects of signal probabilities of different bits on the aging delay of each standard unit on the critical path, and determining at least two bits with the greatest effects.

9. The design method according to claim 7, characterized in that: The method for enhancing the sensitivity of the critical path also includes, when the influence ranges of the two bits with the greatest influence on the circuit aging delay overlap, giving up considering the bit with less influence on the accuracy.

10. A digital integrated circuit, characterized in that: The digital integrated circuit is designed by the digital integrated circuit low power consumption design method as claimed in claim 1.

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