General circuit logic diagram layout method

Abstract

The invention discloses a general circuit logic diagram layout method, which comprises the following steps of: S1, acquiring relative positions of all circuit diagram nodes of a circuit to be optimized and a connection relationship between the circuit diagram nodes and an output port and an input port through a circuit analysis module; s2, performing column positioning on each circuit diagram node according to the connection relationship between the circuit diagram node and the input port and the connection relationship between the circuit diagram node and the input port; s3, adding a virtual node to the to-be-optimized circuit, wherein the virtual node is arranged between two circuit diagram nodes which have a direct connection relationship, and a connection path at least crosses one column; s4, performing row positioning on each column of circuit diagram nodes according to the number of virtual nodes in the precursor nodes of the circuit diagram nodes; and S5, removing all the virtual nodes, and recovering the connection relationship between the circuit diagram nodes and the output port and the input port. The layout algorithm is not limited by a specific circuit, can be widely applied to the design of an analog circuit and a digital circuit, and simplifies the layout problem in the circuit design.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, in particular to a general circuit logic diagram layout method. Background Art

[0002] With the rapid development of electronic technology, analog circuits and digital circuits, as the core components of modern electronic equipment, have become increasingly complex and integrated. Engineers need to frequently deal with circuit diagrams containing a large number of components, interconnections, and logic levels during the design process, and effective circuit diagram display layout is essential for understanding the working principle of the circuit, conducting circuit analysis, troubleshooting, and thus improving design efficiency and shortening product launch cycles.

[0003] Traditional circuit diagram display layout methods have the limitation of visualization effect and information density: in the limited screen space, it is a challenge to balance the density of circuit diagram nodes and the amount of information required for design. Too concentrated placement of circuit diagram components may lead to a chaotic overall view, making it difficult to quickly identify the key paths and connections between components; too sparse layout may miss important details, making it more difficult to consult and understand. Summary of the invention

[0004] In view of the problem in the prior art that the traditional circuit diagram display layout method has a confusing overall view and is difficult to quickly identify the key paths and the connections between components, the present invention proposes a general circuit logic diagram layout method.

[0005] The technical solution of the present invention is to propose a general circuit logic diagram layout method, comprising:

[0006] Step S1: Obtaining the relative positions of all circuit diagram nodes of the circuit to be optimized and the connection relationship between the circuit diagram nodes and the output ports and input ports through the circuit analysis module;

[0007] Step S2: performing column positioning on each of the circuit diagram nodes according to the connection relationship between the circuit diagram node and the input port and the input port;

[0008] Step S3: adding a virtual node to the circuit to be optimized, wherein the virtual node is set between two circuit diagram nodes that are directly connected and whose connection path spans at least one column;

[0009] Step S4: performing row positioning for each column of the circuit diagram node according to the number of virtual nodes in the predecessor node of the circuit diagram node;

[0010] Step S5: remove all the virtual nodes, and restore the connection relationship between the circuit diagram nodes and the output ports and input ports.

[0011] Furthermore, the step S2 includes:

[0012] Step S201: setting the input port to the first column and the output port to the second to last column;

[0013] Step S202: starting from any input port, searching for successor nodes in sequence, and setting a candidate set for all successor nodes, wherein the value of the successor node in the candidate set is the value of the candidate set of the previous circuit diagram node connected to it plus 1;

[0014] Step S203: The column location value of the circuit diagram node is set according to the value in the corresponding candidate set.

[0015] Furthermore, the step S203 includes:

[0016] When the circuit diagram node has only one predecessor node, the column positioning value of the circuit diagram node is a value in the corresponding candidate set;

[0017] When the circuit diagram node has at least two predecessor nodes, the column positioning value of the circuit diagram node is the maximum value in the corresponding candidate set.

[0018] Further, the step S4 includes:

[0019] Step S401: Detecting the number of virtual nodes in the predecessor node of the circuit diagram node;

[0020] Step S402: when the number of the virtual nodes is 0, the row positioning value of the circuit diagram node is optimized according to the row positioning value of its predecessor node;

[0021] When the number of the virtual nodes is 1, the row positioning value of the circuit diagram node is set to the row positioning value of the virtual node;

[0022] When the number of the virtual nodes is at least 2, the row positioning value of the circuit diagram node is optimized according to the row positioning values ​​of all the virtual nodes.

[0023] Furthermore, the row location value of the circuit diagram node satisfies the calculation model:

[0024]

[0025] Among them, new_row is the row location value of the circuit diagram node, row i is the row number of the ith predecessor node of the circuit diagram node, and k is the number of predecessor nodes of the circuit diagram node.

[0026] Furthermore, the step S4 further includes:

[0027] Step S403: For any circuit diagram node that has no predecessor node or successor node, set its column to the next column of the output port, and arrange all circuit diagram nodes that have no predecessor node or successor node in sequence under this column.

[0028] Furthermore, the step S4 further includes:

[0029] Step S404: Obtain output ports of all circuit diagram nodes in the same column, and assign values ​​to all output ports in sequence according to a preset order;

[0030] Step S405: Calculate the port weight value of the output port of each of the circuit diagram nodes;

[0031] Step S406: Obtain the connection relationship between all circuit diagram nodes in the next column and the output port, calculate the sum of the port weight values ​​of the output ports connected thereto, and set the row positioning value of all circuit diagram nodes in the column according to the sum of the port weight values.

[0032] Furthermore, the calculation model of the port weight value is:

[0033]

[0034] Among them, port_weight (p,q) (i) is the port weight value of the output port numbered i in the pth row and the qth column, and port_num is the number of all output ports of the current circuit diagram node.

[0035] Compared with the prior art, the present invention has at least the following beneficial effects:

[0036] 1. Universality: The layout algorithm of the present invention is not limited to a specific type of circuit and can be widely applied to the design stage of analog circuits and digital circuits, greatly simplifying the layout problems in multi-field circuit design to cope with rapidly changing market and technical requirements;

[0037] 2. Flexibility and customizability: The present invention adopts a unique modular design concept, which divides the overall layout process into a basic framework and multiple independent and non-interdependent steps. Each step can operate as a separate functional unit. The non-coupling characteristics between the steps make this layout algorithm highly flexible and scalable;

[0038] 3. More friendly to engineers: The algorithm has the unique ability to handle nodes in the circuit diagram that have no predecessor and successor relationship. By rationally arranging such nodes, the entire circuit diagram can look neater and more orderly, which is beneficial for engineers to analyze the circuit and troubleshoot. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0040] Figure 1 It is a control flow chart of the whole invention;

[0041] Figure 2 It is a schematic diagram after the circuit diagram nodes are positioned in columns according to the present invention;

[0042] Figure 3 and Figure 4 They are respectively a schematic diagram and an effect diagram after adding a virtual node in the present invention;

[0043] Figure 5 It is a schematic diagram of the circuit diagram nodes after row positioning when the number of virtual nodes is 0 in the present invention;

[0044] Figure 6 It is a schematic diagram of the circuit diagram nodes after row positioning when the number of virtual nodes is 1 in the present invention;

[0045] Figure 7 It is a schematic diagram of the circuit diagram nodes after row positioning when there are at least 2 virtual nodes in the present invention;

[0046] Figure 8 It is a schematic diagram of row positioning according to port weight values ​​in the present invention. DETAILED DESCRIPTION

[0047] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0048] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.

[0049] The principle and structure of the present invention are described in detail below with reference to the accompanying drawings and embodiments.

[0050] Traditional circuit diagram display layout methods have the limitation of visualization effect and information density: in the limited screen space, it is a challenge to balance the density of circuit diagram nodes and the amount of information required for design. Too concentrated placement of circuit diagram components may lead to a chaotic overall view, making it difficult to quickly identify the key paths and connections between components; too sparse layout may miss important details, making it more difficult to consult and understand.

[0051] In view of the above problems, the present invention proposes a general circuit logic layout method, comprising:

[0052] Step S1: Obtaining the relative positions of all circuit diagram nodes of the circuit to be optimized and the connection relationship between the circuit diagram nodes and the output ports and input ports through the circuit analysis module;

[0053] Step S2: locating each circuit diagram node in a column according to the connection relationship between the circuit diagram node and the input port and the input port;

[0054] Step S3: adding a virtual node for the circuit to be optimized, where the virtual node is set between two circuit diagram nodes that are directly connected and whose connection path spans at least one column;

[0055] Step S4: performing row positioning for each column of the circuit diagram nodes according to the number of virtual nodes in the predecessor node of the circuit diagram node;

[0056] Step S5: remove all virtual nodes and restore the connection relationship between the circuit diagram nodes and the output ports and input ports.

[0057] See also Figure 1 , "circuit analysis, obtaining circuit diagram nodes and connection relationships" in the above flowchart is also step S1 in the above general circuit logic layout method;

[0058] In the above flowchart, “locating the columns of each circuit diagram node by connection relationship” is step S2 in the above circuit logic layout method;

[0059] “Adding virtual nodes” in the above flowchart is also step S3 in the above circuit logic layout method;

[0060] In the above flowchart, “optimizing the placement order of nodes in each column of the circuit diagram (all predecessor nodes are non-virtual nodes)”, “optimizing the placement order of nodes in each column of the circuit diagram (only one circuit diagram node in the predecessor node is a virtual node)”, “optimizing the placement order of nodes in each column of the circuit diagram (there are multiple virtual nodes in the predecessor node)”, “optimizing the placement order of independent nodes with neither predecessor nodes nor successor nodes”, and “optimizing the placement order of nodes in the circuit diagram considering the port weight value” are step S4 in the above circuit logic layout method;

[0061] “Remove virtual nodes, restore connection relationships, and start wiring” in the above flowchart is step S5 in the above circuit logic layout method;

[0062] based on Figure 1 From the flowchart shown, it can be seen that when optimizing the placement order of nodes in each column of the circuit diagram, the present invention respectively makes settings for the case based on the virtual node in the predecessor node, the case with neither predecessor node nor successor node, and the case of optimization based on the port weight value. The process of optimizing the placement of circuit diagram nodes in the above cases is independent of each other, and each step can operate as a separate functional unit. The non-coupling characteristics between the steps make this layout algorithm highly flexible and scalable.

[0063] The steps of the present invention are described below in conjunction with the accompanying drawings;

[0064] Step S1: Obtaining the relative positions of all circuit diagram nodes of the circuit to be optimized and the connection relationship between the circuit diagram nodes and the output ports and input ports through the circuit analysis module;

[0065] Here, step S1 is implemented by the circuit analysis module, and no additional introduction is given here;

[0066] Step S2: locating each circuit diagram node in a column according to the connection relationship between the circuit diagram node and the input port and the input port;

[0067] Here, the above step S2 can be divided into three steps, namely:

[0068] Step S201: set the input port to the first column and the output port to the second to last column;

[0069] Step S202: starting from any input port, searching for successor nodes in sequence, and setting a candidate set for all successor nodes, the value of the successor node in the candidate set is the value of the candidate set of the previous circuit diagram node connected to it plus 1;

[0070] Step S203: The column location value of the circuit diagram node is set according to the value in the corresponding candidate set.

[0071] Among them, step S203 has two situations according to the number of predecessor nodes, namely:

[0072] When a circuit diagram node has only one predecessor node, the column location value of the circuit diagram node is a value in the corresponding candidate set;

[0073] When a circuit diagram node has at least two predecessor nodes, the column positioning value of the circuit diagram node is the maximum value in the corresponding candidate set.

[0074] Attached Figure 2 The relative positions of all the circuit diagram nodes of the circuit to be optimized obtained by the circuit analysis module, and the connection relationship between the circuit diagram nodes and the output port and the input port, it can be seen that the circuit to be analyzed is arranged in a matrix form, with n columns of circuit diagram nodes;

[0075] Among them, the 0th column represents the input port of the circuit to be optimized, the n-1th column represents the output port of the circuit to be optimized, each rectangular box in the middle column 1 to the n-2th column represents a circuit diagram node, and the connection between the input port and the circuit diagram node, the connection between the output port and the circuit diagram node, and the connection between each circuit diagram node are used to represent the connection relationship between the input port, the output port, and the circuit diagram node;

[0076] In this article, the predecessor node refers to the node connected to the current circuit diagram node and close to the input port side, and the successor node refers to the node connected to the current circuit diagram node and close to the output port side;

[0077] If Figure 2 For node 4 in the circuit diagram, the nodes connected to it are node 3 and node 6. Here, node 3 is close to the input port side, so node 3 serves as the predecessor node of node 4, and node 6 is close to the output port side, so node 6 serves as the successor node of node 4.

[0078] The following is an explanation of step S201 in the present invention. Figure 2 , which has n columns of circuit diagram nodes, where the 0th column is the first column in step S201, and the n-1th column is the second to last column in step S201;

[0079] Step S202 is a process of setting a candidate set. Specifically, the process is as follows: starting from the 0th column, searching for successor nodes backward in sequence according to the connection relationship, and adding an element to the candidate set each time a successor node is found. The value of the element is the maximum value in the candidate set of the column location of the predecessor node plus 1;

[0080] like Figure 2 As shown, the search starts from node 0 and goes backwards. Here, the candidate set of column positioning of node 0 is set to {0}. The successor node of node 0 is node 3. Then, according to the logic in step S202, the candidate set of node 3 is set to {1}. The successor nodes are traversed backwards in sequence, and the candidate set of column positioning of node 4 is obtained to be {2}, the candidate set of column positioning of node 6 is obtained to be {3}, and the candidate set of column positioning of node 8 is obtained to be {4}.

[0081] After searching for node 0 in column 0, we start searching backward from the next node in column 0, that is, node 1. Since this is a new search process, the column positioning candidate set of node 1 is set to {0}. The successor node of node 1 is node 6. In the first search process, a column positioning candidate set {3} has been set for node 6. However, in the second search process, the column positioning candidate set of node 6 is {1}. At this time, the current candidate set is directly added to the candidate set of the first search, and the candidate set for column positioning of node 6 is {3, 1}. Similarly, the column marking candidate set of the next node 8 is {4, 2}.

[0082] After all nodes are found according to the above method, step S202 is completed, and then step S203 needs to be executed to locate the column of each node;

[0083] According to the number of elements in the candidate set of each node, we can know how many predecessor nodes the node has. For example, for node 6, its candidate set is {3, 1}, from which we can know that node 6 has 2 predecessor nodes. Similarly, according to the candidate set of node 3 is {1}, we can know that node 3 has 1 predecessor node.

[0084] The first case of step S203 in the present invention is the case where there is only one predecessor node. At this time, the column positioning value of the circuit diagram node is set to the value of the corresponding candidate set. For example, for node 3, its subsequent set has only one element 1, so the final column positioning value of node 3 is 1. Similarly, the final column positioning value of node 0 is 0.

[0085] The second case is the case with at least two predecessor nodes. At this time, the column positioning value of the circuit diagram node is set to the maximum value in the corresponding subsequent set. For example, for node 6, its candidate set is {3, 1}, which has two elements 3 and 1. At this time, the maximum value in the candidate set is 3, so the final column positioning value of node 6 is 3. Similarly, the final column positioning value of node 8 is 4.

[0086] After executing the above step S2, it is necessary to add virtual nodes to the circuit to be optimized so as to locate the nodes in the circuit diagram. In this case, it is necessary to execute step S3;

[0087] Step S3: adding a virtual node for the circuit to be optimized, where the virtual node is set between two circuit diagram nodes that are directly connected and whose connection path spans at least one column;

[0088] See also Figure 3It can be seen that the nodes with direct connection relationships are node 0 and node 3, node 3 and node 4, node 4 and node 6, node 6 and node 8, node 1 and node 6, node 2 and node 5, and node 5 and node 7;

[0089] Further screening two circuit diagram nodes whose connection paths span at least one column, we can get three combinations, namely, node 1 and node 6 span the first column and the second column, node 2 and node 5 span the first column, and node 5 and node 7;

[0090] When adding a virtual node, you need to add the virtual node in the column you span, such as Figure 3 It can be seen that the added virtual nodes are 1-1, 1-2, and 2-1 (here, multiple columns are actually spanned between node 5 and node 7, node 5 is the 2nd column, node 7 is the n-1th column, and the attached Figure 3 The middle column is omitted for ease of understanding. Therefore, more than one virtual node may be actually added between node 5 and node 7. Figure 3 not indicated).

[0091] After completing the above process of adding virtual nodes, it is necessary to perform row positioning on the circuit diagram nodes, and step S4 needs to be executed at this time;

[0092] Step S4: performing row positioning for each column of the circuit diagram nodes according to the number of virtual nodes in the predecessor node of the circuit diagram node;

[0093] Wherein, the above step S4 includes:

[0094] Step S401: Detect the number of virtual nodes in the predecessor node of the circuit diagram node;

[0095] Step S402: when the number of virtual nodes is 0, the row positioning value of the circuit diagram node is optimized according to the row positioning value of its predecessor node;

[0096] When the number of virtual nodes is 1, the row positioning value of the circuit diagram node is set to the row positioning value of the virtual node;

[0097] When the number of virtual nodes is at least 2, the row positioning value of the circuit diagram node is optimized according to the row positioning values ​​of all virtual nodes.

[0098] Among them, the row positioning value of the above circuit diagram node satisfies the calculation model:

[0099]

[0100] Among them, new_row is the row location value of the circuit diagram node, row i is the row number of the i-th predecessor node of the circuit graph node, and k is the number of predecessor nodes of the circuit graph node.

[0101] The above step S402 is divided into three cases, namely, the number of virtual nodes in the predecessor node of the circuit diagram node is 0, the number of virtual nodes in the predecessor node of the circuit diagram node is 1, and the number of virtual nodes in the predecessor node of the circuit diagram node is multiple;

[0102] In the first case, all predecessor nodes of the circuit diagram node are non-virtual nodes. Figure 5 Take the case of the first example, there are three predecessor nodes of node 6, namely node 3, node 4 and node 5. The row positioning value corresponding to node 3 is 0, the row positioning value corresponding to node 4 is 1, and the row positioning value corresponding to node 5 is 2. Here, node 3 is set as the first predecessor node, node 4 is the second predecessor node, and node 5 is the third predecessor node;

[0103] Substituting into the above calculation model, we can get: new_row = (0 + 1 + 2) / 3 = 1;

[0104] That is, after the above optimization scheme, the row positioning value of node 6 becomes 1, and the re-optimized circuit diagram is Figure 5 Right part.

[0105] For the second case, at this time, the predecessor node has only one virtual node, and the row positioning value of the circuit diagram node is directly set to the row positioning value of the virtual node. There is no need to determine a new row positioning value through the above calculation model. The row positioning value of the virtual node can be determined directly to determine the row positioning value of the circuit diagram node.

[0106] by Figure 6 For example, node 4 is the node to be optimized, and its predecessor nodes are node 3 and node 1-2. Here, node 1-2 is a virtual node, and there is only one virtual node in the predecessor node of node 4. Therefore, the row positioning value of node 4 is directly set to be consistent with the row positioning value of the virtual node 1-2. Here, the row positioning value of the virtual node 1-2 is 1, so the row positioning value of node 4 after optimization is also set to 1. The re-optimized circuit diagram is Figure 6 Right part.

[0107] For the third case, the predecessor node of the circuit diagram node has multiple virtual nodes. Figure 7 For example, there are three predecessor nodes of node 6, namely virtual node 0-2, virtual node 1-2, and node 5. There are two virtual nodes among the predecessor nodes of node 6. Then it needs to be divided into the third case. At this time, it is necessary to follow the above calculation model and optimize according to the row positioning value of the virtual node;

[0108] Here, the row positioning value of virtual node 0-2 is 0, and the row positioning value of virtual node 1-2 is 1. Here, virtual node 0-2 is set as the first predecessor node, and virtual node 1-2 is set as the second predecessor node;

[0109] Substituting into the above calculation model, we can get: new_row = (0 + 1) / 2 = 0.5;

[0110] The row positioning value calculated here is less than 1 and cannot be assigned to the first row. Therefore, the row positioning value of node 6 is still set to 0. The re-optimized circuit diagram is Figure 7 Right part.

[0111] Furthermore, the above step S4 also includes:

[0112] Step S403: For any circuit diagram node that has no predecessor node or successor node, set its column to the next column of the output port, and arrange all circuit diagram nodes that have no predecessor node or successor node in sequence under this column.

[0113] The circuit diagram nodes without predecessor nodes and successor nodes are independent nodes, and there is no connection relationship between them. In order to optimize the layout of the circuit diagram, the present invention places all independent nodes in the same column and arranges them in sequence from row 0 downwards, such as Figure 2 As shown, node 9 and node 10 are both independent nodes, which do not have any predecessor nodes and successor nodes. Therefore, node 9 and node 10 are both placed in the nth column, that is, the next column of the output port, and arranged downward from row 0, where node 9 is in row 0 and node 10 is in row 1.

[0114] Furthermore, the present invention is also provided with a scheme for optimizing the row positioning value according to the port weight value, which comprises:

[0115] Step S404: Obtain output ports of all circuit diagram nodes in the same column, and assign values ​​to all output ports in sequence according to a preset order;

[0116] Step S405: Calculate the port weight value of the output port of each circuit diagram node;

[0117] Step S406: Obtain the connection relationship between all circuit diagram nodes and output ports in the next column, calculate the sum of the port weight values ​​of the output ports connected thereto, and set the row positioning values ​​of all circuit diagram nodes in the column according to the sum of the port weight values.

[0118] Here, the calculation model of the port weight value is:

[0119]

[0120] Among them, port_weighit(p,q) (i) is the port weight value of the output port numbered i in the pth row and the qth column, and port_num is the number of all output ports of the current circuit diagram node.

[0121] by Figure 8 Take the case of node 1 in the qth column and the 0th row as an example. Node 1 has three output ports. Here, the three output ports are assigned values ​​from top to bottom, and the values ​​are 1, 2, and 3 respectively. The values ​​assigned here are the serial numbers in the above calculation model.

[0122] Then, we search downwards in order for node 2, which has an output port and assigns it a value of 1;

[0123] For node 3, it has two output ports, which are assigned values ​​of 1 and 2 respectively;

[0124] The above step corresponds to step S404. After the assignment is completed, the port weight value of each output port needs to be calculated, which is step S405. The calculation is performed according to the above calculation model.

[0125] For node 1, which is in row 0 and column q, the port weight value of the output port of node 1 assigned with a value of 1 can be obtained according to the above calculation model:

[0126]

[0127] The port weight value obtained through the above calculation is 1.25;

[0128] According to the above calculation model, the port weight values ​​of all output ports can be calculated. The port weight values ​​of the three output ports of node 1 are 1.25, 1.5 and 1.75 respectively;

[0129] The port weight value of the output port of node 2 is 2.5;

[0130] The port weight values ​​of the two output ports of node 3 are 3.33 and 3.36 respectively;

[0131] The process of calculating the port weight value is also the above step S405. After the above step S405 is executed, it is necessary to continue to execute step S406;

[0132] It first obtains the connection relationship between all circuit diagram nodes and output ports in the next column, that is, Figure 8 The q+1th column in the graph has nodes 4, 5, and 6. It can be obtained that node 4 is connected to the second output port of node 1 (corresponding port weight value is 1.5) and the second output port of node 3 (corresponding port weight value is 3.66).

[0133] Node 5 is connected to the first output port of node 1 (corresponding port weight value is 1.25) and the output port of node 2 (corresponding port weight value is 2.5).

[0134] Node 6 is connected to the third output port of node 1 (corresponding port weight value is 1.75) and the first output port of node 3 (corresponding port weight value is 3.33).

[0135] Then, it is necessary to set the row positioning value for the circuit diagram nodes in the column according to the sum of the port weight values. According to the above connection relationship, the sum of the port weight values ​​corresponding to the output port connected to node 4 is 5.16, the sum of the port weight values ​​corresponding to the output port connected to node 5 is 3.75, and the sum of the port weight values ​​corresponding to the output port connected to node 6 is 5.08;

[0136] Then, according to the sum of the port weight values, they are arranged in ascending order. Then, node 5 can be set in row 0, node 6 in row 1, and node 4 in row 2.

[0137] Similarly, here it can also be set according to the average value of the port weight value. According to the port weight values ​​calculated above, it can be seen that the average value of the port weight value of node 4 is 2.58, the average value of the port weight value of node 5 is 1.875, and the average value of the port weight value of node 6 is 2.54. The above arrangement can also be obtained in order from small to large.

[0138] The node positions and connections before optimization are as follows Figure 8 As shown in the left part, the optimized node placement and connection are Figure 8 As shown in the right part, Figure 8 It can be seen that the total number of intersections of all the connecting lines before the placement optimization is 6, and the number of intersections is reduced to 4 after the optimization, which means that the present invention simplifies the layout of the circuit.

[0139] Step S5 is a step of removing the virtual node and restoring the connection, which can be implemented by the circuit analysis module, so it will not be described in detail.

[0140] Combined with the above overall layout method, it can be seen that the present invention has the following beneficial effects:

[0141] 1. Universality: The layout algorithm of the present invention is not limited to a specific type of circuit and can be widely applied to the design stage of analog circuits and digital circuits, greatly simplifying the layout problems in multi-field circuit design to cope with rapidly changing market and technical requirements;

[0142] 2. Flexibility and customizability: The present invention adopts a unique modular design concept, which divides the overall layout process into a basic framework and multiple independent and non-interdependent steps. Each step can operate as a separate functional unit. The non-coupling characteristics between the steps make this layout algorithm highly flexible and scalable;

[0143] 3. More friendly to engineers: The algorithm has the unique ability to handle nodes in the circuit diagram that have no predecessor and successor relationship. By rationally arranging such nodes, the entire circuit diagram can look neater and more orderly, which is beneficial for engineers to analyze the circuit and troubleshoot.

[0144] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A general circuit logic diagram layout method, characterized in that: include: Step S1: Obtaining the relative positions of all circuit diagram nodes of the circuit to be optimized and the connection relationship between the circuit diagram nodes and the output ports and input ports through the circuit analysis module; Step S2: performing column positioning on each of the circuit diagram nodes according to the connection relationship between the circuit diagram node and the input port and the input port; Step S3: adding a virtual node to the circuit to be optimized, wherein the virtual node is set between two circuit diagram nodes that are directly connected and whose connection path spans at least one column; Step S4: performing row positioning for each column of the circuit diagram node according to the number of virtual nodes in the predecessor node of the circuit diagram node; Step S5: remove all the virtual nodes, and restore the connection relationship between the circuit diagram nodes and the output ports and input ports.

2. The general circuit logic diagram layout method according to claim 1, characterized in that: The step S2 comprises: Step S201: setting the input port to the first column and the output port to the second to last column; Step S202: starting from any input port, searching for successor nodes in sequence, and setting a candidate set for all successor nodes, wherein the value of the successor node in the candidate set is the value of the candidate set of the previous circuit diagram node connected to it plus 1; Step S203: The column location value of the circuit diagram node is set according to the value in the corresponding candidate set.

3. The general circuit logic diagram layout method according to claim 2, characterized in that: The step S203 includes: When the circuit diagram node has only one predecessor node, the column positioning value of the circuit diagram node is a value in the corresponding candidate set; When the circuit diagram node has at least two predecessor nodes, the column positioning value of the circuit diagram node is the maximum value in the corresponding candidate set.

4. The general circuit logic diagram layout method according to claim 1, characterized in that: The step S4 comprises: Step S401: Detecting the number of virtual nodes in the predecessor node of the circuit diagram node; Step S402: when the number of the virtual nodes is 0, the row positioning value of the circuit diagram node is optimized according to the row positioning value of its predecessor node; When the number of the virtual nodes is 1, the row positioning value of the circuit diagram node is set to the row positioning value of the virtual node; When the number of the virtual nodes is at least 2, the row positioning value of the circuit diagram node is optimized according to the row positioning values ​​of all the virtual nodes.

5. The general circuit logic diagram layout method according to claim 4, characterized in that: The row positioning value of the circuit diagram node satisfies the calculation model: Among them, new_row is the row location value of the circuit diagram node, row i is the row number of the ith predecessor node of the circuit diagram node, and k is the number of predecessor nodes of the circuit diagram node.

6. The general circuit logic diagram layout method according to claim 4, characterized in that: The step S4 further comprises: Step S403: For any circuit diagram node that has no predecessor node or successor node, set its column to the next column of the output port, and arrange all circuit diagram nodes that have no predecessor node or successor node in sequence under this column.

7. The general circuit logic diagram layout method according to claim 4, characterized in that: The step S4 further comprises: Step S404: Obtain output ports of all circuit diagram nodes in the same column, and assign values ​​to all output ports in sequence according to a preset order; Step S405: Calculate the port weight value of the output port of each of the circuit diagram nodes; Step S406: Obtain the connection relationship between all circuit diagram nodes in the next column and the output port, calculate the sum of the port weight values ​​of the output ports connected thereto, and set the row positioning value of all circuit diagram nodes in the column according to the sum of the port weight values.

8. The general circuit logic diagram layout method according to claim 7, characterized in that: The calculation model of the port weight value is: Among them, port_weight (p,q) (i) is the port weight value of the output port numbered i in the pth row and the qth column, and port_num is the number of all output ports of the current circuit diagram node.

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