A Two-Dimensional Sketch Full-Intersection Acceleration Method, System, Computer Device, and Computer Program Product
By building a bounding box and space division index structure, the full interleave process of two-dimensional sketches is optimized, and the problem of high time complexity in traditional methods is solved, achieving more efficient interleave calculation and improving user experience.
Patent Information
- Application Number
- CN202510294780.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-13
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2045-03-13
AI Technical Summary
When the number of voxels is large in the two-dimensional sketch, the traditional traversal interleaving method leads to high complexity in the solution time and poor user experience.
Build a bounding box and establish a spatial division index structure, perform interception calculations through quad-tree and hierarchical surrounding body structure, and optimize the interception process.
The speed and user experience of full interchange of two-dimensional sketches have been improved, unnecessary computational volume has been reduced, and the efficiency of interchange is improved.
Smart Images
Figure CN119810243B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of computer graphics processing, and particularly relates to a method, system, computer device and computer program product for accelerating the full intersection of two-dimensional sketches. Background Art
[0002] Solving the intersections between voxels in a two-dimensional sketch is often used for calculating the minimum enclosed region, clipping and extending, etc. When the number of voxels in a two-dimensional sketch is large, as the number of voxels increases, the traditional traversal intersection method will increase exponentially with the increase in the number of voxels. The time complexity of solving the intersections between all voxels is n^2. In software such as CAD, the above problem makes users wait for a long time when they need to perform intersection calculations on all voxels in a two-dimensional sketch, resulting in a poor experience.
[0003] Therefore, there is an urgent need for a more efficient method for full intersection of voxels in a two-dimensional sketch to improve the full intersection speed and user experience. Summary of the Invention
[0004] In view of this, embodiments of this application provide a method, system, computer device and computer program product for accelerating the full intersection of two-dimensional sketches to achieve more efficient full intersection of two-dimensional sketches and improve the user experience.
[0005] The first aspect of the embodiments of this application provides a method for accelerating the full intersection of two-dimensional sketches, including:
[0006] Constructing a first bounding box for a first voxel in the target two-dimensional sketch;
[0007] When the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch does not meet a preset threshold, performing a first intersection calculation on the second voxels and the first bounding box in the target two-dimensional sketch to obtain a first intersection result;
[0008] Establishing a spatial partitioning index structure for the first bounding box, where the spatial partitioning index structure includes an index of the first bounding box;
[0009] Performing a second intersection calculation on each target bounding box in the first bounding box, the bounding boxes in the index of the target bounding box, and the bounding boxes in the parent index of the index to obtain a second intersection result.
[0010] In an implementation of the first aspect, establishing the spatial partitioning index structure for the first bounding box includes:
[0011] Recursively partitioning the plane space of the target two-dimensional sketch into a quadtree structure according to a preset step size and a preset partitioning threshold, and assigning target index information to each piece of target space obtained by the partitioning;
[0012] The target index information includes the target index of the target space and the index of the parent space of the target space; in the case where the target space is not the smallest partition space, the target index information further includes the indices of the sub-spaces of the target space.
[0013] For each target bounding box in the first bounding box, use the index of the smallest partition space of the target bounding box as the index of the target bounding box.
[0014] Delete the paths in the quadtree structure that do not contain bounding boxes.
[0015] In one implementation manner of the first aspect, the building of the spatial partition index structure for the first bounding box includes:
[0016] For each target bounding box in the first bounding box, find the corresponding spatial index of the target bounding box and add it to the index tree.
[0017] In one implementation manner of the first aspect, the method further includes:
[0018] When the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch satisfies a preset threshold, construct a hierarchical bounding volume structure for the first bounding box.
[0019] Perform a first intersection calculation on the second voxels and the hierarchical bounding volume structure to obtain a first intersection result.
[0020] In one implementation manner of the first aspect, the constructing of the hierarchical bounding volume structure for the first bounding box when the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch satisfies a preset threshold includes:
[0021] When the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch is greater than or equal to 2, construct a hierarchical bounding volume structure for the first bounding box based on the surface area heuristic algorithm.
[0022] In one implementation manner of the first aspect, before constructing the first bounding box for the first voxels in the target two-dimensional sketch, it further includes:
[0023] Obtain all the voxels in the target two-dimensional sketch;
[0024] Divide all the voxels into first voxels and second voxels according to the type and geometric data of the voxels.
[0025] In one implementation of the first aspect, before establishing the spatial partitioning index structure for the first bounding box, the following steps are further included:
[0026] During the first intersection calculation process, if the first bounding box to be split is split for the first time, then split the first bounding box and store the information of the sub-bounding boxes obtained by splitting the first bounding box into the acceleration cache.
[0027] The method further includes:
[0028] During the first intersection calculation or the second intersection calculation process, if the first bounding box to be split is not split for the first time, then obtain the information of the sub-bounding boxes of the first bounding box from the acceleration cache.
[0029] The second aspect of the embodiments of the present application provides a two-dimensional sketch full-intersection acceleration system, including:
[0030] A bounding box construction module, configured to construct a first bounding box for the first voxel in the target two-dimensional sketch;
[0031] A first intersection module, configured to perform a first intersection calculation on the second voxel and the first bounding box in the target two-dimensional sketch to obtain a first intersection result when the ratio of the number of the first voxels to the number of the second voxels in the target two-dimensional sketch does not meet a preset threshold;
[0032] A spatial partitioning index module, configured to establish a spatial partitioning index structure for the first bounding box, where the spatial partitioning index structure includes the index of the first bounding box;
[0033] A second intersection module, configured to perform a second intersection calculation on each target bounding box in the first bounding box, the bounding box in the index of the target bounding box, and the bounding box in the parent index of the index to obtain a second intersection result.
[0034] The third aspect of the embodiments of the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the method described in the first aspect are implemented.
[0035] The fourth aspect of the embodiments of the present application provides a computer program product, including a computer program. When the computer program is run, the method described in the first aspect is executed.
[0036] The beneficial effect of the first aspect of the embodiment of the present application is as follows: By constructing a first bounding box for the first voxel in the target two-dimensional sketch, and when the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch does not meet the preset threshold, performing a first intersection calculation on the second voxels and the first bounding box in the target two-dimensional sketch to obtain a first intersection result; then establishing a spatial partitioning index structure for the first bounding box, where the spatial partitioning index structure includes the index of the first bounding box; performing a second intersection calculation on each target bounding box in the first bounding box, the bounding boxes in the index of the target bounding box, and the bounding boxes in the parent index of the index to obtain a second intersection result, achieving more efficient full intersection of two-dimensional sketches and improving the user experience.
[0037] It can be understood that the beneficial effects of the above second aspect to the fourth aspect can refer to the relevant descriptions in the above first aspect and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0039] Figure 1 is a schematic flowchart of the implementation of the full intersection acceleration method for two-dimensional sketches provided by the embodiment of the present application;
[0040] Figure 2 is a schematic flowchart of the implementation of the full intersection acceleration method for two-dimensional sketches provided by the embodiment of the present application;
[0041] Figure 3 is a schematic diagram of the full intersection acceleration system for two-dimensional sketches provided by the embodiment of the present application;
[0042] Figure 4 is a schematic diagram of the computer device provided by the embodiment of the present application;
[0043] Figure 5 is a schematic diagram of the computer program product provided by the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0044] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.
[0045] It should be understood that, as used in the specification of this application and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.
[0046] It should also be understood that the term "and / or" as used in the specification of this application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0047] As used in the specification of this application and the appended claims, the term "if" may be construed, depending on the context, as "when" or "once" or "in response to determining" or "in response to detecting". Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be construed, depending on the context, as meaning "once determined" or "in response to determining" or "once [the described condition or event] is detected" or "in response to detecting [the described condition or event]".
[0048] In addition, in the description of the specification of this application and the appended claims, the terms "first", "second", "third", etc. are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.
[0049] Reference to "one embodiment" or "some embodiments" or the like described in the specification of this application means that a particular feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc., which appear in different places in this specification, are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way.
[0050] The embodiment of the present application provides a method for full intersection of two-dimensional sketches, which is used to achieve efficient full intersection between voxels in two-dimensional sketches. The method for full intersection of two-dimensional sketches provided by the present application constructs a first bounding box for the first voxel in the target two-dimensional sketch, and when the ratio of the number of the second voxels to the number of the first voxels in the target two-dimensional sketch does not meet the preset threshold, performs a first intersection calculation on the second voxels and the first bounding box in the target two-dimensional sketch to obtain a first intersection result; then establishes a spatial partition index structure for the first bounding box, and the spatial partition index structure includes the index of the first bounding box; performs a second intersection calculation on each target bounding box in the first bounding box, the bounding boxes in the index of the target bounding box, and the bounding boxes in the parent index of the index to obtain a second intersection result, so as to achieve more efficient full intersection of two-dimensional sketches.
[0051] The method for full intersection of two-dimensional sketches provided by the embodiment of the present application can be applied to computer devices such as desktop computers, notebooks, palmtop computers, cloud servers, mobile phones, tablet computers, wearable devices, vehicle-mounted devices, augmented reality (AR) / virtual reality (VR) devices, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), etc. The embodiment of the present application does not impose any restrictions on the specific types of computer devices.
[0052] As Figure 1 shown, the first aspect of the embodiment of the present application provides a method for accelerating full intersection of two-dimensional sketches, including:
[0053] Step S11, constructing a first bounding box for the first voxel in the target two-dimensional sketch.
[0054] In applications, the target two-dimensional sketch is a two-dimensional sketch that needs to perform full intersection (intersect all voxels in the two-dimensional sketch). By constructing a bounding box for the first voxel, the representation of the voxel can be simplified, and by representing the voxel with a bounding box, the speed of voxel intersection can be increased. In applications, the first bounding box can be an axis-aligned bounding box AABB (Axis-Aligned Bounding-Box), a spherical bounding box, an OBB (Oriented Bounding Box), etc. It can be understood that the first voxel is a voxel type for which a bounding box can be constructed. The first bounding box constructed for each first voxel can be one or more.
[0055] Step S12, when the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch does not meet the preset threshold, perform a first intersection calculation on the second voxels and the first bounding box in the target two-dimensional sketch to obtain a first intersection result.
[0056] In an application, the first voxels are voxels that can construct a bounding box, and the second voxels are voxels that cannot construct a bounding box. When the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch does not meet the preset threshold, perform a first intersection calculation on each second voxel and each first bounding box of each first voxel in the target two-dimensional sketch to obtain a first intersection result.
[0057] Step S13, establish a spatial partitioning index structure for the first bounding box, where the spatial partitioning index structure includes an index of the first bounding box.
[0058] Step S14, perform a second intersection calculation on each target bounding box in the first bounding box, the bounding box in the index of the target bounding box, and the bounding box in the parent index of the index to obtain a second intersection result.
[0059] In an application, by performing an intersection calculation on each target bounding box in each first bounding box, the bounding box in the index of the target bounding box, and the bounding box in the parent index of the index, it is possible to avoid performing an intersection calculation on the bounding boxes in the sibling voxel index and its child voxel index, accelerating the intersection calculation efficiency. For example, if the current voxel has an intersection with the bounding box of a certain parent voxel, then continue to query the bounding boxes of the child voxels of the parent voxel, which can avoid unnecessary calculations and reduce the amount of calculation for each intersection. If two voxels are located in different parts of the space, their bounding boxes will not have an intersection, thus skipping those voxel regions that do not require calculation.
[0060] In one embodiment, step S13, establishing a spatial partitioning index structure for the first bounding box, includes:
[0061] Step S131, recursively partition the planar space of the target two-dimensional sketch into a quadtree structure according to a preset step size and a preset partitioning threshold, and allocate target index information to each piece of target space obtained by the partitioning.
[0062] In an application, use a preset step size (or resolution) to divide the planar space of the target two-dimensional sketch into small pieces of uniform size. When the number of objects in a certain area exceeds the preset partitioning threshold or the side length of the area is greater than the preset partitioning threshold, the area will be further divided.
[0063] Step S132, the target index information includes the target index of the target space and the index of the parent space of the target space; when the target space is not the smallest partition space, the target index information further includes the indexes of the subspace of the target space.
[0064] In the application, in the quadtree structure constructed by partitioning the plane space of the target two-dimensional graph, except for the root node and the leaf nodes, the target space nodes all have parent nodes and child nodes. Therefore, their index information includes the index of the target space of their parent node and the index of the target space of their child nodes; the target space of the root node (the entire plane space) has no parent target space, and its target index information includes the index of the target space of its child nodes; the target space of the leaf node has no child target space, and its target index information includes the index of the target space of its parent node.
[0065] Step S133, for each target bounding box in the first bounding box, use the index of the smallest partition space of the target bounding box as the index of the target bounding box.
[0066] In the application, the smallest partition space is actually a kd-tree (K-Dimensional Tree), and the leaf nodes of this kd-tree are the target bounding boxes.
[0067] Step S134, delete the paths in the quadtree structure that do not contain bounding boxes.
[0068] In the application, by deleting the paths in the quadtree structure that do not contain bounding boxes, the recursive depth is reduced.
[0069] In the application, the root space is a two-dimensional Axis Aligned space with the maximum threshold side length. If the depth of the constructed tree is k, it means the number of space partition layers is k. Therefore, the time complexity of traversing all the partitioned spaces is equal to the dimension of the current number of partitioned spaces; and the partitioning method is quadripartition, so the number is at least 4^k.
[0070] In one embodiment, the establishing the spatial partitioning index structure for the first bounding box includes:
[0071] For each target bounding box in the first bounding box, find the corresponding spatial index of the target bounding box and add it to the index tree.
[0072] In the application, find the corresponding spatial index according to the target bounding box and add it to the index tree to construct the spatial partitioning index structure, so as to reduce the construction time complexity from O(4^k) to O(kn), where k is the maximum depth of the index tree and n is the number of bounding boxes added to the index tree construction.
[0073] Such as Figure 2As shown, in one embodiment, the method further includes:
[0074] Step S15, when the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch satisfies a preset threshold, construct a hierarchical bounding volume structure for the first bounding box.
[0075] Step S16, perform a first intersection calculation on the second voxel and the hierarchical bounding volume structure to obtain a first intersection result.
[0076] In application, when the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch satisfies a preset threshold, by constructing a hierarchical bounding volume structure, BVH (Bounding Volume Hierarchy), for the first bounding box, and then performing a first intersection calculation on the second voxel and the hierarchical bounding volume structure, partial intersection calculations of all bounding boxes in the second voxel and the BVH structure are filtered. Through the hierarchical structure of the BVH, the intersection calculation will first attempt to intersect with the root node bounding box of the hierarchical bounding volume structure of the first voxel. If the intersection fails, then the bounding boxes of the entire subtree and all its child nodes can be excluded. This greatly reduces the number of bounding boxes that need to be calculated.
[0077] In application, when the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch does not satisfy the preset threshold, no hierarchical bounding volume construction is performed to avoid the computational cost of hierarchical bounding volume construction being greater than the computational cost of filtered intersection calculation.
[0078] In one embodiment, the step S15, when the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch satisfies a preset threshold, construct a hierarchical bounding volume structure for the first bounding box, includes:
[0079] Step S151, when the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch is greater than or equal to 2, construct a hierarchical bounding volume structure for the first bounding box based on the surface area heuristic algorithm.
[0080] In application, constructing a hierarchical bounding volume structure for the first bounding box based on the surface area heuristic algorithm SAH (Surface Area Heuristic) includes the following steps:
[0081] Initial partitioning: Start constructing with all bounding boxes as the root node.
[0082] Recursive splitting: For all bounding boxes in the current node, try different splitting schemes (such as cutting at different positions along the x and y axes).
[0083] Use SAH to calculate the cost of each splitting scheme and select the one with the lowest cost. The cost model of SAH takes into account the traversal cost: the fixed cost of accessing a node each time; the intersection test cost: the cost of performing intersection tests on all primitives in the leaf node; the splitting surface area: the sum of the surface areas of the bounding volumes of the two newly created child nodes, etc. The total cost where the total cost represents the expected cost of accessing and processing a node and all its child nodes, represents the basic cost of accessing an internal node, represents the probability that the ray hits the i-th child node, is the cost of performing an intersection test with the bounding box of the i-th node For leaf nodes, this is usually the cost of performing intersection tests on all primitives within the node; for internal nodes, it is the cost of further recursion; N is the number of child nodes, which is usually 2 in the case of a binary tree.
[0084] According to the selected splitting scheme, distribute the bounding boxes to the left and right child nodes.
[0085] If the number of bounding boxes in a certain child node exceeds a predetermined threshold, repeat the above process; otherwise, mark the node as a leaf node.
[0086] When the number of bounding boxes contained in a node is less than a certain threshold or no better splitting can be found, stop splitting and mark the node as a leaf node.
[0087] In one embodiment, before constructing the first bounding box for the first voxel in the target two-dimensional sketch in step S11, it further includes:
[0088] Step S101, obtain all voxels in the target two-dimensional sketch.
[0089] Step S102, divide all the voxels into the first voxels and the second voxels according to the type and geometric data of the voxels.
[0090] In an application, the voxel type, its bounding box construction, and the splitting method are as follows:
[0091] Line: The line has an infinite length and no bounding and construction are performed;
[0092] Line segment: If the line segment is horizontal or vertical, taking the vertical line segment as an example, the side length of the bounding box in the perpendicular direction of the line segment is set to a minimum precision threshold, and the side length of the bounding box in the direction of the line segment is equal to the length of the line segment; if it is a general line segment, the x and y coordinates of the lower left corner of the bounding box are the minimum values of the x and y coordinates of the two endpoints of the line segment, and the x and y coordinates of the upper right corner of the bounding box are the maximum values of the x and y coordinates of the two endpoints of the line segment; when the bounding box of a horizontal or vertical line segment is split, it can be divided into two equal parts along the direction of the line segment; when a general line segment is split, it is equivalent to reconstructing two bounding boxes with the midpoint and two endpoints of the line segment;
[0093] Circle: Calculate the four tangent points of the circle and the horizontal and vertical lines, and the bounding box can be constructed with the minimum and maximum values of the x and y coordinates of the four tangent points; when splitting, the four tangent points are combined before and after to form the bounding boxes of four arcs respectively, and the splitting of the bounding box of the arc refers to the direct splitting part of the bounding box of the arc;
[0094] Arc: Judge the span of the arc. If it does not cross a single quadrant with the center of the circle as the origin, the minimum and maximum values of the x and y coordinates of the starting point and the ending point respectively form the two endpoints of the bounding box, and the splitting of the bounding box can refer to the splitting of the general line segment, denoted as direct splitting; if the span of the arc crosses a single quadrant with the center of the circle as the origin, record the horizontal / vertical tangent points passed through and take the minimum and maximum values together with the x and y coordinates of the starting point and the ending point to form the two endpoints of the bounding box. When splitting for the first time, construct the bounding box with the horizontal / vertical tangent points as the division, and subsequent splitting refers to the direct splitting of the arc;
[0095] Ellipse and elliptical arc: The construction of the bounding box of the ellipse and the elliptical arc refers to the construction of the bounding box of the circle and the arc, and the difference lies in the calculation of the horizontal / vertical tangent points of the ellipse;
[0096] Spline curve: Only consider the non-closed spline curve of the control points. In this application, the bounding box is divided by the dichotomy based on the chord length ratio. When the arc length chord length ratio of the spline curve is less than a certain threshold and the first-order partial derivative vectors of the starting point and the ending point are in the same quadrant, it is considered that the bounding box formed by the starting point and the two endpoints contains this spline curve, otherwise the x and y coordinates of the two endpoints of the bounding box are the minimum values of the x and y coordinates of all control points.
[0097] In one embodiment, before step S13 of establishing the spatial division index structure for the first bounding box, it further includes:
[0098] Step S121, in the process of the first intersection calculation, if the first bounding box to be split is split for the first time, split the first bounding box and store the information of the sub-bounding boxes obtained by splitting the first bounding box into the acceleration cache;
[0099] The method further includes:
[0100] Step S17, during the first intersection calculation or the second intersection calculation, if the first bounding box to be split is not split for the first time, obtain the sub-bounding box information of the first bounding box from the acceleration cache.
[0101] In an application, by storing the sub-bounding box information obtained by splitting the first bounding box for the first time into the acceleration cache, when the first bounding box needs to be split subsequently, its sub-bounding box information can be directly obtained from the acceleration cache, avoiding repeated split calculations, saving the overhead of recalculating the sub-bounding box once, and thus improving the overall intersection speed.
[0102] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
[0103] The embodiment of the present application further provides a two-dimensional sketch full-intersection acceleration system for executing the steps in the embodiment of the two-dimensional sketch full-intersection acceleration method. The two-dimensional sketch full-intersection acceleration system can be a virtual appliance in a computer device, run by the processor of the computer device, or the computer device itself.
[0104] As Figure 3 shown, the embodiment of the present application provides a two-dimensional sketch full-intersection acceleration system 300, including:
[0105] A bounding box construction module 301 for constructing a first bounding box for the first voxel in the target two-dimensional sketch;
[0106] A first intersection module 302 for performing a first intersection calculation on the second voxel and the first bounding box in the target two-dimensional sketch to obtain a first intersection result when the ratio of the number of the first voxels to the number of the second voxels in the target two-dimensional sketch does not meet a preset threshold;
[0107] A space division index module 303 for establishing a space division index structure for the first bounding box, where the space division index structure includes the index of the first bounding box;
[0108] A second intersection module 304 for performing a second intersection calculation on each target bounding box in the first bounding box, the bounding box in the index of the target bounding box, and the bounding box in the parent index of the index to obtain a second intersection result.
[0109] In an embodiment, the space division index module 303 is used for:
[0110] Recursively divide the plane space of the target two-dimensional sketch into a quadtree structure according to a preset step size and a preset division threshold, and allocate target index information to each piece of target space obtained by the division;
[0111] The target index information includes the target index of the target space and the index of the parent space of the target space; when the target space is not the smallest divided space, the target index information further includes the indices of the sub-spaces of the target space;
[0112] For each target bounding box in the first bounding box, use the index of the smallest divided space of the target bounding box as the index of the target bounding box;
[0113] Delete the paths in the quadtree structure that do not contain bounding boxes.
[0114] In one embodiment, the space division index module 303 is configured to:
[0115] For each target bounding box in the first bounding box, find the corresponding space index of the target bounding box and add it to the index tree.
[0116] In one embodiment, the first intersection module 302 is further configured to:
[0117] When the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch satisfies a preset threshold, construct a hierarchical bounding volume structure for the first bounding box;
[0118] Perform a first intersection calculation on the second voxels and the hierarchical bounding volume structure to obtain a first intersection result.
[0119] In one embodiment, the first intersection module 302 is specifically configured to:
[0120] When the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch is greater than or equal to 2, construct a hierarchical bounding volume structure for the first bounding box based on the surface area heuristic algorithm.
[0121] In one embodiment, the two-dimensional sketch full-intersection acceleration system 300 further includes a voxel division module, configured to:
[0122] Obtain all voxels in the target two-dimensional sketch;
[0123] Divide all the voxels into first voxels and second voxels according to the type and geometric data of the voxels.
[0124] In one embodiment, the two-dimensional sketch full-intersection acceleration system 300 further includes an acceleration cache module, configured to:
[0125] In the first intersection calculation process, if the first bounding box to be split is split for the first time, split the first bounding box and store the sub-bounding box information obtained by splitting the first bounding box into the acceleration cache;
[0126] The method further includes an acceleration splitting module for:
[0127] In the first intersection calculation or the second intersection calculation process, if the first bounding box to be split is not split for the first time, obtain the sub-bounding box information of the first bounding box from the acceleration cache.
[0128] In an application, each module in the data verification device can be a software program module, can also be implemented by different logic circuits integrated in a processor, or can also be implemented by multiple distributed processors.
[0129] Figure 4 It is a schematic structural diagram of a computer device provided by an embodiment of the present application. As Figure 4 shown, the computer device 4 of this embodiment includes: at least one processor 40 ( Figure 4 only one is shown in the figure), a processor, a memory 41, and a computer program 42 stored in the memory 41 and operable on the at least one processor 40. When the processor 40 executes the computer program 42, the steps in any of the above-mentioned two-dimensional sketch full-intersection acceleration method embodiments are implemented.
[0130] The computer device may include, but is not limited to, a processor 40 and a memory 41. Those skilled in the art can understand that Figure 4 this is only an example of the computer device 4, and does not constitute a limitation on the computer device 4. It may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.
[0131] The processor 40 may be a central processing unit (CPU), and the processor 40 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0132] The memory 41 may be an internal storage unit of the computer device 4 in some embodiments, such as the hard disk or memory of the computer device 4. The memory 41 may also be an external storage device of the computer device 4 in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the computer device 4. Further, the memory 41 may also include both the internal storage unit and the external storage device of the computer device 4. The memory 41 is used to store an operating system, application programs, a BootLoader, data, and other programs, such as the program code of the computer program. The memory 41 may also be used to temporarily store data that has been output or will be output.
[0133] It should be noted that for the information interaction, execution process, etc. between the above-mentioned device / units, since they are based on the same concept as the method embodiments of the present application, for their specific functions and the technical effects brought, reference may be specifically made to the method embodiment part, and details are not described herein again.
[0134] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working process of the units and modules in the above system can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.
[0135] The embodiment of the present application also provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.
[0136] As Figure 5 shown, the embodiment of the present application provides a computer program product 5, including a computer program 50, and when the computer program 50 is run, the steps in the above-mentioned method embodiments of the full-intersection acceleration method for two-dimensional sketches are executed.
[0137] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-described embodiment methods of this application, a computer program can be used to instruct the relevant hardware to complete. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the device / computer equipment, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk, or an optical disc, etc. In some jurisdictions, according to legislation and patent practice, the computer-readable medium cannot be an electrical carrier signal and a telecommunication signal.
[0138] In the above embodiments, the descriptions of the various embodiments have their own focuses. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0139] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.
[0140] In the embodiments provided in this application, it should be understood that the disclosed computer equipment and methods can be implemented in other ways. For example, the computer equipment embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be in an electrical, mechanical, or other form.
[0141] The unit described as a separation component may or may not be physically separated. The component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0142] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.
Claims
1. A method for accelerating the full intersection of two-dimensional sketches, characterized in that, Including: Constructing a first bounding box for a first voxel in a target two-dimensional sketch; When the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch does not meet a preset threshold, performing a first intersection calculation on the second voxels and the first bounding box in the target two-dimensional sketch to obtain a first intersection result; when the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch meets the preset threshold, constructing a hierarchical bounding volume structure for the first bounding box; Performing a first intersection calculation on the second voxels and the hierarchical bounding volume structure to obtain a first intersection result; the first voxel is a voxel capable of constructing a bounding box, and the second voxel is a voxel incapable of constructing a bounding box; Establishing a spatial partitioning index structure for the first bounding box, where the spatial partitioning index structure includes an index of the first bounding box; Performing a second intersection calculation on each target bounding box in the first bounding box, the bounding box in the index of the target bounding box, and the bounding box in the parent index of the index of the target bounding box to obtain a second intersection result; The establishing a spatial partitioning index structure for the first bounding box includes: Recursively partitioning the planar space of the target two-dimensional sketch into a quadtree structure according to a preset step size and a preset partitioning threshold, and allocating target index information to each piece of target space obtained by the partitioning; The target index information includes a target index of the target space and an index of the parent space of the target space; when the target space is not the smallest partitioned space, the target index information further includes an index of the subspace of the target space; For each target bounding box in the first bounding box, using the index of the smallest partitioned space of the target bounding box as the index of the target bounding box; Deleting paths in the quadtree structure that do not contain bounding boxes.
2. The full-intersection acceleration method for 2D sketches as described in claim 1, wherein The establishing a spatial partitioning index structure for the first bounding box includes: For each target bounding box in the first bounding box, finding the spatial index corresponding to the target bounding box and adding it to the index tree.
3. The two-dimensional sketch full-intersection acceleration method according to claim 1 or 2, characterized in that The constructing a hierarchical bounding volume structure for the first bounding box when the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch meets the preset threshold includes: When the ratio of the number of second voxels to the number of first voxels in the target two-dimensional sketch is greater than or equal to 2, constructing a hierarchical bounding volume structure for the first bounding box based on the surface area heuristic algorithm.
4. The two-dimensional sketch full-intersection acceleration method according to claim 1, characterized in that Before constructing the first bounding box for the first voxel in the target two-dimensional sketch, it further includes: Obtaining all voxels in the target two-dimensional sketch; Dividing all the voxels into first voxels and second voxels according to the type and geometric data of the voxels.
5. The two-dimensional sketch full-intersection acceleration method according to claim 1, wherein Before establishing the spatial partitioning index structure for the first bounding box, it further includes: During the first intersection calculation, if the first bounding box to be split is split for the first time, splitting the first bounding box and storing the information of the sub-bounding boxes obtained by splitting the first bounding box into an acceleration cache; The method further includes: During the first intersection calculation or the second intersection calculation, if the first bounding box to be split is not split for the first time, obtain the sub-bounding box information of the first bounding box from the acceleration cache.
6. A two-dimensional sketch full-intersection acceleration system, characterized in that Comprising: A bounding box construction module, configured to construct a first bounding box for a first voxel in a target two-dimensional sketch; The first voxel is a voxel capable of constructing a bounding box; A first intersection module, configured to perform a first intersection calculation on a second voxel in the target two-dimensional sketch and the first bounding box to obtain a first intersection result when a ratio of the number of the first voxels to the number of second voxels in the target two-dimensional sketch does not meet a preset threshold; and construct a hierarchical bounding volume structure for the first bounding box when a ratio of the number of second voxels to the number of the first voxels in the target two-dimensional sketch meets the preset threshold; Perform a first intersection calculation on the second voxel and the hierarchical bounding volume structure to obtain a first intersection result; the second voxel is a voxel that cannot construct a bounding box; A space division indexing module, configured to establish a space division indexing structure for the first bounding box, where the space division indexing structure includes an index of the first bounding box; The establishing the space division indexing structure for the first bounding box includes: recursively performing space division of a plane space of the target two-dimensional sketch into a quadtree structure according to a preset step size and a preset division threshold, and allocating target index information to each piece of target space obtained by the division; the target index information includes a target index of the target space and an index of a parent space of the target space; when the target space is not the smallest divided space, the target index information further includes an index of a subspace of the target space; for each target bounding box in the first bounding box, using the index of the smallest divided space of the target bounding box as the index of the target bounding box; deleting paths in the quadtree structure that do not contain a bounding box; A second intersection module, configured to perform a second intersection calculation on each target bounding box in the first bounding box, a bounding box in an index of the target bounding box, and a bounding box in a parent index of the index of the target bounding box to obtain a second intersection result.
7. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, steps of the method according to any one of claims 1 to 5 are implemented.
8. A computer program product, characterized in that, Comprising a computer program, when the computer program is run, the method according to any one of claims 1 to 5 is executed.
Citation Information
Patent Citations
Rapid intersection method for STL (stereo lithography) models of products
CN102508973A