Display driving circuit and defect testing method

Abstract

The invention discloses a display driving circuit and a defect detection method. An example display driving integrated circuit includes a gamma voltage generator, a source driver, a gamma line, a first transistor, and a second transistor. The gamma voltage generator generates a gamma voltage. The source driver generates a data signal based on the gamma voltage. The gamma line connects the gamma voltage generator and the source driver and transmits a gamma voltage. The first transistor and the second transistor are connected to a first end and a second end of a first gamma line of the gamma lines. The first transistor includes a first gate for receiving a first signal. The second transistor includes a second gate for receiving a second signal. The first signal and the second signal are complementary to each other.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0135107 filed in the Korean Intellectual Property Office on October 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to driving of a display device, and more particularly, to a display driving circuit and a defect testing method. Background Art

[0003] The electronic device includes a display driver integrated circuit (DDI) for displaying image data on a display panel. The display driver integrated circuit includes a source driver, and the source driver is used to provide an input data signal related to the image data to a pixel included in the display panel through a source line. The source driver includes a source channel connected to the source line respectively. One source channel includes a source decoder and a source amplifier, the source decoder is used to select one of the gamma voltages generated by the gamma voltage generator based on the input data signal, and the source amplifier is used to amplify or buffer the selected voltage and provide the selected voltage as a data voltage to the pixel within a predetermined time.

[0004] In this case, the gamma lines between the gamma voltage generator and the source driver may have increased or decreased resistance due to factors such as poor process or short circuit with adjacent lines. When the resistance of the gamma lines is poor, it may be difficult for the pixels to receive accurate data voltages, and thus the electronic device may not be able to output high-quality images. Summary of the invention

[0005] The present disclosure relates to a display driver integrated circuit for determining defects of gamma lines, and a defect testing method for quickly screening display driver integrated circuits including abnormal gamma lines.

[0006] In some embodiments, a display driver integrated circuit includes: a gamma voltage generator for generating a gamma voltage; a source driver for generating a data signal based on the gamma voltage; a gamma line for connecting the gamma voltage generator with the source driver and transmitting the gamma voltage; and a first transistor and a second transistor connected to respective ends of a first gamma line from among the gamma lines and including gates for receiving signals complementary to each other.

[0007] In some embodiments, a display driver integrated circuit includes: a source driver for generating a data signal based on a gamma voltage; a gamma line for sending the gamma voltage to the source driver; a first transistor disposed at a front end of the gamma line; and a second transistor having a different type from the first transistor and disposed at a rear end of the gamma line.

[0008] In some embodiments, a method for testing defects of a gamma line sequentially connected to a first transistor, a source driver, and a second transistor includes: applying a first test voltage to the first transistor and applying a second test voltage to the second transistor; sending an enable signal to a gate of the second transistor and sending a disable signal to a gate of the first transistor, the disable signal being an inverted signal of the enable signal; obtaining a current value of a current flowing to the gamma line; and determining whether the gamma line has a defect based on the current value. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A block diagram illustrating an example of a display system.

[0010] Figure 2 A block diagram illustrating an example of a display device.

[0011] Figure 3 A block diagram illustrating an example of a display device.

[0012] Figure 4 A block diagram illustrating an example of a display device.

[0013] Figure 5 A block diagram illustrating an example of a display device.

[0014] Figure 6 A block diagram illustrating an example of a display device.

[0015] Figure 7 A circuit diagram showing an example of a gamma voltage generator.

[0016] Figure 8 A circuit diagram showing an example of a gamma voltage generator.

[0017] Fig. 9 A block diagram showing an example of a source driver.

[0018] Fig.10 A timing diagram showing an example of an enable signal.

[0019] Fig.11 A block diagram showing an example of a source driver.

[0020] Fig.12 A timing diagram showing an example of an enable signal.

[0021] Fig.13 A block diagram illustrating an example of a display driver integrated circuit.

[0022] Fig.14 A flow chart showing an example of a method for testing gamma lines.

[0023] Fig.15 An example of a semiconductor system is shown. DETAILED DESCRIPTION

[0024] In the following detailed description, only certain embodiments of the present disclosure are shown and described by way of illustration. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0025] Therefore, the drawings and descriptions are considered to be illustrative rather than restrictive in nature, and the same reference numerals represent the same elements throughout the specification. In the flowcharts described with reference to the drawings in this specification, the order of operations may be changed, various operations may be combined, specific operations may be divided, and specific operations may not be performed.

[0026] Unless the expressions "one", "single", etc. are used, expressions recited in the singular may be interpreted as singular or plural. Terms including ordinal numbers such as first, second, etc. will only be used to describe various components and should not be interpreted as limiting these components. The terms may only be used to distinguish one component from other components.

[0027] Figure 1 A block diagram illustrating an example of a display system.

[0028] Reference Figure 1 The display system 10 may be installed on an electronic device having an image display function. For example, the electronic device may include a smart phone, a tablet personal computer (PC), a portable multimedia player (PMP), a camera, a wearable device, a television, a digital video disk (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, a robot, an unmanned aerial vehicle, various medical instruments, a navigation device, a global positioning system (GPS) receiver, a transportation device, furniture, or various measuring devices.

[0029] In some embodiments, the display system 10 may provide an artificial reality system (e.g., a virtual reality (VR) system, an augmented reality (AR) system, a mixed reality (MR) system, a hybrid reality system, or a combination thereof, and / or derivative systems). The artificial reality system may be implemented on various types of platforms including head mounted displays (HMDs), mobile devices, computing systems, and other hardware platforms for providing artificial reality content to at least one viewer.

[0030] The display system 10 may include a host processor 100 and a display device 200. The display device 200 may include a display driver integrated circuit (DDI) 210 and a display panel 220.

[0031] The host processor 100 may generate an input image signal (IS) to be displayed on the display panel 220, and may transmit the input image signal (IS) and a control command (CTRL) to the DDI 210. The input image signal (IS) may include frame data corresponding to each frame. The control command (CTRL) may include setting information about brightness, gamma, and frame rate.

[0032] The host processor 100 may be a graphics processor. However, the present disclosure is not limited thereto, and the host processor 100 may be implemented with various types of processors, such as a central processing unit (CPU), a microprocessor, a multimedia processor, an application processor (AP), or an electronic control unit (ECU). In some embodiments, the host processor 100 may be implemented with an integrated circuit (IC) or a system on chip (SoC).

[0033] The display device 200 may receive an input image signal (IS) from the host processor 100, and may display an image based on the input image signal (IS). The display device 200 may display a two-dimensional (2D) or three-dimensional (3D) image to a user. In some embodiments, the display device 200 may be a device in which the DDI 210 and the display panel 220 are implemented as a single module. For example, the DDI 210 may be mounted on a substrate of the display panel 220, or the DDI 210 and the display panel 220 may be electrically connected to each other through a connecting member such as a flexible printed circuit board (FPCB).

[0034] The DDI 210 may generate an analog signal for driving the display panel 220 based on the input image signal (IS) received from the host processor 100. For example, the analog signal may include a gate signal and a data signal for driving a pixel included in the display panel 220. The DDI 210 may provide the gate signal and the data signal to the pixel. The display panel 220 may emit image light corresponding to the input image signal (IS) through the signal provided by the DDI 210.

[0035] The DDI 210 may include a gamma voltage generator (G_GEN) 211 and a source driver (S_DRV) 212 . The gamma voltage generator 211 may generate a gamma voltage VG. The gamma voltage VG may correspond to various brightness levels. The gamma voltage generator 211 may output the gamma voltage VG to the source driver 212 .

[0036] The source driver 212 may generate a data signal regarding an input image signal (IS) based on the gamma voltage VG. For example, the source driver 212 may include a decoder and a source amplifier. The source driver 212 may output the data signal to the display panel 220.

[0037] In some embodiments, the resistance component of the wires for connecting the gamma voltage generator 211 and the source driver 212 may be non-uniform. For example, the gamma line may be arranged between the gamma voltage generator 211 and the source driver 212, and the gamma voltage generator 211 may output the gamma voltage VG to the source driver 212 through the gamma line. When a defect is generated during the process or an adjacent line is short-circuited, the gamma line may generate a non-uniform resistance component, which may deteriorate the quality of the image output by the display device 200. For example, when the resistance component of at least one of the gamma lines deviates from the reference resistance range, the gamma voltage generator 211 may not output the target voltage within the target time. That is, the source driver 212 may receive an unexpected voltage at an unexpected time, and the display panel 220 may output a low-quality image.

[0038] The DDI 210 may measure the resistance component of at least one of the gamma lines for connecting the gamma voltage generator 211 and the source driver 212 accordingly. The DDI 210 may determine that the gamma line whose measured resistance component deviates from the reference resistance range is bad. The DDI 210 may determine that the gamma line whose measured resistance component is within the reference resistance range is normal. In some embodiments, instead of the DDI 210, an external test device may be connected to the DDI 210, and the resistance component of the gamma line may be measured. In some embodiments, the DDI 210 may measure the current or voltage of the source driver 212, and may determine whether the gamma line has a defect based on the measured value.

[0039] The display panel 220 may display an image to a user based on a data signal of the source driver 212. The display panel 220 may be one of a display device "for receiving an electrically transmitted image signal and displaying an image" (such as a thin film transistor liquid crystal display (TFT-LCD), a light emitting diode (LED) display, a micro light emitting diode (μLED) display, an organic light emitting diode (OLED) display, an active matrix OLED display (AMOLED), a transparent OLED display (TOLED), a field emission display, a plasma display panel (PDP)). In some embodiments, the display panel 220 may be single or multiple. For example, two display panels 220 may output image light to the user's eyes.

[0040] Figure 2 A block diagram illustrating an example of a display device.

[0041] Reference Figure 2 , the display device 250 may include a DDI 300 and a display panel 400 .

[0042] The DDI 300 may transmit the data signal to the display panel 400 through the source line SL. The display panel 400 may display an image based on the data signal.

[0043] The DDI 300 may include a gamma voltage generator 310 and a source driver 320. The gamma voltage generator 310 may receive a minimum gamma voltage VG_BOT and a maximum gamma voltage VG_TOP. In some embodiments, an external power supply may output the minimum gamma voltage VG_BOT and the maximum gamma voltage VG_TOP to the gamma voltage generator 310. In some embodiments, the DDI 300 may further include a reference voltage generator for generating the minimum gamma voltage VG_BOT and the maximum gamma voltage VG_TOP. The reference voltage generator may receive an input voltage from an external power supply of the DDI 300, and may generate the minimum gamma voltage VG_BOT and the maximum gamma voltage VG_TOP based on the input voltage. In some embodiments, the DDI 300 may further include a direct current to direct current (DC-DC) converter for supplying the input voltage to the reference voltage generator.

[0044] The gamma voltage generator 310 may generate the gamma voltages VG based on the minimum gamma voltage VG_BOT and the maximum gamma voltage VG_TOP. The gamma voltage generator 310 may output the gamma voltages VG to the source driver 320.

[0045] The source driver 320 may generate a data signal based on the gamma voltage VG. The source driver 320 may output the data signal to the display panel 400 through the source lines SL.

[0046] The gamma voltage generator 310 and the source driver 320 may be connected through the gamma line. That is, the gamma voltage generator 310 may transmit the gamma voltage VG to the source driver 320 through the gamma line. In this case, in order to calculate the resistance component of the gamma line, the DDI 300 may further include a transistor connected to the gamma line.

[0047] For example, using the first gamma line 305 among the gamma lines, the DDI 300 may include a first transistor TR1 and a second transistor TR2 connected to the first gamma line 305. The first transistor TR1 and the second transistor TR2 may be transistors of different types. For example, the first transistor TR1 may be a p-channel metal oxide semiconductor (PMOS) transistor, and the second transistor TR2 may be an n-channel metal oxide semiconductor (NMOS) transistor, and the embodiment is not limited thereto.

[0048] The first transistor TR1 and the second transistor TR2 may be arranged at respective ends of the first gamma line 305. For example, the first transistor TR1 may be arranged at a front end of the first gamma line 305, and the second transistor TR2 may be arranged at a rear end of the first gamma line 305. The front end of the first gamma line 305 may mean a position before the first gamma line 305 passes through the source driver 320, and the rear end of the first gamma line 305 may mean a position after the first gamma line 305 passes through the source driver 320. The first transistor TR1 may be arranged between the gamma voltage generator 310 and the source driver 320. The first transistor TR1 may be connected to the first gamma line 305 through a drain, and the second transistor TR2 may be connected to the first gamma line 305 through a drain.

[0049] The first transistor TR1 and the second transistor TR2 may be used to measure the resistance component of the first gamma line 305 in the source driver 320. In some embodiments, a first driving voltage may be applied to the source of the first transistor TR1, and a second driving voltage may be applied to the source of the second transistor TR2. The first driving voltage and the second driving voltage may be one of the voltages generated or used by the display device 250, respectively. In some embodiments, a maximum gamma voltage VG_TOP may be applied to the source of the first transistor TR1, and the source of the second transistor TR2 may be grounded.

[0050] Two signals complementary to each other may be input to the gate of the first transistor TR1 and the gate of the second transistor TR2. For example, a non-enable signal / EN may be input to the gate of the first transistor TR1, and an enable signal EN may be input to the gate of the second transistor TR2.

[0051] The DDI 300 may further include a controller for controlling the overall operation of the DDI 300. The controller may generate a non-enable signal / EN and an enable signal EN, and may output the signals / EN and EN to the transistors TR1 and TR2 when measuring the resistance component of the first gamma line 305. In some embodiments, the DDI 300 may further include an inverter. The controller may generate an enable signal EN and may input the enable signal EN to the second transistor TR2, and the inverter may invert the enable signal EN to generate a non-enable signal / EN. The inverter may input the non-enable signal / EN to the first transistor TR1.

[0052] The controller may measure a resistance component of the first gamma line 305. The controller may measure a current flowing to the first gamma line 305. The controller may determine whether the first gamma line 305 has a defect based on a reference current range. For example, when the measured current value deviates from the reference current range, the controller may determine that the first gamma line 305 is abnormal. When the measured current value is within the reference current range, the controller may determine that the first gamma line 305 is normal.

[0053] The controller may measure the resistance component based on the measured current value and the voltage applied to the corresponding ends (e.g., the front end and the rear end) of the first gamma line 305. The controller may calculate the resistance component by dividing the current value by the potential difference at the corresponding ends of the first gamma line 305. The controller may determine whether the first gamma line 305 has a defect based on the reference resistance range. For example, when the calculated resistance deviates from the reference resistance range, the controller may determine that the first gamma line 305 is abnormal. When the calculated resistance is within the reference resistance range, the controller may determine that the first gamma line 305 is normal.

[0054] In some embodiments, an external test device of the DDI 300 may measure the current flowing to the first gamma line 305. One end of the test device may be connected to the first transistor TR1, and the other end may be connected to the second transistor TR2. When the measured current value deviates from the reference current range, the test device may determine that the first gamma line 305 is abnormal. When the measured current value is within the reference current range, the test device may determine that the first gamma line 305 is normal. In some implementations, the test device may calculate the resistance of the resistance component based on the measured current value. The test device may determine whether the first gamma line 305 has a defect based on the calculated resistance and the reference resistance range.

[0055] Figure 2 A first gamma line 305 from among the gamma lines is shown, at least one further gamma line may be connected to two transistors in a similar manner as the first gamma line 305, and a current or resistance may be measured.

[0056] Figure 3 A block diagram illustrating an example of a display device.

[0057] Reference Figure 3 , the display device 250 may include a DDI 300 and a display panel 400. Figure 2 The contents of the description are identically applicable to the display panel 400. Therefore, a repeated description will not be provided.

[0058] The DDI 300 may include a first pad 301 and a second pad 302. A first test voltage VTS1 may be applied through the first pad 301, and the first transistor TR1 may receive the first test voltage VTS1 through a source. A second test voltage VTS2 may be applied through the second pad 302, and the second transistor TR2 may receive the second test voltage VTS2 through a source. In some embodiments, the first test voltage VTS1 and the second test voltage VTS2 may be one of voltages generated or used by the display device 250, respectively. In some embodiments, the first test voltage VTS1 and the second test voltage VTS2 may be voltages generated by an external test device for test purposes.

[0059] The current IG1 may flow to the first gamma line 305 through the first test voltage VTS1 of the first pad 301, the second test voltage VTS2 of the second pad 302, and the resistance component 325 of the first gamma line 305. For example, the resistance component 325 may represent a resistance component between the front end and the rear end of the first gamma line 305. The controller of the DDI 300 may measure the value of the current IG1.

[0060] The controller of DDI 300 may calculate the resistance RG of resistance component 325 as shown in Equation 1.

[0061] (Equation 1)

[0062]

[0063] Here, RG is the resistance of the resistance component 325 (ohms), VTS1 is the value of the first test voltage VTS1 (volts), VTS2 is the value of the second test voltage VTS2 (volts), and IG1 is the value of the current IG1 (amperes).

[0064] The controller may determine whether the first gamma line 305 has a defect based on the value of the measured current IG1 or the calculated resistance RG. In some embodiments, when the value of the measured current IG1 is within the reference current range, the controller may determine that the first gamma line 305 is normal, and when the value of the measured current IG1 deviates from the reference current range, the controller may determine that the first gamma line 305 is abnormal. In some embodiments, when the calculated resistance RG is within the reference resistance range, the controller may determine that the first gamma line 305 is normal, and when the calculated resistance RG deviates from the reference resistance range, the controller may determine that the first gamma line 305 is abnormal.

[0065] In some embodiments, an external test device of the DDI 300 may measure the current IG1 flowing to the first gamma line 305. One end of the test device may be connected to the first transistor TR1, and the other end may be connected to the second transistor TR2. When the current value of the measured current IG1 deviates from the reference current range, the test device may determine that the first gamma line 305 is abnormal. When the current value of the measured current IG1 is within the reference current range, the test device may determine that the first gamma line 305 is normal. In some embodiments, a test device (e.g., a controller) may calculate the resistance RG of the resistance component 325 based on the measured current value. The test device may determine whether the first gamma line 305 has a defect based on the calculated resistance RG and the reference resistance range.

[0066] Figure 3 A first gamma line 305 from among the gamma lines is shown, at least one further gamma line may be connected to two transistors in a similar manner as the first gamma line 305, and a current or resistance may be measured.

[0067] Figure 4 A block diagram illustrating an example of a display device.

[0068] Reference Figure 4 , the display device 250 may include a DDI 300 and a display panel 400. Figure 2 The contents of the description are identically applicable to the display panel 400. Therefore, a repeated description will not be provided.

[0069] The DDI 300 may include a first pad 301 and a second pad 302. A maximum gamma voltage VG_TOP is applied through the first pad 301, and the first transistor TR1 may receive the maximum gamma voltage VG_TOP through a source. The maximum gamma voltage VG_TOP may be one of the voltages input to the gamma voltage generator 310. The second pad 302 may be connected to a ground (GND), and a source of the second transistor TR2 may be connected to the ground (GND). In some embodiments, a minimum gamma voltage VG_BOT may be applied through the second pad 302, and the second transistor TR2 may receive the minimum gamma voltage VG_BOT through a source.

[0070] Current IG2 may flow to the first gamma line 305 through the maximum gamma voltage VG_TOP of the first pad 301 and the resistance component 325 of the first gamma line 305. The test apparatus 500 may measure the current IG2 flowing to the first gamma line 305. The test apparatus 500 may be connected to a line for supplying the maximum gamma voltage VG_TOP through the first pad 301.

[0071] When the current value of the measured current IG2 deviates from the reference current range, the test device 500 may determine that the first gamma line 305 is abnormal. When the current value of the measured current IG2 is within the reference current range, the test device 500 may determine that the first gamma line 305 is normal.

[0072] The test apparatus 500 may calculate the resistance RG of the resistance component 325 as shown in Equation 2.

[0073] (Equation 2)

[0074]

[0075] Here, RG is the resistance of the resistance component 325 (ohms), VG_TOP is the value of the maximum gamma voltage VG_TOP (volts), and IG2 is the value of the current IG2 (amperes).

[0076] The test device 500 may determine whether the first gamma line 305 has a defect based on the calculated resistance RG and the reference resistance range. When the calculated resistance RG is within the reference resistance range, the test device 500 may determine that the first gamma line 305 is normal, and when the calculated resistance RG deviates from the reference resistance range, the test device 500 may determine that the first gamma line 305 is abnormal.

[0077] In some embodiments, the controller of the DDI 300 may measure the current IG2 and may determine whether the first gamma line 305 has a defect based on the measured current value and a reference current range. In some embodiments, the controller of the DDI 300 may calculate the resistance RG of the resistance component 325 and may determine whether the first gamma line 305 has a defect based on the resistance RG and a reference resistance range.

[0078] Figure 4 A first gamma line 305 from among the gamma lines is shown, at least one further gamma line may be connected to two transistors in a similar manner as the first gamma line 305, and a current or resistance may be measured.

[0079] Figure 5 A block diagram illustrating an example of a display device.

[0080] Reference Figure 5 , the display device 251 may include a DDI 300 and a display panel 400. The DDI 300 may include a gamma voltage generator 310 and a source driver 320. Figure 2 The contents of the description are identically applicable to the gamma voltage generator 310 and the display panel 400. Therefore, a repeated description will not be provided.

[0081] The source driver 320 may include decoders (DEC) 321_1 to 321_m (m is an integer greater than 1) and source amplifiers (SAMP) 322_1 to 322_m. The decoders 321_1 to 321_m may correspond to the source amplifiers 322_1 to 322_m and may be connected to the source amplifiers 322_1 to 322_m.

[0082] The decoders 321_1 to 321 — m may receive the gamma voltages VG from the gamma voltage generator 310 .

[0083] Each decoder 321_1 to 321_m may select one of the gamma voltages VG based on the input image signal. In some embodiments, the controller of the DDI 300 may sample the input image signal and may output the sampled signal to the decoders 321_1 to 321_m. The decoders 321_1 to 321_m may select one of the gamma voltages VG based on the sampled signal. Each decoder 321_1 to 321_m may output the selected voltage to the source amplifiers 322_1 to 322_m.

[0084] The source amplifiers 322_1 to 322_m may amplify the gamma voltages selected by the decoders 321_1 to 321_m to generate data signals. The source amplifiers 322_1 to 322_m may transmit the data signals to the display panel 400 through the source lines SL. The display panel 400 may display an image based on the data signals.

[0085] The gamma voltage generator 310 and the decoders 321_1 to 321_m may be connected through gamma lines. That is, the gamma voltage generator 310 may transmit the gamma voltage VG to the decoders 321_1 to 321_m through the gamma lines. In this case, in order to calculate the resistance component of the gamma lines, the DDI 300 may further include transistors connected to the gamma lines.

[0086] For example, for a first gamma line 305 among the gamma lines, the DDI 300 may include a first transistor TR1 and a second transistor TR2 connected to the first gamma line 305. The first transistor TR1 and the second transistor TR2 may be transistors of different types. For example, the first transistor TR1 may be a PMOS transistor, and the second transistor TR2 may be an NMOS transistor, and the embodiment is not limited thereto.

[0087] The first transistor TR1 and the second transistor TR2 may be arranged at respective ends of the first gamma line 305. For example, the first transistor TR1 may be arranged at the front end of the first gamma line 305, and the second transistor TR2 may be arranged at the rear end of the first gamma line 305. The front end of the first gamma line 305 may represent a position before the first gamma line 305 passes through the decoders 321_1 to 321_m, and the rear end of the first gamma line 305 may represent a position after the first gamma line 305 passes through the decoders 321_1 to 321_m. The first transistor TR1 may be arranged between the gamma voltage generator 310 and the first decoder 321_1. The first decoder 321_1 may be first connected to a gamma line (e.g., the first gamma line 305) among the decoders 321_1 to 321_m. The first transistor TR1 may be connected to the first gamma line 305 through a drain, and the second transistor TR2 may be connected to the first gamma line 305 through a drain.

[0088] The first transistor TR1 and the second transistor TR2 may be used to measure the resistance component of the first gamma line 305 in the decoders 321_1 to 321_m. Figure 3 or Figure 4 The contents of the description are equally applicable to the element for measuring the resistance component of the first gamma line 305. Therefore, repeated description will not be provided.

[0089] Figure 6 A block diagram illustrating an example of a display device.

[0090] Reference Figure 6 , the display device 252 may include a DDI 300 and a display panel 400. The DDI 300 may include a gamma voltage generator 310 and a source driver 320. Figure 2 The contents of the description are identically applicable to the gamma voltage generator 310, the source driver 320, and the display panel 400. Therefore, a repeated description will not be provided.

[0091] The gamma voltage generator 310 and the source driver 320 may be connected via a gamma line. That is, the gamma voltage generator 310 may send the gamma voltage VG to the source driver 320 via the gamma line. In this case, the DDI 300 may further include a transistor connected to the gamma line for a stress test of the DDI 300. When a voltage in a specific range is applied, a stress test may be provided to determine whether the DDI 300 has a defect based on an output (e.g., voltage, current, etc.) of the DDI 300. The DDI 300 including a gamma line determined to be defective by the stress test may be screened.

[0092] For example, for a first gamma line 305 among the gamma lines, the DDI 300 may include a first transistor TR1, a second transistor TR2, and a third transistor TR3 connected to the first gamma line 305. The first transistor TR1 to the third transistor TR3 may be transistors of different types. For example, the first transistor TR1 may be a PMOS transistor, and the second transistor TR2 and the third transistor TR3 may be NMOS transistors, and the embodiment is not limited thereto.

[0093] The first transistor TR1 to the third transistor TR3 may be arranged at respective ends of the first gamma line 305. For example, the first transistor TR1 and the third transistor TR3 may be arranged at the front end of the first gamma line 305, and the second transistor TR2 may be arranged at the rear end of the first gamma line 305. The front end of the first gamma line 305 may represent a position before the first gamma line 305 passes through the source driver 320, and the rear end of the first gamma line 305 may represent a position after the first gamma line 305 passes through the source driver 320. The first transistor TR1 and the third transistor TR3 may be arranged between the gamma voltage generator 310 and the source driver 320. The first transistor TR1 may be connected to the first gamma line 305 through a drain, and the second transistor TR2 and the third transistor TR3 may be connected to the first gamma line 305 through a drain.

[0094] The first to third transistors TR1 to TR3 may be used for stress testing of the first gamma line 305 in the source driver 320. In some embodiments, a first test voltage VTS1 may be applied to the source of the first transistor TR1, a second test voltage VTS2 may be applied to the source of the second transistor TR2, and a third test voltage VTS3 may be applied to the source of the third transistor TR3. The first to third test voltages VTS1 to VTS3 may be one of the voltages generated or used by the display device 252, respectively. In some embodiments, the maximum gamma voltage VG_TOP may be applied to the source of the first transistor TR1 (e.g., as the first test voltage VTS1), and the sources of the second and third transistors TR2 and TR3 may be grounded.

[0095] Different signals may be input to the gates of the first transistor TR1 to the third transistor TR3. For example, the first signal EN1 to the third signal EN3 may be input to the gates of the first transistor TR1 to the third transistor TR3. In some embodiments, the first signal EN1 and the third signal EN3 may be complementary to each other. The second signal EN2 may be obtained by performing a logic OR operation on the first signal EN1 and the third signal EN3. That is, when the first transistor TR1 is in the on state, the third transistor TR3 is in the off state, and vice versa. When the first transistor TR1 or the third transistor TR3 is in the on state, the second transistor TR2 is in the on state. Therefore, the full swing voltage between the first test voltage VTS1 and the third test voltage VTS3 may be applied to the first gamma line 305.

[0096] The DDI 300 may further include a controller for controlling the overall operation of the DDI 300. The controller may generate first to third signals EN1 to EN3, and may output the first to third signals EN1 to EN3 to the first to third transistors TR1 to TR3 at the test time of the first gamma line 305. In some embodiments, the DDI 300 may further include an inverter. The controller may generate a first signal EN1 and may input the first signal EN1 to the first transistor TR1, and the inverter may invert the first signal EN1 to generate the third signal EN3. The inverter may input the third signal EN3 to the third transistor TR3. In some embodiments, the DDI 300 may further include a logic OR circuit (or an OR gate circuit). The logic OR circuit may generate a second signal EN2 by performing a logic OR operation on the first signal EN1 and the third signal EN3. The logic OR circuit may input the second signal EN2 to the second transistor TR2.

[0097] When the first gamma line 305 applies a voltage to the source driver 320, the controller may determine whether the DDI 300 has a defect based on the voltage (or current) output by the source driver 320. The first gamma line 305 may apply a full swing voltage between the first test voltage VTS1 and the third test voltage VTS3 to the source driver 320. The controller may determine whether the DDI 300 has a defect based on the first reference voltage range and the second reference voltage range. For example, the first reference voltage range may have a voltage range including the first test voltage VTS1, and the second reference voltage range may have a voltage range including the third test voltage VTS3. When the voltage output by the source driver 320 is within the first reference voltage range and the second reference voltage range, the controller may determine that the DDI 300 is normal. For example, when the maximum value of the voltage output by the source driver 320 is within the first reference voltage range and the minimum value is within the second reference voltage range, the controller may determine that the DDI 300 is normal. In some embodiments, the controller may determine whether the DDI 300 has a defect based on the waveform of the voltage output by the source driver 320.

[0098] In some embodiments, a test device external to the DDI 300 may be connected to the source driver 320 and may measure a voltage (or current) of the source driver 320. When the measured voltage value deviates from a reference voltage range, the test device may determine that the first gamma line 305 is abnormal. When the measured current value is within the reference voltage range, the test device may determine that the first gamma line 305 is normal.

[0099] Figure 6 A first gamma line 305 from among the gamma lines is shown, and at least one further gamma line may be connected to two transistors in a similar manner as the first gamma line 305, and a voltage may be measured.

[0100] Figure 7 A circuit diagram showing an example of a gamma voltage generator.

[0101] Reference Figure 7 , the gamma voltage generator 600 may include resistors R0 to RN (N is an integer greater than 1). The resistors R0 to RN may be a resistor string connected in series. The gamma voltage generator 600 may generate the first gamma voltage VG_1 to the Nth gamma voltage VG_N by dividing the interval between the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT. The gamma voltage generator 600 may output the first gamma voltage VG_1 to the Nth gamma voltage VG_N between the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT divided by the resistors R0 to RN together with the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT as the gamma voltage VG.

[0102] Figure 8 A circuit diagram showing an example of a gamma voltage generator.

[0103] Reference Figure 8 , the gamma voltage generator 700 may include a first resistor string (R string) 710, decoders 721 to 724, amplifiers 731 to 734, and a second resistor string 740. According to an embodiment, the gamma voltage generator 700 may further include at least one resistor string, at least one decoder, and at least one amplifier.

[0104] The first resistor string 710 may include resistors connected in series. The first resistor string 710 may generate a voltage VT by dividing the interval between the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT. The first resistor string 710 may output the voltage between the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT divided by the resistors and the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT together as the voltage VT.

[0105] The decoders 721 to 724 may select one of the voltages. For example, the decoders 721 to 724 may receive a voltage selection signal from a controller of the DDI, and may select one of the voltages based on the voltage selection signal.

[0106] The voltage received by the decoders 721 to 724 may be a voltage based on the voltage VT output by the first resistor string 710. In some embodiments, at least one of the decoders 721 to 724 may receive the voltage VT output by the first resistor string 710, and may select one of the voltages VT. In some embodiments, at least one of the decoders 721 to 724 may select one of the voltages generated by at least two resistor strings. For example, the at least two resistor strings may include the first resistor string 710 and an additional resistor string. The additional resistor string may receive the voltage VT from the first resistor string 710 and may generate a secondary voltage. At least one of the decoders 721 to 724 may select one of the secondary voltages.

[0107] The amplifiers 731 to 734 may amplify the voltage selected by the decoders 721 to 724. For example, the amplifiers 731 to 734 may generate voltages VH1, VH2, VH_P-2, and VH_P-1 (P is an integer greater than 2) by amplifying the selected voltages. In this case, the amplifiers 732 and 733 may output the voltages VH_2 and VH_P-1 to the second resistor string 740. For example, the amplifiers 732 and 733 may output the voltages VH_2 and VH_P-1 to the display panel.

[0108] The second resistor string 740 may include resistors R1 to RQ (Q is an integer greater than 3). Q may be an integer less than 3 than P. The second resistor string 740 may generate voltages VH_3 to VH_P-2 by dividing the interval between the voltage VH_2 and the voltage VH_P-1. The second resistor string 740 may output the voltages VH_3 to VH_P-2 generated by the resistors R1 to RQ together with the voltages VH_2 and VH_P-1. The voltages VH_1 to VH_P output by the amplifiers 731 to 734 and the second resistor string 740 may be input to the source driver of the DDI as gamma voltages. The source driver may generate a data signal based on the voltages VH_1 to VH_P.

[0109] Fig. 9 A block diagram showing an example of a source driver, and Fig.10 A timing diagram showing an example of an enable signal.

[0110] Reference Fig. 9 , the source driver 800 may receive the gamma voltages VK_1 to VK_6. The source driver 800 may generate data signals based on the gamma voltages VK_1 to VK_6.

[0111] The source driver 800 may receive the gamma voltages VK_1 to VK_6 through the gamma lines GL1 to GL6. In this case, when the gamma lines GL1 to GL6 have defects (such as non-uniform resistance components), it is difficult for the source driver 800 to normally receive the gamma voltages VK_1 to VK_6. Therefore, in order to determine whether the gamma lines GL1 to GL6 have defects, the gamma lines GL1 to GL6 may be connected to the first transistors TR1_1 to TR1_6 and the second transistors TR2_1 to TR2_6. The first transistors TR1_1 to TR1_6 and the second transistors TR2_1 to TR2_6 may be transistors of different types. For example, the first transistors TR1_1 to TR1_6 may be PMOS transistors, the second transistors TR2_1 to TR2_6 may be NMOS transistors, and the embodiment is not limited thereto. The drains of the first transistors TR1_1 to TR1_6 and the drains of the second transistors TR2_1 to TR2_6 may be connected to the gamma lines GL1 to GL6.

[0112] The first transistors TR1_1 to TR1_6 and the second transistors TR2_1 to TR2_6 may be used to measure the resistance components of the gamma lines GL1 to GL6 in the source driver 800. In some embodiments, a first test voltage VTS1 may be applied to the sources of the first transistors TR1_1 to TR1_6, and a second test voltage VTS2 may be applied to the sources of the second transistors TR2_1 to TR2_6. The first test voltage VTS1 and the second test voltage VTS2 may be one of the voltages generated or used by the display device, respectively. In some embodiments, a maximum gamma voltage VG_TOP may be applied to the sources of the first transistors TR1_1 to TR1_6, and the sources of the second transistors TR2_1 to TR2_6 may be grounded.

[0113] Two signals complementary to each other may be input to the gates of the first transistors TR1_1 to TR1_6 and the gates of the second transistors TR2_1 to TR2_6. For example, the non-enable signals / EN1 to / EN6 may be input to the gates of the first transistors TR1_1 to TR1_6, and the enable signals EN1 to EN6 may be input to the gates of the second transistors TR2_1 to TR2_6.

[0114] The controller of the DDI may generate non-enable signals / EN1 to / EN6 and enable signals EN1 to EN6.

[0115] Reference Fig. 9 and Fig.10, the controller may generate enable signals EN1 to EN6. The enable signals EN1 to EN6 may have different logic level transition times. For example, when the first enable signal EN1 changes from a first level (e.g., high) to a second level (e.g., low), the second enable signal EN2 may change from the second level to the first level. That is, the controller may generate enable signals EN1 to EN6, and the first levels of the enable signals EN1 to EN6 do not overlap with each other in the time domain. The enable signals EN1 to EN6 may have the same pulse width. The controller may generate non-enable signals / EN1 to / EN6 in a manner similar to that of generating enable signals EN1 to EN6.

[0116] When the first enable signal EN1 is changed from the second level to the first level and the first non-enable signal / EN1 is changed from the first level to the second level, due to the potential difference between the first test voltage VTS1 at the source of the first transistor TR1_1 and the second test voltage VTS2 at the source of the second transistor TR2_1, current may flow to the first gamma line GL1. The controller may measure the current flowing to the first gamma line GL1. The controller may determine whether the first gamma line GL1 has a defect based on the measured current and the reference current range. The controller may calculate the resistance of the first gamma line GL1 based on the measured current and the potential difference between the first test voltage VTS1 and the second test voltage VTS2. The controller may determine whether the first gamma line GL1 has a defect based on the calculated resistance and the reference resistance range. The controller may determine whether the other gamma lines GL2 to GL6 have a defect in a similar manner to the first gamma line GL1.

[0117] In some embodiments, the test apparatus may determine at least one of a current and a resistance of the gamma lines GL1 to GL6 , and may determine whether the gamma lines GL1 to GL6 have a defect based on at least one of the determined current value and the resistance.

[0118] Fig.11 A block diagram showing an example of a source driver, and Fig.12 A timing diagram showing an example of an enable signal.

[0119] Reference Fig.11 , the source driver 900 may receive the gamma voltages VK_1 to VK_6. The source driver 900 may generate data signals based on the gamma voltages VK_1 to VK_6.

[0120] The source driver 900 may receive the gamma voltages VK_1 to VK_6 through the gamma lines GL1 to GL6. In this case, when the gamma lines GL1 to GL6 have defects (such as non-uniform resistance components), it is difficult for the source driver 900 to normally receive the gamma voltages VK_1 to VK_6. Therefore, in order to determine whether the gamma lines GL1 to GL6 have defects, the gamma lines GL1 to GL6 may be connected to the first transistors TR1_1 to TR1_6 and the second transistors TR2_1 to TR2_6. The first transistors TR1_1 to TR1_6 and the second transistors TR2_1 to TR2_6 may be transistors of different types. For example, the first transistors TR1_1 to TR1_6 may be PMOS transistors, and the second transistors TR2_1 to TR2_6 may be NMOS transistors, and the embodiment is not limited thereto. The drains of the first transistors TR1_1 to TR1_6 and the drains of the second transistors TR2_1 to TR2_6 may be connected to the gamma lines GL1 to GL6.

[0121] The first transistors TR1_1 to TR1_6 and the second transistors TR2_1 to TR2_6 may be used to measure the resistance components of the gamma lines GL1 to GL6 in the source driver 800. In some embodiments, a first test voltage VTS1 may be applied to the sources of the first transistors TR1_1 to TR1_6, and a second test voltage VTS2 may be applied to the sources of the second transistors TR2_1 to TR2_6. The first test voltage VTS1 and the second test voltage VTS2 may be one of the voltages generated or used by the display device, respectively. In some embodiments, a maximum gamma voltage VG_TOP may be applied to the sources of the first transistors TR1_1 to TR1_6, and the sources of the second transistors TR2_1 to TR2_6 may be grounded.

[0122] Two signals complementary to each other may be input to the gates of the first transistors TR1_1 to TR1_6 and the gates of the second transistors TR2_1 to TR2_6. For example, the non-enable signals / EN1 to / EN3 may be input to the gates of the first transistors TR1_1 to TR1_6, and the enable signals EN1 to EN3 may be input to the gates of the second transistors TR2_1 to TR2_6.

[0123] The controller of the DDI may generate non-enable signals / EN1 to / EN6 and enable signals EN1 to EN6.

[0124] Reference Fig.11 and Fig.12, the controller may generate enable signals EN1 to EN3. The enable signals EN1 to EN3 may have different logic level transition times. For example, when the first enable signal EN1 changes from a first level (e.g., high) to a second level (e.g., low), the second enable signal EN2 may change from the second level to the first level. That is, the controller may generate enable signals EN1 to EN3, and the first levels of the enable signals EN1 to EN3 do not overlap with each other in the time domain. The enable signals EN1 to EN3 may have the same pulse width. The controller may generate non-enable signals / EN1 to / EN3 in a manner similar to that of generating enable signals EN1 to EN3.

[0125] When the first enable signal EN1 is changed from the second level to the first level and the first non-enable signal / EN1 is changed from the first level to the second level, a current may flow to the first gamma line GL1 due to a potential difference between a first test voltage VTS1 at the source of the first transistor TR1_1 and a second test voltage VTS2 at the source of the second transistor TR2_1. In addition, a current may flow to the second gamma line GL2 due to a potential difference between a first test voltage VTS1 at the source of the first transistor TR1_2 and a second test voltage VTS2 at the source of the second transistor TR2_2. The controller may measure the sum of the currents flowing to the first gamma line GL1 and the second gamma line GL2. The controller may determine whether the first gamma line GL1 and the second gamma line GL2 have a defect based on the measured current and a reference current range.

[0126] When the controller measures Fig. 9 The current of one of the gamma lines in the Fig.11 When the current of the two gamma lines in Fig. 9 The reference current range can be Fig.11 The reference current range is different in . For example, Fig. 9 The reference current range can be lower than Fig.11 The reference current range is .

[0127] The controller may calculate the combined resistance of the first gamma line GL1 and the second gamma line GL2 based on the measured current and the potential difference between the first test voltage VTS1 and the second test voltage VTS2. The controller may determine whether the first gamma line GL1 and the second gamma line GL2 have a defect based on the calculated resistance and the reference resistance range. The controller may determine whether the remaining gamma lines GL3 to GL6 have a defect in a similar manner to the first gamma line GL1 and the second gamma line GL2.

[0128] In some embodiments, the test apparatus may determine at least one of a current and a resistance of the gamma lines GL1 to GL6 , and may determine whether the gamma lines GL1 to GL6 have a defect based on at least one of the determined current value and resistance.

[0129] Fig.11 and Fig.12 It is shown that the same enable signal (e.g., EN1) and non-enable signal (e.g., / EN1) are applied to two gamma lines (e.g., GL1 and GL2), and the current or resistance of the two gamma lines is measured, but the embodiment is not limited thereto, and the controller can measure the current or resistance of at least three gamma lines. That is, the time for screening DDI can be reduced by testing the gamma lines at the same time.

[0130] Fig.13 A block diagram illustrating an example of a display driver integrated circuit.

[0131] Reference Fig.13 , the display driving integrated circuit 1000 may include a gamma voltage generator 1005 , a source driver 1050 , first transistors TR1 to TRS, and second transistors TS1 to TSP.

[0132] The gamma voltage generator 1005 may generate voltages VH_1 to VH_P based on a maximum gamma voltage VG_TOP and a minimum gamma voltage VG_BOT. The voltages VH_1 to VH_P generated by the gamma voltage generator 1005 may be input to the source driver 1050 as gamma voltages. The gamma voltage generator 1005 may include a first resistor string 1010, decoders 1021 to 1024, amplifiers 1031 to 1034, and a second resistor string 1040. According to an embodiment, the gamma voltage generator 1005 may further include at least one resistor string, at least one decoder, and at least one amplifier. Figure 8 The description of the first resistor string 710, decoders 721 to 724, amplifiers 731 to 734, and second resistor string 740 shown in FIG. 1 is identically applicable to the first resistor string 1010, decoders 1021 to 1024, amplifiers 1031 to 1034, and second resistor string 1040. Therefore, a repeated description will not be provided.

[0133] The source driver 1050 may generate a data signal based on the voltages VH_1 to VH_P. The source driver 1050 may output the voltages VL1 to VL8 as the data signal. The source driver 1050 may include a decoder and a source amplifier connected to the decoder. Figure 5 The description of the source driver 320 may be equally applicable to the source driver 1050 .

[0134] The first transistors TR1 to TRS and the second transistors TS1 to TSP may have different types of transistors. For example, the first transistors TR1 to TRS may be PMOS transistors, and the second transistors TS1 to TSP may be NMOS transistors.

[0135] The first transistors TR1 to TRS and the second transistors TS1 to TSP may be arranged at respective ends of the gamma line. For example, the first transistors TR1 to TRS may be arranged at the front end of the gamma line (e.g., a portion of the gamma line between the gamma voltage generator 1005 and the source driver 1050), and the second transistors TS1 to TSP may be arranged at the rear end of the gamma line (e.g., a portion of the gamma line after the source driver 1050).

[0136] The first transistors TR1 to TRS may be connected to the corresponding gamma line through the drain. The first transistors TR1 to TRS may receive the first voltage VRE through the source. The second transistors TS1 to TSP may be connected to the corresponding gamma line through the drain. The second transistors TS1 to TSP may receive the second voltage VRF through the source.

[0137] Two signals complementary to each other may be input to the gates of the first transistors TR1 to TRS and the gates of the second transistors TS1 to TSP. For example, a non-enable signal / EN may be input to the gates of the first transistors TR1 to TRS, and an enable signal EN may be input to the gates of the second transistors TS1 to TSP. Therefore, the first transistors TR1 to TRS and the second transistors TS1 to TSP may become turned on, and current may flow.

[0138] The resistance components of each gamma line used to connect the gamma voltage generator 1005 and the source driver 1050 may be different from each other. Different voltage drops can be generated by the current flowing to the gamma line and the different resistance components. That is, the source driver 1050 can receive an abnormal voltage among the voltages VH_1 to VH_P, and can generate an abnormal voltage among the voltages VL1 to VL8 based on the received abnormal voltage. When one or more of the voltages VL1 to VL8 deviate from the reference voltage range, the display driver integrated circuit 1000 can determine that the gamma line is bad. When none of the voltages VL1 to VL8 deviates from the reference voltage range, the display driver integrated circuit 1000 can determine that the gamma line is normal. The first transistors TR1 to TRS and the second transistors TS1 to TSP become conductive based on the first voltage VRE, the second voltage VRF, the non-enable signal / EN and the enable signal EN, so the gamma lines can be tested at the same time and the screening time can be reduced.

[0139] In some embodiments, the display driving integrated circuit 1000 may not measure the voltages VL1 to VL8 , and an external test device may be connected to the source driver 1050 , may measure the voltages VL1 to VL8 , and may determine whether the gamma lines are normal.

[0140] Fig.14 A flow chart showing an example of a method for testing gamma lines.

[0141] Reference Fig.14 , the test device may determine whether the gamma line of the DDI may have a defect. The gamma line may be connected to two transistors of different types. For example, a PMOS transistor may be connected to the front end of the gamma line, and an NMOS transistor may be connected to the back end of the gamma line. The drains of the PMOS transistor and the NMOS transistor may be connected to the gamma line. The portion of the gamma line before the source driver may be referred to as the front end, and the portion of the gamma line after the source driver may be referred to as the back end.

[0142] A configuration will now be described in which a test device determines whether a first gamma line GL1 from among the gamma lines has a defect. The description of the first gamma line GL1 may be equally applicable to other gamma lines among the gamma lines that are not the first gamma line GL1. The test device may be incorporated into a controller in the DDI, or may be arranged outside the DDI.

[0143] The test device may apply a first test voltage VTS1 to the first transistor TR1 and a second test voltage VTS2 to the second transistor TR2 (S1010). The test device may apply voltages to the sources of the first transistor TR1 and the second transistor TR2. In some embodiments, the first test voltage VTS1 may be a maximum gamma voltage (e.g., Figure 2 In some embodiments, the second test voltage VTS2 may be a ground voltage. In some embodiments, the test device may control the power supply to apply the first test voltage VTS1 and the second test voltage VTS2 to the first transistor TR1 and the second transistor TR2.

[0144] The test device may send a non-enable signal / EN to the first transistor TR1, and may send an enable signal EN to the second transistor TR2 (S1020). The non-enable signal / EN may be an inverted signal of the enable signal EN. The test device may send a signal to the gates of the first transistor TR1 and the second transistor TR2. The first transistor TR1 may become a conductive state based on the second level (e.g., low) of the non-enable signal / EN. The second transistor TR2 may become a conductive state based on the first level (e.g., high) of the enable signal EN. That is, the first transistor TR1 and the second transistor TR2 may become a conductive state at the same time. When the first transistor TR1 and the second transistor TR2 are in a conductive state, the current IG1 may flow to the first gamma line GL1 based on the resistance component of the first gamma line GL1 and the potential difference between the first test voltage VTS1 and the second test voltage VTS2.

[0145] The test apparatus may measure the current IG1 of the first gamma line GL1 ( S1030 ).

[0146] The test device may determine whether the first gamma line GL1 has a defect (S1040). The test device may determine whether the first gamma line GL1 has a defect based on the current value of the current IG1 and the reference current range. For example, when the current value is within the reference current range, the test device may determine that the first gamma line GL1 is normal, and when the current value deviates from the reference current range, the test device may determine that the first gamma line GL1 is abnormal.

[0147] In some embodiments, the test device may calculate the resistance of the first gamma line GL1 based on the current value of the current IG1. For example, the test device may calculate the resistance of the first gamma line GL1 based on the potential difference between the first test voltage VTS1 and the second test voltage VTS2 and the current value of the current IG1. The test device may determine whether the first gamma line GL1 has a defect based on the calculated resistance and the reference resistance range.

[0148] Fig.15 An example of a semiconductor system is shown.

[0149] Reference Fig.15 , the semiconductor system 1200 may include a processor 1210 , a memory 1220 , a display device 1230 , and a peripheral device 1240 that are electrically connected to a system bus 1250 .

[0150] The processor 1210 may control data input / output of the memory 1220 , the display device 1230 , and the peripheral device 1240 , and may perform image processing on image data transmitted between corresponding devices.

[0151] The display device 1230 includes a display driver IC (DDI) 1231 and a display panel (DP) 1232, and the display device 1230 may store image data applied through the system bus 1250 in a frame memory included in the DDI 1231, and may display the image data on the display panel 1232. Figures 1 to 14 The described DDI may be combined with the DDI 1231. That is, the DDI 1231 may determine the current or resistance of the gamma line connected to the source driver. The DDI 1231 may determine the current or resistance by using two transistors connected to the corresponding gamma line. The DDI 1231 may determine whether the gamma line has a defect based on the determined current or resistance. When the DDI 1231 includes a gamma line with a defect, the DDI 1231 is screened, so that the DDI 1231 without the defect may be used to display an image, and the display device 1230 may display a high-quality image.

[0152] The peripheral device 1240 may convert a video or still image produced by a camera, a scanner, or a webcam into an electrical signal. Image data obtained by the peripheral device 1240 may be stored in the memory 1220 or may be displayed on the display panel 1232 in real time.

[0153] The memory 1220 may include a volatile memory such as a dynamic random access memory (DRAM) and / or a non-volatile memory such as a flash memory. The memory 1220 may be constructed using DRAM, a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), a NOR flash memory, a NAND flash memory, and a fusion flash memory (e.g., a memory in which a static random access memory (SRAM) buffer, a NAND flash memory, and a NOR interface logic are combined). The memory 1220 may store image data obtained from the peripheral device 1240 or a video signal processed by the processor 1210.

[0154] The semiconductor system 1200 may be installed in a mobile electronic product such as a smart phone, and without being limited thereto, the semiconductor system 1200 may be installed in various types of electronic products for displaying an image.

[0155] In some embodiments, reference Figures 1 to 15 The described respective constituent elements or a combination of two or more constituent elements may be implemented by a digital circuit, a programmable or non-programmable logic device or array, or an application specific integrated circuit (ASIC).

[0156] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope of protection that can be claimed, but rather as descriptions of features that can be specific to a particular embodiment of a particular invention. Specific features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as working in a particular combination, one or more features from the combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0157] While the disclosure has been described in conjunction with exemplary embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display driver integrated circuit, comprising: A gamma voltage generator is configured to: generate a plurality of gamma voltages; a source driver configured to: generate a plurality of data signals based on the plurality of gamma voltages; a plurality of gamma lines connecting the gamma voltage generator and the source driver, the plurality of gamma lines being configured to transmit the plurality of gamma voltages; a first transistor connected to a first end of a first gamma line among the plurality of gamma lines, the first transistor comprising a first gate configured to receive a first signal; as well as A second transistor is connected to the second end of the first gamma line, and includes a second gate configured to receive a second signal, wherein the first signal and the second signal are complementary to each other.

2. The display driver integrated circuit according to claim 1, wherein A first end of the first gamma line includes a front end between the gamma voltage generator and the source driver, and a second end of the first gamma line includes a rear end after the source driver, A first transistor is connected to the front end, and The second transistor is connected to the back end.

3. The display driver integrated circuit according to claim 1, wherein The first transistor and the second transistor are different types of transistors.

4. The display driver integrated circuit according to claim 3, wherein A drain of the first transistor and a drain of the second transistor are connected to a first gamma line.

5. The display driver integrated circuit according to claim 1, comprising: The controller is configured to apply an enable signal to the second transistor and a disable signal to the first transistor, the disable signal being an inverted signal of the enable signal.

6. The display driver integrated circuit according to claim 1, wherein The first transistor is configured to receive a first test voltage, and the second transistor is configured to receive a second test voltage through a source, and The first current is configured to flow to the first gamma line through the first test voltage, the second test voltage, and a resistance component between the first end and the second end of the first gamma line.

7. The display driver integrated circuit according to claim 6, comprising: The controller is configured to determine whether the first gamma line has a defect based on a current value of the first current.

8. The display driver integrated circuit according to claim 7, wherein The controller is configured to determine that the first gamma ray is normal based on the first current being within a reference current range, and to determine that the first gamma ray is abnormal based on the first current not being within the reference current range.

9. The display driver integrated circuit according to claim 7, wherein The controller is configured to determine a resistance of the resistance component based on a current value of the first current, and determine whether the first gamma line has a defect based on the resistance.

10. The display driver integrated circuit according to claim 9, wherein The controller is configured to determine that the first gamma ray is normal based on the resistance being within a reference resistance range, and to determine that the first gamma ray is abnormal based on the resistance not being within the reference resistance range.

11. The display driver integrated circuit according to claim 6, wherein The gamma voltage generator is configured to receive a maximum gamma voltage and a minimum gamma voltage, and generate the plurality of gamma voltages based on the maximum gamma voltage and the minimum gamma voltage, and The first transistor is configured to receive a maximum gamma voltage as a first test voltage.

12. The display driver integrated circuit according to any one of claims 1 to 11, wherein: The source driver includes: a plurality of decoders configured to: select a gamma voltage from among the plurality of gamma voltages; and a plurality of source amplifiers connected to the plurality of decoders, the plurality of source amplifiers being configured to: amplify the selected gamma voltage and output the amplified gamma voltage to the display panel, and Wherein, the plurality of gamma lines are connected to the plurality of decoders.

13. A display driver integrated circuit, comprising: A source driver configured to: generate a plurality of data signals based on a plurality of gamma voltages; a plurality of gamma lines configured to: send the plurality of gamma voltages to a source driver; a plurality of first transistors disposed at front ends of the plurality of gamma lines; as well as A plurality of second transistors are of a different type from the plurality of first transistors, and the plurality of second transistors are disposed at rear ends of the plurality of gamma lines.

14. The display driver integrated circuit according to claim 13, wherein The plurality of first transistors include a plurality of p-channel metal oxide semiconductor transistors, and The plurality of second transistors include a plurality of n-channel metal oxide semiconductor transistors.

15. The display driver integrated circuit according to claim 13, comprising a controller, wherein the controller is configured to: outputting an enable signal to a plurality of gates of the plurality of second transistors, outputting a non-enable signal to the plurality of gates of the plurality of first transistors, the non-enable signal being an inverted signal of the enable signal, and Based on the plurality of current values ​​of the plurality of gamma lines, it is determined whether the plurality of gamma lines have defects.

16. The display driver integrated circuit according to claim 15, wherein The controller is configured to generate a plurality of enable signals having the same pulse width and having a plurality of first levels that do not overlap with each other in a time domain, and output the plurality of enable signals to the plurality of gates of the plurality of second transistors.

17. The display driver integrated circuit according to claim 16, wherein The controller is configured to output a plurality of different enable signals to the plurality of second transistors, respectively, and determine whether the plurality of gamma lines have defects based on the plurality of current values ​​of the plurality of gamma lines.

18. The display driver integrated circuit according to claim 16, wherein The controller is configured to: output the same enable signal to at least two second transistors among the multiple second transistors, and determine whether the at least two gamma lines have defects based on at least two current values ​​of the at least two gamma lines among the multiple gamma lines, and the at least two gamma lines among the multiple gamma lines correspond to the at least two second transistors.

19. A method for testing a defect of a gamma line, the gamma line being sequentially connected to a first transistor, a source driver, and a second transistor, the method comprising: applying a first test voltage to the first transistor; applying a second test voltage to the second transistor; sending an enable signal to the gate of the second transistor; Sending a non-enable signal to the gate of the first transistor, the non-enable signal being an inverted signal of the enable signal; obtaining a current value of a current flowing to a gamma line; as well as Whether the gamma line has a defect is determined based on the current value.

20. The method according to claim 19, wherein: The steps to determine whether the gamma line is defective include: determining that the gamma line is normal based on the current value being within the reference current range; and The gamma ray abnormality is determined based on the current value not being within the reference current range.

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