Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascade arranged gate driving units, and each gate driving unit comprises a pull-up circuit, a pull-down circuit and an output circuit. The pull-up circuit comprises a first active switch and a first capacitor. The output end of the first active switch is connected to the output circuit. The input end of the first active switch is connected to a pull-up signal line. The control end of the first active switch is connected to one end of the first capacitor. The pull-up signal line is connected to the other end of the first capacitor. When there is a pull-up signal on the pull-up signal line, the first capacitor is charged, and the first active switch is turned on. When there is no pull-up signal on the pull-up signal line, the first active switch is turned off. The first capacitor is arranged to control the opening of the first active switch by charging the first capacitor, thereby improving the stability of the gate driving circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate drive circuit and a display panel. BACKGROUND

[0002] GOA (Gate Driver on Array) technology is the mainstream technology of the current display panel, which is conducive to further reducing the frame of the display panel to realize narrow frame or frameless. Among them, the gate drive circuit is mainly made to the array substrate by thin film deposition, and the shift register circuit is realized to realize the row-by-row scanning driving function of the display panel. In the traditional active matrix display, the row scanning signal is usually realized by external integrated circuit, and after using the panel GOA technology, the row scanning driving circuit is made by the same process as the thin film transistor (TFT), so as to realize the row-by-row scanning driving function.

[0003] However, for the pull-up circuit in the gate drive circuit, it is easy to be burned due to the large impedance caused by the via at the connection in the process of starting the gate drive circuit. SUMMARY

[0004] The purpose of the present application is to provide a gate drive circuit and a display panel, by setting a first capacitor, using the first capacitor to control the opening of the first active switch, avoiding the problem that when the pull-up signal is too large, the via connecting the control end and the input end of the first active switch is burned out, causing the gate drive unit to fail to work, and improving the stability of the gate drive circuit.

[0005] The present application discloses a gate drive circuit arranged on a substrate of a display panel, the gate drive circuit comprising a plurality of gate drive units arranged in cascade, the gate drive unit comprising a pull-up circuit, a pull-down circuit and an output circuit; the pull-up circuit comprising a first active switch and a first capacitor, the output end of the first active switch being connected to the output circuit, the input end of the first active switch being connected to a pull-up signal line, the control end of the first active switch being connected to one end of the first capacitor, the pull-up signal line being connected to the other end of the first capacitor; when there is a pull-up signal on the pull-up signal line, the first capacitor is charged, the first active switch is turned on, and when there is no pull-up signal on the pull-up signal line, the first active switch is turned off.

[0006] Optionally, the pull-up circuit further comprises a second active switch, an output terminal of the second active switch is connected to an output terminal of the first active switch, when the second active switch is turned on, the output terminal of the first active switch is pulled down to a potential when the first active switch is turned off; a control terminal of the second active switch is connected to the pull-down circuit, when the next stage of the gate drive unit outputs, the pull-down circuit of the next stage of the gate drive unit controls the second active switch of the current stage to turn on.

[0007] Optionally, the display panel comprises a substrate, a first metal layer and a second metal layer, the first metal layer is arranged on the substrate, the second metal layer is arranged on the first metal layer, and the second metal layer is insulated from the first metal layer; the input terminal and the output terminal of the first active switch are arranged in the second metal layer, and the control terminal of the first active switch is arranged in the first metal layer; the first capacitor comprises a first electrode and a second electrode, the first electrode is arranged in the first metal layer, and the second electrode is arranged in the second metal layer; the first electrode is connected to the control terminal of the first active switch, and the second electrode is connected to the input terminal of the first active switch and the pull-up signal line.

[0008] Optionally, in the first stage of the gate drive unit, the pull-up signal line comprises a frame start signal line, the pull-up circuit further comprises a connection line, the frame start signal line is arranged in the first metal layer, the connection line is arranged in the second metal layer, the frame start signal line is connected to the connection line through a via, and the input terminal of the first active switch is connected to the connection line; the connection line is further connected to the second electrode; wherein the pull-up signal is a frame start signal.

[0009] Optionally, in the nth stage of the gate drive unit, the pull-up signal line comprises a stage transmission signal line, the pull-up circuit comprises a third active switch, a control terminal and an input terminal of the third active switch are connected to the stage transmission signal line, wherein n is a natural number greater than 1, and the first active switch is arranged only in the first stage of the gate drive unit.

[0010] Optionally, in the first stage of the gate drive unit, the pull-up circuit further comprises a fourth active switch, an input terminal of the fourth active switch is connected to the connection line, a control terminal of the fourth active switch is connected to the connection line through a via, and an output terminal of the fourth active switch is connected to the output circuit.

[0011] Optionally, when the frame start signal line outputs a frame start signal, the first active switch and the fourth active switch are turned on at the same time, and the first stage of the gate drive unit outputs a scanning signal.

[0012] Optionally, a ground signal line is further arranged between the frame start signal line and the first active switch, and the connection line is connected with the frame start signal line across the ground signal line.

[0013] Optionally, the capacitance of the first capacitor is greater than or equal to 0.1 pF.

[0014] The application further discloses a display panel comprising a display substrate and a gate drive circuit as described above arranged on the display substrate, wherein the gate drive circuit is used for driving the display panel to display.

[0015] The application sets the first capacitor at the input end and the output end of the first active switch, so that one end of the first capacitor is connected to the control end of the first active switch, and the other end of the first capacitor is connected to the input end of the first active switch. When the pull-up circuit receives the pull-up signal on the pull-up signal line, the first capacitor is charged so that the voltage of the control end of the first active switch rises to a preset voltage, so that the first active switch is in a conductive state. When the gate drive unit does not output, the first active switch is controlled to be in a cut-off state by removing the pull-up signal. By setting the first capacitor, the via hole at the connection between the input end and the control end of the first active switch is omitted, so that the via hole at the connection between the input end and the control end of the first active switch is not burned by the pull-up signal output to the input end and the control end of the first active switch, and the gate drive circuit cannot work normally. By setting the first capacitor, the first active switch is controlled to be turned on by the charging of the first capacitor, so that the problem that the via hole at the connection between the control end and the input end of the first active switch is burned when the pull-up signal is too large, and the gate drive unit cannot work, is avoided, and the stability of the gate drive circuit is improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings included to provide a further understanding of the embodiments of the application, constitute a part of the specification and are used to explain the principles of the application together with the text. Obviously, the accompanying drawings in the following description only show some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort. In the drawings:

[0017] Figure 1 is a schematic diagram of a gate drive circuit of a first embodiment of the application;

[0018] Figure 2 is a schematic diagram of a film layer structure of a gate drive unit of the first embodiment of the application;

[0019] Figure 3 is a schematic diagram of an equivalent circuit of the gate drive unit of the first embodiment of the application;

[0020] Figure 4 is a schematic diagram of the n-th gate drive unit of the present application;

[0021] Figure 5 is a schematic diagram of the gate drive circuit of the second embodiment of the present application;

[0022] Figure 6 is an equivalent circuit schematic diagram of the gate drive unit of the second embodiment of the present application;

[0023] Figure 7 is a schematic diagram of the gate drive circuit of the third embodiment of the present application;

[0024] Figure 8 is an equivalent schematic diagram of the gate drive circuit of the third embodiment of the present application;

[0025] Figure 9 is a schematic diagram of the display panel of the present application.

[0026] Wherein, 100, gate drive circuit; 110, gate drive unit; 111, pull-up circuit; 112, pull-down circuit; 113, output circuit; 114, maintaining module; T1, first active switch; T2, second active switch; T3, third active switch; T4, fourth active switch; C1, first capacitor; 120, first metal layer; 121, first electrode; 130, second metal layer; 131, second electrode; 132, connection line; STV, frame start signal line; VSS, ground signal line; CLK, clock signal line; 200, display panel; 210, display substrate. DETAILED DESCRIPTION

[0027] It needs to be understood that the terms used herein, the specific structural and functional details disclosed, are only for the purpose of describing specific embodiments, and are representative, but the present application can be embodied in many alternative forms, and should not be interpreted as being limited to the embodiments set forth herein.

[0028] In the description of the present application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating relative importance, or implying the number of the indicated technical features. Therefore, unless otherwise specified, the features defined with "first", "second" can explicitly or implicitly include one or more of the features; the meaning of "multiple" is two or more. In addition, the terms indicating the orientation or position relationship such as "up", "down", "left", "right", "vertical", "horizontal", etc. are described based on the orientation or relative position relationship shown in the drawings, only for the convenience of the simplified description of the present application, and cannot be understood as indicating that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0029] The present application will be described in detail below with reference to the accompanying drawings and optional embodiments.

[0030] Figure 1 is a schematic diagram of a gate drive circuit of the first embodiment of the present application, Figure 2 is a schematic diagram of the film layer structure of the gate drive unit of the first embodiment of the present application, Figure 3 is a schematic diagram of the equivalent circuit of the gate drive unit of the first embodiment of the present application, referring to Figures 1 to 3 As shown in the figure, the present application discloses a gate drive circuit 100, which is arranged on a substrate of a display panel, and comprises a plurality of gate drive units 110 arranged in cascade, wherein each gate drive unit 110 comprises a pull-up circuit 111, a pull-down circuit 112 and an output circuit 113; the pull-up circuit 111 comprises a first active switch T1 and a first capacitor C1, the output end of the first active switch T1 is connected to the output circuit 113, the input end of the first active switch T1 is connected to a pull-up signal line, the control end of the first active switch T1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the pull-up signal line; when there is a pull-up signal on the pull-up signal line, the first capacitor C1 is charged, the first active switch T1 is turned on, and when there is no pull-up signal on the pull-up signal line, the first active switch T1 is turned off.

[0031] The application sets the first capacitor C1 at the input end and the output end of the first active switch T1, so that one end of the first capacitor C1 is connected to the control end of the first active switch T1, and the other end of the first capacitor C1 is connected to the input end of the first active switch T1. When the pull-up circuit 111 receives the pull-up signal on the pull-up signal line, the first capacitor C1 is charged so that the voltage of the control end of the first active switch T1 rises to a preset voltage, so that the first active switch T1 is in a conductive state. When the gate drive unit 110 does not output, the first active switch T1 is controlled to be in a cut-off state by removing the pull-up signal. By setting the first capacitor C1, the via hole at the connection between the input end and the control end of the first active switch T1 is omitted, preventing the via hole at the connection between the input end and the control end of the first active switch T1 from being burned by the pull-up signal during output to the input end and the control end of the first active switch T1, causing the gate drive circuit 100 to fail to work normally. By setting the first capacitor C1, the first capacitor C1 is charged to control the opening of the first active switch T1, avoiding the problem that the via hole connecting the control end and the input end of the first active switch T1 is burned when the pull-up signal is too large, causing the gate drive unit 110 to fail to work, and improving the stability of the gate drive circuit 100.

[0032] The main function of the pull-up circuit 111 is to improve the potential of the Q point, the output circuit 113 mainly outputs the scanning signal under the control of the Q point potential and the clock signal line CLK, the maintenance module 114 is mainly used to maintain the normal work of the gate drive unit 110, and the pull-down circuit mainly pulls down the Q point and the output signal of the output circuit of the gate drive unit.

[0033] The technology of setting the gate drive circuit 100 on the substrate substrate of the display panel is called GDL (Gate Driver Less) technology, also called GOA (Gate on Array) technology. It is a kind of shift register circuit on the array substrate, that is, it is formed by using film layer process on the substrate substrate, and realizes the row-by-row scanning driving function of the display panel. In the traditional active matrix display, the row scanning signal is usually realized by external integrated circuit, and after using the panel GDL technology, the row scanning driving circuit can be made by using the same process as the thin film transistor (TFT), so as to realize the row-by-row scanning driving function.

[0034] The first active switch T1 is also called a thin film transistor, which generally needs multiple film layers to be formed on a substrate, such as a gate, an active layer, a source, a drain, and the like. In general, the control end of the first active switch T1 is the gate of the thin film transistor, the output end of the first active switch T1 is the drain of the thin film transistor, and the input end of the first active switch T1 is the source of the thin film transistor. The gate, the source, and the drain are not located in the same layer, so when the pull-up signal line needs to be connected to the input end and the control end of the first active switch T1 at the same time, that is, the source and the gate which are not located in the same layer are connected at the same time, a via is needed to make the connection. At the position of the via, the source and the gate of different layers are generally connected by an electrode, and the number of vias corresponds to the impedance at this position. When the number of vias is large, the impedance at this position is small. However, due to the limited wiring space, in general, the number of vias is 2 to 4, which also has a large impedance. Therefore, when the pull-up signal is transmitted to the gate or the source of the first active switch T1 through the via, due to the excessive impedance and heat, the via may be burned out, thereby causing the gate drive circuit 100 to fail to work normally. Moreover, since the gate drive circuit 100 is outputted step by step, when the above problem occurs at a certain stage, the entire gate drive circuit 100 will fail to output.

[0035] Specifically, the display panel includes a substrate, a first metal layer 120, and a second metal layer 130. The first metal layer 120 is disposed on the substrate, and the second metal layer 130 is disposed on the first metal layer 120. The first metal layer 120 and the second metal layer 130 are insulated from each other, generally separated by an insulating material. Correspondingly, the thin film transistor disposed on the substrate uses the first metal layer 120 to form the gate of the thin film transistor, and uses the second metal layer 130 to form the source and the drain of the thin film transistor. The gate of the thin film transistor is generally the control end of the active switch, the source is generally the input end of the active switch, and the drain is generally the output end of the active switch.

[0036] In the gate drive circuit 100, in the pull-up circuit 111 of the gate drive unit 110, when the start signal is transmitted to the first active switch T1 in the pull-up circuit 111, the start signal is transmitted to the control end and the input end of the first active switch T1 respectively by setting the via hole to drive the first active switch T1 to output the signal to the Q point, and the Q point controls the output circuit 113 to output the scanning signal to the scanning line. However, when the voltage of the start signal is large and the hole of the via hole is limited, the impedance at the position of the via hole is large, which causes the problem of burning the via hole. The Q point is a key node in the gate drive unit 110, the pull-up circuit 111 is used to raise the potential of the Q point, and the pull-down circuit 112 is used to lower the voltage of the Q point. That is, under the control of the pull-up circuit 111 and the output circuit 113, the output of the scanning signal is realized. Under the action of the pull-down circuit 112, the output circuit 113 no longer outputs the scanning signal. Generally, the output circuit 113 is also provided with a clock signal line CLK, and under the control of the Q point potential and the clock signal line CLK, the multiple rows of scanning lines output the scanning signal row by row.

[0037] In the embodiment, the first active switch T1 directly connected with the control end and the input end is not arranged in the pull-up circuit 111 of the gate drive unit 110, but the first active switch T1 is controlled to be turned on and turned off by the first capacitor C1. The two electrodes of the first capacitor C1 are respectively connected to the control end and the input end of the first active switch T1. When the capacitor is charged, the potential difference of the capacitor remains unchanged, so that the control end of the first active switch T1 also changes to the conduction voltage potential instantaneously, so that the first active switch T1 remains in the conduction state. The conduction voltage potential of the first active switch T1 is the threshold voltage of the first active switch T1. When the voltage of the control end of the first active switch T1 is greater than or equal to the threshold voltage, the first active switch T1 is turned on.

[0038] Specifically, the input end and the output end of the first active switch T1 are arranged in the second metal layer 130, and the control end of the first active switch T1 is arranged in the first metal layer 120; the first capacitor C1 includes a first electrode 121 and a second electrode 131, the first electrode 121 is arranged in the first metal layer 120, and the second electrode 131 is arranged in the second metal layer 130; the first electrode 121 is connected to the control end of the first active switch T1, and the second electrode 131 is connected to the input end of the first active switch T1 and the pull-up signal line. In the embodiment, the input end of the first active switch T1 is connected to one side electrode of the first capacitor C1, and the electrode is also connected to the pull-up signal line. When the pull-up signal exists in the pull-up signal line, the pull-up signal changes the control end of the first active switch T1 to the conduction voltage potential through the first capacitor C1, so that the pull-up signal is output from the input end of the first active switch T1 to the Q point.

[0039] In an embodiment, taking the first-stage gate drive unit 110 as an example, in the first-stage gate drive unit 110, the pull-up signal line includes a frame start signal line STV, the pull-up circuit 111 further includes a connection line 132, the frame start signal line STV is arranged in the first metal layer 120, the connection line 132 is arranged in the second metal layer 130, the frame start signal line STV is connected to the connection line 132 through a via, and the input end of the first active switch T1 is connected to the connection line 132; the connection line 132 is further connected to the second electrode 131; wherein the pull-up signal is a frame start signal.

[0040] Generally, in the gate drive circuit 100, the pull-up circuit 111 of the first-stage, second-stage, and the like gate drive unit 110 needs to be controlled through the frame start signal line STV, and the gate drive unit 110 of other stages is output by the first-stage or the second-stage gate drive unit 110. Generally, the stage transmission signal between the two-stage gate drive unit 110 is generally not connected through a via, so that the first capacitor C1 does not need to be arranged. Therefore, the first capacitor C1 of the embodiment is arranged only in the first-stage, second-stage, and the like gate drive unit 110 which needs to be controlled through the frame start signal line STV. Of course, the gate drive unit 110 of other stages can be designed according to actual conditions.

[0041] Specifically, the frame start signal line STV and the first active switch T1 are further provided with a ground signal line VSS, and the connection line 132 is connected to the frame start signal line STV across the ground signal line VSS. Of course, the clock signal line CLK and the like mentioned above are needed to be connected to the multi-stage gate drive unit 110. Therefore, the clock signal line CLK is generally arranged on the side of the frame start signal line STV which is closer to the first active switch T1, so as to reduce the parasitic capacitance and impedance caused by the cross-line.

[0042] Figure 4 is a schematic diagram of the n-th stage gate drive unit of the application, referring to Figure 4 Specifically, in the n-th stage gate drive unit 110, the pull-up signal line includes a stage transmission signal line, and the pull-up circuit 111 includes a third active switch T3, the control end and the input end of the third active switch T3 are connected to the stage transmission signal line, wherein n is a natural number greater than 1, and the first active switch T1 is arranged only in the first-stage gate drive unit 110.

[0043] In the embodiment, the main consideration is that the stage transmission signal on the stage transmission signal line is different from the frame start signal, and the burnout problem of the frame start signal does not exist. Therefore, the first capacitor C1 can not be arranged in the other stage gate drive units 110, so as to reduce the cost. Of course, the other stage gate drive units 110 can also be protected, and the first capacitor C1 can also be arranged synchronously in the pull-up circuit 111 of each stage gate drive circuit 100.

[0044] In an embodiment, the pull-up circuit 111 further comprises a second active switch T2, an output end of the second active switch T2 is connected to an output end of the first active switch T1, and when the second active switch T2 is turned on, the potential of the output end of the first active switch T1 is pulled down to the potential when the first active switch T1 is turned off; a control end of the second active switch T2 is connected to the pull-down circuit 112, and when the next stage gate drive unit 110 outputs, the pull-down voltage Qb output by the pull-down circuit 112 of the next stage gate drive unit 110 controls the second active switch T2 of the current stage to be turned on.

[0045] In the embodiment, by arranging the second active switch T2, when the current row scanning line is scanned and turned off, the potential at the Q point is released by controlling the second active switch T2. At this time, the frame start signal on the frame start signal line STV is also low, and at this time, the voltage at the control end of the first active switch T1 is pulled down to be lower than the turn-on voltage mentioned above by the capacitive coupling effect of the first capacitor C1, so that the first active switch T1 is in the off state. Thus, the control of the pull-up circuit 111 of the gate drive unit 110 is realized, and the frame start signal is no longer output to the Q point.

[0046] It is worth mentioning that in actual setting, the control end of the second active switch T2 of the current stage gate drive unit 110 can also be connected to the pull-down circuit 112 of the next two stage gate drive units 110, and does not need to be limited to the next stage gate drive unit 110.

[0047] Of course, on the basis of the above-mentioned second active switch T2, an additional second active switch T2 can also be added, the input end and the control end of the second active switch T2 are connected in the same way as the above-mentioned second active switch T2, but the output end of the second active switch T2 is connected to the control end of the first active switch T1, and when the second active switch T2 is turned on, the voltage at the control end of the first active switch T1 is released, so as to better turn off the first active switch T1.

[0048] Figure 5 is a schematic diagram of a gate drive circuit of a second embodiment of the application, Figure 6is an equivalent circuit schematic diagram of the gate drive unit of the second embodiment of the present application, referring to Figures 5 to 6 As shown in the figure, in the present embodiment, the present application further discloses another gate drive circuit 100, which is arranged on a substrate of a display panel, and comprises a plurality of cascaded gate drive units 110, each of which comprises a pull-up circuit 111, a pull-down circuit 112 and an output circuit 113. The pull-up circuit 111 comprises a first capacitor C1, and does not comprise a first active switch T1, but directly raises the potential of the Q point through coupling of the first capacitor C1. When there is a pull-up signal on the pull-up signal line, the first capacitor C1 is charged to output a frame start signal to the Q point.

[0049] In the present embodiment, the frame start signal is directly coupled to the Q point, and the circuit design is relatively simple, but there is a problem of shutdown delay. For example, in the above embodiment, the second active switch T2 is added, and when the current gate drive unit 110 needs to stop output, the second active switch T2 is used to release the electric quantity in the first capacitor C1. In the present embodiment, the capacity of the first capacitor C1 needs to be relatively large, at least greater than or equal to 10 pF. In the first embodiment, the capacity of the first capacitor C1 is greater than or equal to 0.1 pF.

[0050] Figure 7 is a schematic diagram of the gate drive circuit of the third embodiment of the present application, Figure 8 is an equivalent schematic diagram of the gate drive circuit of the third embodiment of the present application, referring to Figures 7 to 8As shown in the embodiment, the application further discloses a gate drive circuit 100 arranged on a substrate of a display panel, the gate drive circuit 100 comprising a plurality of gate drive units 110 arranged in cascade, the gate drive unit 110 comprising a pull-up circuit 111, a pull-down circuit 112 and an output circuit 113; the pull-up circuit 111 comprising a first active switch T1 and a first capacitor C1, an output end of the first active switch T1 being connected to the output circuit 113, an input end of the first active switch T1 being connected to a pull-up signal line, a control end of the first active switch T1 being connected to one end of the first capacitor C1, the pull-up signal line being connected to the other end of the first capacitor C1; in the first stage gate drive unit 110, the pull-up signal line comprises a frame start signal line STV, the pull-up circuit 111 further comprising a connecting line 132, the frame start signal line STV being arranged in the first metal layer 120, the connecting line 132 being arranged in the second metal layer 130, the frame start signal line STV being connected to the connecting line 132 through a via, the input end of the first active switch T1 being connected to the connecting line 132; the connecting line 132 being further connected to the second electrode 131; wherein the pull-up signal is a frame start signal.

[0051] In the first stage gate drive unit 110, the pull-up circuit 111 further comprising a fourth active switch T4, an input end of the fourth active switch T4 being connected to the connecting line 132, a control end of the fourth active switch T4 being connected to the connecting line 132 through a via; an output end of the fourth active switch T4 being connected to the output circuit 113. When the pull-up signal line has the pull-up signal, the first capacitor C1 is charged, the first active switch T1 is turned on, when the pull-up signal line has no pull-up signal, the first active switch T1 is turned off.

[0052] In this embodiment, by adding a fourth active switch T4 to the first embodiment, the control end of the fourth active switch T4 is connected to the input end through a via, and is connected to the connection line 132, which is connected to the frame start signal line STV after crossing the ground signal line VSSVSS and the clock signal line CLK. In this scheme, the first active switch T1 and the fourth active switch T4 work together. When the frame start signal line STV outputs the frame start signal, the first active switch T1 and the fourth active switch T4 are turned on at the same time, and the first-stage gate drive unit 110 outputs the scan signal. Moreover, importantly, in the case that the fourth active switch T4 cannot work normally due to via burnout, the first active switch T1 can still be normally started through the action of the first capacitor C1, so as to improve the working stability of the gate drive circuit 100. It is worth mentioning that the other schemes in the first embodiment are also applicable to the third embodiment, and will not be described here.

[0053] Figure 9 is a schematic view of a display panel of the present application, as shown in Figure 9 The present application also discloses a display panel, which comprises a display substrate 210 and a gate drive circuit 100 arranged on the display substrate, wherein the gate drive circuit 100 is used for driving the display panel to display.

[0054] The present application sets the first capacitor C1 at the input end and the output end of the first active switch T1, so that one end of the first capacitor C1 is connected to the control end of the first active switch T1, and the other end of the first capacitor C1 is connected to the input end of the first active switch T1. When the pull-up circuit 111 receives the pull-up signal on the pull-up signal line, the first capacitor C1 is charged to make the voltage of the control end of the first active switch T1 rise to a preset voltage, so that the first active switch T1 is in a conductive state. When the gate drive unit 110 does not output, the first active switch T1 is controlled to be in a cut-off state by removing the pull-up signal. By setting the first capacitor C1, the via at the connection between the input end and the control end of the first active switch T1 is omitted, which prevents the via at the connection between the input end and the control end of the first active switch T1 from being burned by the pull-up signal during output to the input end and the control end of the first active switch T1, so that the gate drive circuit 100 cannot work normally. By setting the first capacitor C1, the first active switch T1 is controlled to be turned on by charging the first capacitor C1, which avoids the problem that the via connecting the control end and the input end of the first active switch T1 is burned when the pull-up signal is too large, so that the gate drive unit 110 cannot work, thereby improving the stability of the gate drive circuit 100, and the service life and stability of the display panel.

[0055] It should be noted that the inventive concept of the present application can form very many embodiments, but the length of the application file is limited and cannot list them one by one, so the above described embodiments or technical features can be combined to form new embodiments without conflict, and the combination of each embodiment or technical feature will enhance the original technical effect.

[0056] The above is a further detailed description of the present application in combination with specific optional embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the scope of protection of the present application.

Claims

1. A gate driving circuit disposed on a substrate of a display panel, the gate driving circuit comprising a plurality of cascaded gate driving units, characterized in that, The gate driving unit includes a pull-up circuit, a pull-down circuit, and an output circuit; The pull-up circuit includes a first active switch and a first capacitor. The output terminal of the first active switch is connected to the output circuit, the input terminal of the first active switch is connected to the pull-up signal line, the control terminal of the first active switch is connected to one end of the first capacitor, and the pull-up signal line is connected to the other end of the first capacitor. When a pull-up signal is present on the pull-up signal line, the first capacitor is charged and the first active switch is turned on; when no pull-up signal is present on the pull-up signal line, the first active switch is turned off. The display panel includes a substrate, a first metal layer, and a second metal layer. The first metal layer is disposed on the substrate, and the second metal layer is disposed on the first metal layer. The second metal layer is insulated from the first metal layer. The input and output terminals of the first active switch are disposed within the second metal layer, and the control terminal of the first active switch is disposed within the first metal layer. The first capacitor includes a first electrode and a second electrode, wherein the first electrode is disposed within the first metal layer and the second electrode is disposed within the second metal layer; The first electrode is connected to the control terminal of the first active switch, and the second electrode is connected to the input terminal of the first active switch and the pull-up signal line.

2. The gate driving circuit according to claim 1, characterized in that, The pull-up circuit also includes a second active switch, the output terminal of which is connected to the output terminal of the first active switch. When the second active switch is turned on, it is used to pull down the potential of the output terminal of the first active switch to the potential when the first active switch is turned off. The control terminal of the second active switch is connected to the pull-down circuit. When the gate driving unit of the next stage outputs, the pull-down circuit of the gate driving unit of the next stage controls the second active switch of the current stage to turn on.

3. The gate driving circuit according to claim 1, characterized in that, In the first-stage gate driving unit, the pull-up signal line includes a frame start signal line, and the pull-up circuit also includes a connecting line. The frame start signal line is disposed in the first metal layer, and the connecting line is disposed in the second metal layer. The frame start signal line is connected to the connecting line through a via. The input terminal of the first active switch is connected to the connecting line. The connecting line is also connected to the second electrode. The pull-up signal is a frame start signal.

4. The gate driving circuit according to claim 1, characterized in that, Within the nth stage gate driving unit, the pull-up signal line includes a stage transmission signal line, and the pull-up circuit includes a third active switch. The control terminal and input terminal of the third active switch are respectively connected to the stage transmission signal line. Where n is a natural number greater than 1, and the first active switch is only set in the gate driving unit of the first stage.

5. The gate driving circuit according to claim 3, characterized in that, Within the first-stage gate driving unit, the pull-up circuit further includes a fourth active switch. The input terminal of the fourth active switch is connected to the connection line, and the control terminal of the fourth active switch is connected to the connection line via a via. The output terminal of the fourth active switch is connected to the output circuit.

6. The gate driving circuit according to claim 5, characterized in that, When the frame start signal line outputs a frame start signal, the first active switch and the fourth active switch are simultaneously turned on, and the first-stage gate drive unit outputs a scan signal.

7. The gate driving circuit according to claim 3, characterized in that, A grounding signal line is also provided between the frame start signal line and the first active switch, and the connecting line crosses the grounding signal line and connects to the frame start signal line.

8. The gate driving circuit according to claim 1, characterized in that, The capacitance of the first capacitor is greater than or equal to 0.1pF.

9. A display panel, characterized in that, The display includes a display substrate and a gate driving circuit as described in any one of claims 1-8 disposed on the display substrate, wherein the gate driving circuit is used to drive the display panel to display.

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