Pixel circuit

Abstract

A pixel circuit includes a light emitting element, a capacitor, a driving transistor, a first write circuit, a second write circuit, a compensation circuit, a first transistor, and a second transistor. The light-emitting element is coupled to a first system voltage source. The capacitor is coupled to the first node and the second node. The driving transistor is coupled to a first node and a third node. The first write circuit writes a data voltage to the first node. The second write circuit writes an initial voltage to the second node and the third node, respectively. The compensation circuit compensates for the second node and raises the level of the first node through the capacitance. The first transistor is turned on in response to the driving signal and changes the level of the third node. The second transistor is turned on in response to the driving signal, the driving transistor is turned on through the levels of the third node and the first node, and a driving current is generated to lighten the light-emitting element.

Description

Technical Field

[0001] The present disclosure relates to a display device. Specifically, the present disclosure relates to a pixel circuit for compensating for the influence of resistance and capacitance. Background Art

[0002] In the existing display, the driving signal is sequentially sent to the active area (AA) of the panel by multiple shift registers on one side of the panel of the display, which is roughly equal to the view area (VA). However, the farther the pixel circuit is from the multiple shift registers, the more the current in the pixel circuit will be delayed or reduced due to the influence of the resistance and capacitance delay of the signal line of the driving signal, resulting in a decrease in the overall brightness of the panel or uneven brightness in some areas.

[0003] Therefore, the above technology still has many defects, and practitioners in this field need to develop other suitable pixel circuits. Summary of the invention

[0004] One aspect of the present disclosure relates to a pixel circuit. The pixel circuit includes a light-emitting element, a first capacitor, a driving transistor, a first writing circuit, a second writing circuit, a compensation circuit, a first transistor, and a second transistor. The light-emitting element is coupled to a first system voltage source. The first capacitor is coupled to a first node and a second node. The driving transistor is coupled to a first node and a third node. The first writing circuit is coupled to the first node, and is used to write a first level of a data voltage of a data line to the first node according to a first control signal in a first stage. The second writing circuit is coupled to the second node and the third node, and is used to write an initial voltage to the second node and the third node respectively according to a first control signal in a first stage. The compensation circuit is coupled to the second node, and is used to compensate a compensation voltage from an initial voltage of the second node according to a second control signal in a second stage, and to raise the first node from a first level of the data voltage to a second level through the first capacitor. The first transistor is coupled to the driving transistor, the third node, and the second system voltage source, and is used to be turned on in response to a driving signal in a third stage to change the initial voltage of the third node to the system voltage of the second system voltage source. The second transistor is coupled between the driving transistor and the light emitting element, and is used to respond to the driving signal to turn on in the third stage, so as to turn on the driving transistor through the system voltage and the second level of the first node, so as to generate a driving current between the first system voltage source and the second system voltage source, thereby lighting the light emitting element.

[0005] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present disclosure provides a pixel circuit technology that can improve the influence of the resistance and capacitance delay of the signal line to improve the overall brightness of the panel of the display device. In addition, the architecture of the pixel circuit of the present disclosure can reduce the system voltage requirement and maintain the panel brightness of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The content of the present disclosure may be better understood with reference to the embodiments in the following paragraphs and the following drawings:

[0007] Figure 1 is a circuit block diagram of a display device according to some embodiments of the present disclosure;

[0008] Figure 2 is a circuit block diagram of a pixel circuit according to some embodiments of the present disclosure;

[0009] Figure 3 is a signal timing diagram of a pixel circuit according to some embodiments of the present disclosure;

[0010] Figure 4 is a circuit state schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0011] Figure 5 is a circuit state schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0012] Figure 6 is a circuit state schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0013] Figure 7 is a circuit block diagram of a pixel circuit according to some embodiments of the present disclosure;

[0014] Figure 8 A circuit block diagram of a pixel circuit according to some embodiments of the present disclosure; and

[0015] Fig. 9 It is a circuit block diagram of a pixel circuit according to some embodiments of the present disclosure.

[0016] Description of reference numerals:

[0017] 10: Display device

[0018] AA: Viewing area

[0019] SR: Scratchpad register area

[0020] SL: Signal line

[0021] P1, P2: Position

[0022] 100,100A,100B,100C: Pixel circuit

[0023] COF1, COF2, COF3, COF4: driver chip

[0024] EM[1],EM[2],EM[n-2],EM[n-1],EM[n]: driving signal

[0025] SN[1],SN[2],SN[n-1],SN[n]: first control signal

[0026] EMC[n]: Second control signal

[0027] T1~T8,DT1,ATS: Transistor

[0028] C1, C2: capacitors

[0029] Vdata: data voltage

[0030] DL: Data Line

[0031] EM_Vgl: voltage level of compensation voltage

[0032] L: Light-emitting element

[0033] N1~N3:Node

[0034] 110, 110A, 110B, 110C: first writing circuit

[0035] 120, 120A, 120B, 120C: Second writing circuit

[0036] 130,130A,130B,130C: Compensation circuit

[0037] 140A, 140B: Balanced circuit

[0038] 150C: Detection circuit

[0039] SVDD, SVSS: system voltage source

[0040] VDD, VSS: system voltage

[0041] SDC: Direct current voltage source

[0042] DC: Direct current voltage

[0043] V N1 ,V N3 : Voltage level

[0044] Id: driving current

[0045] VH: High level

[0046] VL: Low level

[0047] I1: Display phase

[0048] I11~I13: Stage

[0049] ATS: Detection control signal

[0050] AT1: Detection transistor

[0051] R1, R2: Path DETAILED DESCRIPTION

[0052] The concept of the present disclosure will be clearly illustrated below with drawings and detailed descriptions. After understanding the embodiments of the present disclosure, any person skilled in the art can make changes and modifications based on the techniques disclosed in the present disclosure without departing from the concept and scope of the present disclosure.

[0053] The terms used herein are only for describing specific embodiments and are not intended to be limiting of the present disclosure. Singular forms such as "a", "an", "this", "this", and "the" as used herein also include plural forms.

[0054] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0055] Regarding the terms used in this article, unless otherwise noted, they generally have the ordinary meaning of each term used in this field, in the context of this disclosure and in the specific context. Certain terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the present disclosure.

[0056] Figure 1 FIG. 1 is a circuit block diagram of a display device 10 according to some embodiments of the present disclosure. Figure 1 The display device 10 includes a visible area AA of the panel, a register region SR where a plurality of shift registers are located, and a plurality of driver chips (e.g., driver chip COF1, driver chip COF2, driver chip COF3, and driver chip COF4). The register region SR is electrically connected to the driver chip COF1. The visible area AA of the panel includes a plurality of pixel circuits 100.

[0057] like Figure 1 As shown, the pixel circuit 100 at position P1 and the pixel circuit 100 at position P2 are pixel circuits of the same pixel column. Compared with the pixel circuit 100 at position P1, the pixel circuit 100 at position P2 is affected by the resistance and capacitance delay of the signal line SL. The circuit architecture of the pixel circuit 100 at position P1 is similar to that of the pixel circuit 100 at position P2.

[0058] The driving signal in the existing display is sequentially sent to the active area (AA) of the panel by multiple shift registers on one side of the panel of the display, which is roughly equal to the view area (VA). However, the farther the pixel circuit is from the multiple shift registers, the more the current in the pixel circuit will be delayed or reduced due to the influence of the resistance and capacitance delay of the signal line SL, resulting in a decrease in the overall brightness of the panel or uneven brightness in some areas. The subsequent content of this disclosure will describe how to improve the above problems.

[0059] Figure 2 FIG. 1 is a circuit block diagram of a pixel circuit 100 according to some embodiments of the present disclosure. Figure 2 , the pixel circuit 100 includes a light-emitting element L, a driving transistor DT1, a capacitor C1, a first writing circuit 110, a second writing circuit 120, a compensation circuit 130, a transistor T5 and a transistor T6. The first writing circuit 110 includes a transistor T1. The second writing circuit 120 includes a transistor T2 and a transistor T3. The compensation circuit 130 includes a transistor T4. Please take the top and right of the elements in the figure as the first end. The light-emitting element L includes a first end and a second end. The second end of the light-emitting element L is coupled to the system voltage source SVSS. The capacitor C1 includes a first end and a second end. The first end of the capacitor C1 is coupled to the node N2. The second end of the capacitor C1 is coupled to the node N1.

[0060] The driving transistor DT1 includes a first terminal, a second terminal and a control terminal. The first terminal of the driving transistor DT1 is coupled to the node N3 and the second terminal of the transistor T5. The second terminal of the driving transistor DT1 is coupled to the first terminal of the transistor T6. The control terminal of the driving transistor DT1 is coupled to the node N1.

[0061] The first write circuit 110 includes a transistor T1. The transistor T1 includes a first terminal, a second terminal and a control terminal. The first terminal of the transistor T1 is coupled to the node N1. The second terminal of the transistor T1 is coupled to the data line DL and receives the data voltage Vdata of the data line DL. The control terminal of the transistor T1 is used to receive a first control signal SN[n]. The transistor T1 is turned on in response to the first control signal SN[n].

[0062] The second write circuit 120 includes a transistor T2 and a transistor T3. The transistor T2 includes a first terminal, a second terminal and a control terminal. The first terminal of the transistor T2 is used to receive the initial voltage of the previous stage driving signal EM[n-2]. The second terminal of the transistor T2 is coupled to the second node N2. The control terminal of the transistor T2 is used to receive the first control signal SN[n]. The transistor T2 is turned on in response to the first control signal SN[n]. The transistor T3 includes a first terminal, a second terminal and a control terminal. The first terminal of the transistor T3 is coupled to the node N3, the first terminal of the driving transistor DT1 and the second terminal of the transistor T5. The second terminal of the transistor T3 is coupled to the node N2 and the second terminal of the transistor T2. The control terminal of the transistor T3 is used to receive the first control signal SN[n]. The transistor T3 is turned on in response to the first control signal SN[n].

[0063] The compensation circuit 130 includes a transistor T4. The transistor T4 includes a first terminal, a second terminal and a control terminal. The first terminal of the transistor T4 is used to receive a voltage level EM_Vgl of a compensation voltage. The voltage level EM_Vgl of the compensation voltage is a DC voltage. The second terminal of the transistor T4 is coupled to the second node N2. The control terminal of the transistor T4 is used to receive a second control signal EMC[n]. The transistor T4 is turned on in response to the second control signal EMC[n].

[0064] The transistor T5 includes a first terminal, a second terminal and a control terminal. The first terminal of the transistor T5 is coupled to the system voltage source SVDD. The second terminal of the transistor T5 is coupled to the node N3. The control terminal of the transistor T5 is used to receive the driving signal EM[n]. The transistor T5 is turned on in response to the driving signal EM[n]. The transistor T6 includes a first terminal, a second terminal and a control terminal. The first terminal of the transistor T6 is coupled to the second terminal of the driving transistor DT1. The second terminal of the transistor T6 is coupled to the first terminal of the light emitting element L. The control terminal of the transistor T6 is used to receive the driving signal EM[n]. The transistor T6 is turned on in response to the driving signal EM[n].

[0065] In one embodiment, the driving transistor DT1, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, and the transistor T6 can be implemented as P-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS). However, the types of the aforementioned multiple transistors can be set according to actual needs and are not limited to the embodiments of the present disclosure.

[0066] To make Figure 2 The operation of the pixel circuit 100 is easy to understand. Figures 3 to 6 . Figure 3 To illustrate some embodiments according to the present disclosure Figure 2Schematic diagram of signal timing of the pixel circuit 100 in the display phase I1. The display phase I1 consists of phases I11 to I13. Figures 4 to 6 FIG. 1 is a schematic diagram of a circuit state of a pixel circuit 100 according to some embodiments of the present disclosure.

[0067] It should be noted that Figure 3 The front-stage driving signal EM[n-2], the driving signal EM[n], the voltage level V N1 and voltage level V N3 The solid line signal is Figure 1 2 is a diagram showing the signal timing of the pixel circuit 100 at position P1. Figure 3 The front-stage driving signal EM[n-2], the driving signal EM[n], the voltage level V N1 and voltage level V N3 The dashed signal is Figure 1 2 . The signal timing of the pixel circuit 100 at position P2 is shown in FIG.

[0068] In some embodiments, see Figure 3 and Figure 4 , in stage I11 of display stage I1, the first control signal SN[n] and the previous drive signal EM[n-2] are at a low level VL. The second control signal EMC[n] and the drive signal EM[n] are at a high level VH. The first control signal SN[n] writes the data voltage Vdata of the data line DL to the second end of the capacitor C1 (i.e., node N1) through the transistor T1 of the first write circuit 110. The first control signal SN[n] writes the low level VL (i.e., initial voltage) of the previous drive signal EM[n-2] to the first end of the capacitor C1 (i.e., node N2) and node N3 through the transistor T2 and transistor T3 of the second write circuit 120. Here, the low level VL of the previous drive signal EM[n-2] is designed to be the same as the voltage level EM_Vgl of the compensation voltage. At this time, the voltage level of the node N1 changes as shown in FIG. Figure 3 The voltage level shown is V N1 The voltage level of node N3 changes as follows: Figure 3 The voltage level shown is V N3 .

[0069] In some embodiments, the data voltage Vdata can be implemented as 4V to 11V. It should be noted that the voltage value of the data voltage Vdata corresponds to different grayscale values. For example, the data voltage Vdata includes 256 grayscale voltages.

[0070] Please refer to Figure 1 , Figure 3 and Figure 4, relative to the pixel circuit 100 at position P1, the low level VL of the front-stage driving signal EM[n-2] written into the pixel circuit 100 at position P2 will be affected by the resistance and capacitance delay of the signal line SL and cannot be completely written. That is to say, the low level VL of the front-stage driving signal EM[n-2] is higher than the low level VL of the front-stage driving signal EM[n-2] of the pixel circuit 100 at position P1. For example, the low level VL of the front-stage driving signal EM[n-2] written into the pixel circuit 100 at position P1 is -5 volts (Volt). The low level VL of the front-stage driving signal EM[n-2] written into the pixel circuit 100 at position P2 is -4 volts (Volt).

[0071] In some embodiments, see Figure 3 and Figure 5 , in stage I12 of display stage I1, the second control signal EMC[n] and the previous drive signal EM[n-2] are at a low level VL. The first control signal SN[n] and the drive signal EM[n] are at a high level VH. At this time, the transistor T1 of the first write circuit 110, the transistor T2 of the second write circuit 120, and the transistor T3 are in a closed state. The second control signal EMC[n] compensates the first end of the capacitor C1 (i.e., the node N2) with a voltage level EM_Vgl of a compensation voltage through the transistor T4 of the compensation circuit 130. At the same time, the capacitor C1 changes the voltage level V of the node N1 in response to the change of the voltage level of the node N2. N1 .

[0072] At this time, the voltage level V N1 =Vdata+(EM_Vgl-VL)*C1 / Ctotal, where VL is the low level of the previous driving signal EM[n-2], and Ctotal is the equivalent total capacitance value of the single pixel circuit 100. The voltage level of the node N2 is the voltage level of the compensation voltage EM_Vgl. The voltage level of the node N3 is V N3 It is low level VL.

[0073] Please refer to Figure 1 , Figure 3 and Figure 5 , the voltage level V of the node N1 of the pixel circuit 100 at the position P1 N1 The voltage level V of the node N1 of the pixel circuit 100 at the position P2 is N1 =Vdata+(EM_Vgl-VL)*C1 / Ctotal. The voltage level of the node N2 of the pixel circuit 100 located at the position P2 is the voltage level of the compensation voltage EM_Vgl. The voltage level of the node N3 of the pixel circuit 100 located at the position P2 is V N3The low level VL of the delayed previous stage driving signal EM[n-2] is shown in FIG. Due to the voltage level EM_Vgl of the compensation voltage in phase I12, the pixel circuit 100 located at position P2 reduces the influence of the resistance and capacitance delay of the signal line SL.

[0074] In some embodiments, see Figure 3 and Figure 6 , in stage I13 of display stage I1, the driving signal EM[n] is at a low level VL. The first control signal SN[n], the second control signal EMC[n] and the previous driving signal EM[n-2] are at a high level VH. The driving signal EM[n] writes the voltage level VDD of the system voltage of the system voltage source SVDD to the node N3 through the transistor T5. The driving transistor T1 outputs a driving current Id to the light-emitting element L according to the driving voltage difference between the first end and the control end. The driving voltage difference between the first end and the control end of the driving transistor DT1 is equal to the voltage difference between the second end of the capacitor C1 (i.e., the node N1) and the node N3. The formula of the above driving current Id is as follows:

[0075] Id=K(VGS-Vth) 2 …Formula 1

[0076] In Formula 1, Id is the driving current, VGS is the voltage difference between the first terminal and the control terminal of the driving transistor DT1, and Vth is the threshold voltage of a single transistor. In this stage I13, the voltage level of the control terminal (i.e., node N1) of the driving transistor DT1 is (Vdata+(EM_Vgl-VL)*C1 / Ctotal). The voltage level of the first terminal of the driving transistor DT1 is (VDD). Substituting the voltage levels of the first terminal and the control terminal of the driving transistor DT1 into Formula 1, it can be obtained:

[0077]

[0078] Please refer to Figure 1 , Figure 3 and Figure 5 , the driving current Id of the pixel circuit 100 at position P1 is K(Vdata-VDD) 2 The driving current Id of the pixel circuit 100 at position P2 is The driving current Id of the pixel circuit 100 at the position P2 is greater than the driving current Id of the pixel circuit 100 at the position P1 to improve the influence of the resistance and capacitance delay of the signal line SL, thereby improving the overall brightness of the panel of the display device 10 .

[0079] Figure 71 is a circuit block diagram of a pixel circuit 100A according to some embodiments of the present disclosure. The pixel circuit 100A includes a light-emitting element L, a driving transistor DT1, a capacitor C1, a first writing circuit 110A, a second writing circuit 120A, a compensation circuit 130A, a balancing circuit 140A, a transistor T5, and a transistor T6. The first writing circuit 110A includes a transistor T1. The second writing circuit 120A includes a transistor T2 and a transistor T3. The compensation circuit 130A includes a transistor T4. The connection method and driving method of the light-emitting element L, the driving transistor DT1, the transistor T1 of the first writing circuit 110A, the transistors T2 and T3 of the second writing circuit 120A, and the transistor T4 of the compensation circuit 130A are similar to those of Figure 2 The corresponding components of the pixel circuit 100 are not described in detail here. Figure 2 The pixel circuit 100 and Figure 7 The structural differences between the pixel circuit 100A and the pixel circuit 100A are described.

[0080] Compared to Figure 2 The pixel circuit 100, Figure 7 The pixel circuit 100A further includes a balancing circuit 140A. The balancing circuit 140A includes a capacitor C2. The capacitor C2 includes a first end and a second end. The first end of the capacitor C2 is coupled to the control end of the driving transistor DT1 and the node N1. The second end of the capacitor C2 is coupled to the DC voltage DC of the DC voltage source SDC. The capacitor C2 is used to balance the coupling effect of the components in the pixel circuit 100A on the node N1 and reduce the demand for the system voltage VDD of the system voltage source SVDD.

[0081] Figure 8 1 is a circuit block diagram of a pixel circuit 100B according to some embodiments of the present disclosure. The pixel circuit 100B includes a light-emitting element L, a driving transistor DT1, a capacitor C1, a first writing circuit 110B, a second writing circuit 120B, a compensation circuit 130B, a balancing circuit 140B, a transistor T5, and a transistor T6. The first writing circuit 110B includes a transistor T1. The second writing circuit 120B includes a transistor T2 and a transistor T3. The compensation circuit 130B includes a transistor T4. The connection method and driving method of the light-emitting element L, the driving transistor DT1, the transistor T1 of the first writing circuit 110B, the transistors T2 and T3 of the second writing circuit 120B, and the transistor T4 of the compensation circuit 130B are similar to those of Figure 2 The corresponding components of the pixel circuit 100 are not described in detail here. Figure 2 The pixel circuit 100 and Figure 8 The structural differences between the pixel circuit 100B and the pixel circuit 100B are described.

[0082] Compared to Figure 2 The pixel circuit 100, Figure 8 The pixel circuit 100B further includes a balancing circuit 140B. The balancing circuit 140B includes a transistor T7. The transistor T7 includes a first end, a second end and a control end. The first end of the transistor T7 is coupled to the control end of the driving transistor DT1, the node N1 and the second end of the transistor T7. The control end of the transistor T7 is coupled to the DC voltage DC of the DC voltage source SDC. The transistor T7 is used to balance the coupling effect of the components in the pixel circuit 100A on the node N1. In addition, the usage of the first end and the second end of the transistor T7 is equivalent to a variable capacitor. The capacitance value of the variable capacitor is adjusted by changing the DC voltage DC of the DC voltage source SDC. The smaller the DC voltage DC connected to the control end of the transistor T7, the larger the capacitance value of the variable capacitor of the transistor T7. The larger the capacitance value of the transistor T7 as a variable capacitor, the lower the demand for the system voltage VDD of the system voltage source SVDD.

[0083] Fig. 9 1 is a circuit block diagram of a pixel circuit 100C according to some embodiments of the present disclosure. The pixel circuit 100C includes a light-emitting element L, a driving transistor DT1, a capacitor C1, a first writing circuit 110C, a second writing circuit 120C, a compensation circuit 130C, a detection circuit 150C, a transistor T5, and a transistor T6. The first writing circuit 110C includes a transistor T1. The second writing circuit 120C includes a transistor T2 and a transistor T3. The compensation circuit 130C includes a transistor T4. The connection method and driving method of the light-emitting element L, the driving transistor DT1, the transistor T1 of the first writing circuit 110C, the transistors T2 and T3 of the second writing circuit 120C, and the transistor T4 of the compensation circuit 130C are similar to those of Figure 2 The corresponding components of the pixel circuit 100 are not described in detail here. Figure 2 The pixel circuit 100 and Fig. 9 The structural differences between the pixel circuit 100C are described below.

[0084] Compared to Figure 2 The pixel circuit 100, Fig. 9The pixel circuit 100C further includes a detection circuit 150C. The detection circuit 150C includes a transistor T8 and a detection transistor AT1. The detection transistor AT1 includes a first end, a second end, and a control end. The first end of the detection transistor AT1 is coupled to the data line DL. The control end of the detection transistor AT1 is used to receive a detection control signal ATS. The detection transistor AT1 is used to turn on in response to the detection control signal ATS during the detection phase. The transistor T8 includes a first end, a second end, and a control end. The first end of the transistor T8 is coupled to the second end of the detection transistor AT1. The second end of the transistor T8 is coupled between the transistor T6 and the light-emitting element L. The control end of the transistor T8 is used to receive a drive signal EM[n]. The transistor T8 is turned on in response to the drive signal EM[n].

[0085] In one embodiment, the transistor T7, the transistor T8 and the detection transistor AT1 can be implemented as P-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS). However, the types of the aforementioned transistors can be set according to actual needs and are not limited to the embodiments of the present disclosure.

[0086] It should be noted that the driving method of the detection stage is similar to the driving method of the display stage I1, and will not be described in detail here. The difference between the detection stage and the display stage I1 is whether the detection control signal ATS is at a low level (not shown in the figure) to turn on the detection transistor AT1. In other words, the detection control signal ATS is at a high level (not shown in the figure) in the display stage I1.

[0087] Before the light emitting element L is connected to the pixel circuit 100C, a detection signal can be input from the system voltage source SVDD along the path R1, and the data line DL detects whether the detection signal from the system voltage source SVDD is received to detect the pixel circuit 100C.

[0088] When the light emitting element L is connected to the pixel circuit 100C and the driving transistor DT1 is not turned on, a detection signal can be input from the system voltage source SVSS along the path R2, and the data line DL end detects whether the detection signal from the system voltage source SVSS end is received to detect the connection status of the light emitting element L.

[0089] In some embodiments, the detection circuit 150C of the pixel circuit 100C may be applied to the pixel circuit 100 , the pixel circuit 100A, or the pixel circuit 100B.

[0090] According to the above embodiments, the present disclosure provides a pixel circuit. The technology of the pixel circuit disclosed in the present disclosure can improve the influence of the resistance and capacitance delay of the signal line to improve the overall brightness of the panel of the display device. In addition, the architecture of the pixel circuit disclosed in the present disclosure can reduce the system voltage requirement and maintain the panel brightness of the display device.

[0091] Although the present disclosure is disclosed in detail with the embodiments as above, the present disclosure does not exclude other feasible implementations. Therefore, the protection scope of the present disclosure shall be subject to the definition of the claims, rather than being limited by the aforementioned embodiments.

[0092] For those skilled in the art, various changes and modifications can be made to the present disclosure without departing from the concept and scope of the present disclosure. Based on the above embodiments, all changes and modifications made to the present disclosure are also included in the protection scope of the present disclosure.

Claims

1. A pixel circuit comprising: A light emitting element coupled to a first system voltage source; A first capacitor coupled to a first node and a second node; a driving transistor coupled to the first node and a third node; a first writing circuit coupled to the first node and used for writing a first level of a data voltage of a data line to the first node according to a first control signal in a first phase; a second writing circuit coupled to the second node and the third node and used for writing an initial voltage to the second node and the third node respectively according to the first control signal in the first stage; a compensation circuit coupled to the second node and used for compensating the second node from the initial voltage to a compensation voltage according to a second control signal in a second stage, and raising the first node from the first level of the data voltage to a second level through the first capacitor; a first transistor coupled to the driving transistor, the third node and a second system voltage source, and configured to be turned on in response to a driving signal in a third phase to change the initial voltage of the third node to a system voltage of the second system voltage source; as well as A second transistor is coupled between the driving transistor and the light-emitting element and is used to be turned on in response to the driving signal in the third stage, so as to turn on the driving transistor through the system voltage and the second level of the first node, so that a driving current is generated between the first system voltage source and the second system voltage source, thereby lighting the light-emitting element.

2. The pixel circuit according to claim 1, further comprising: A balancing circuit is coupled to the first node and a control terminal of the driving transistor and is used for balancing a coupling state of the first node.

3. The pixel circuit as claimed in claim 2, wherein the balancing circuit comprises: A second capacitor comprising: a first terminal coupled to the first node and the control terminal of the driving transistor; and A second terminal is coupled to a DC voltage source and is used for receiving a DC voltage from the DC voltage source.

4. The pixel circuit as claimed in claim 2, wherein the balancing circuit comprises: A balanced transistor comprising: a first terminal coupled to the control terminal of the driving transistor; a second terminal coupled to the first node and the first terminal of the balancing transistor; and A control terminal is coupled to a voltage source and is used to change an equivalent capacitance of the balancing transistor in response to a variable voltage of the voltage source.

5. The pixel circuit according to claim 1, further comprising: A detection circuit is coupled between the second transistor and the light emitting element and is used to respond to a detection control signal and the driving signal to be turned on in a detection phase to detect the pixel circuit or the light emitting element.

6. The pixel circuit as claimed in claim 5, wherein the detection circuit comprises: a third transistor, coupled between the second transistor and the light emitting element, and configured to be turned on in response to the driving signal during the detection phase; and A detection transistor is coupled to the third transistor and the data line and is used to be turned on in response to the detection control signal during the detection phase.

7. The pixel circuit as claimed in claim 1, wherein the first writing circuit comprises: a third transistor, comprising: a first terminal coupled to the first node; a second end coupled to the data line and used for receiving the data voltage of the data line; and A control terminal is used to receive the first control signal, wherein the third transistor is turned on in the first stage in response to the first control signal.

8. The pixel circuit as claimed in claim 1, wherein the second writing circuit comprises: a third transistor, comprising: A first terminal, for receiving the initial voltage; a second terminal coupled to the second node; and a control terminal for receiving the first control signal, wherein the third transistor is turned on in the first stage in response to the first control signal; and a fourth transistor, comprising: a first end, configured to receive the third node; a second terminal coupled to the second node; and A control terminal is used to receive the first control signal, wherein the fourth transistor is turned on in the first stage in response to the first control signal.

9. The pixel circuit as claimed in claim 1, wherein the compensation circuit comprises: a third transistor, comprising: A first terminal, used for receiving the compensation voltage; a second terminal coupled to the second node; and A control terminal is used to receive the second control signal, wherein the third transistor is turned on in the second stage in response to the second control signal.

10. The pixel circuit as claimed in claim 1, wherein the driving transistor comprises: a first terminal coupled to the third node; a second terminal coupled to the second transistor; and A control terminal is coupled to the first node, wherein the driving transistor is turned on in response to the system voltage and the second level of the first node in the third stage.

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