8T2C depletion type double-gate driving tube threshold voltage compensation circuit and method

Abstract

The invention relates to an 8T2C depletion type double-gate driving tube threshold voltage compensation circuit and method, belongs to the technical field of display, and solves the problems of complex control and unstable circuit in the prior art. Comprising a light emitting diode, a switch tube unit, a depletion type double-gate driving tube, a compensation capacitor and a storage capacitor, the drain of the first switch tube is connected with external initial voltage, and the source is connected with the top gate of the driving tube; the drain electrode of the second switch tube is connected with the source electrode of the driving tube. The source electrode is connected with one end of the compensation capacitor and ground. The source electrode of the third switch tube is connected with the drain electrode of the driving tube; the source electrode of the fourth switch tube is connected with the source electrode of the driving tube; the source of the fifth switch tube is connected with the bottom grid of the driving tube, and the drain is connected with data signals; the source electrode of the sixth switch tube is connected with the drain electrode of the driving tube; the drain electrode of the seventh switch tube is connected with the source electrode of the driving tube. The target of stable pixel compensation is achieved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an 8T2C depletion-type dual-gate drive tube threshold voltage compensation circuit and method. Background Art

[0002] Active organic light-emitting diode displays have become a strong candidate for the next generation of flat panel displays due to their excellent color characteristics, high contrast, and low power consumption.

[0003] Since active organic light-emitting diodes are current-controlled display devices, the stability and uniformity of the driving thin-film transistor are very important for achieving uniform brightness. The amorphous InGaZnO4 thin-film transistors currently used have high mobility, high transparency, low processing temperature and potential good uniformity. However, the instability of the threshold voltage limits the application of driving thin-film transistors in circuits. Since the threshold voltage of the driving thin-film transistor is sensitive to light and heat and may shift with time and environmental conditions, threshold voltage drift may occur in actual applications, which will affect the brightness and color uniformity of the display. Summary of the invention

[0004] In view of the above analysis, the embodiments of the present invention aim to provide an 8T2C depletion-type dual-gate driver threshold voltage compensation circuit and method to solve the problems of low average compensation rate, large number of clock signal lines and complex control in the prior art.

[0005] On the one hand, an embodiment of the present invention provides an 8T2C depletion-mode dual-gate driver threshold voltage compensation circuit, including:

[0006] An 8T2C depletion-type dual-gate drive tube threshold voltage compensation circuit, characterized in that it comprises: a light emitting diode, a switch tube unit, a depletion-type dual-gate drive tube, a compensation capacitor, and a storage capacitor; wherein the switch tube unit comprises first to seventh switch tubes;

[0007] The drain of the first switch tube is connected to the external initial voltage, and the source is connected to the top gate of the depletion-type dual-gate drive tube; the drain of the second switch tube is connected to the source of the depletion-type dual-gate drive tube, and the source is connected to one end of the compensation capacitor and the ground; the other end of the compensation capacitor is connected to the top gate of the depletion-type dual-gate drive tube; the source of the third switch tube is connected to the drain of the depletion-type dual-gate drive tube, and the drain is connected to the top gate of the depletion-type dual-gate drive tube; the source of the fourth switch tube is connected to the source of the depletion-type dual-gate drive tube and one end of the storage capacitor, and the drain is connected to the bottom gate of the depletion-type dual-gate drive tube and the other end of the storage capacitor; the source of the fifth switch tube is connected to the bottom gate of the depletion-type dual-gate drive tube, and the drain is connected to the data signal; the source of the sixth switch tube is connected to the drain of the depletion-type dual-gate drive tube, and the drain is connected to the power supply voltage; the drain of the seventh switch tube is connected to the source of the depletion-type dual-gate drive tube, and the source is connected to the anode of the light-emitting diode; the cathode of the light-emitting diode is grounded.

[0008] A further improvement based on the above scheme further includes first to sixth clock signals input from the outside; wherein,

[0009] The first clock signal controls the on and off of the first switch tube;

[0010] The second clock signal controls the on and off of the second switch tube;

[0011] The third clock signal controls the on and off of the third switch tube and the fourth switch tube;

[0012] The fourth clock signal controls the on and off of the fifth switch tube;

[0013] The data signal is input into the drain of the fifth switch tube;

[0014] The sixth clock signal controls the on and off of the sixth switch tube and the seventh switch tube.

[0015] Based on the further improvement of the above solution, the low voltage of the first to fourth and sixth clock signals is -5V, and the high voltage is 15V; the low voltage of the data signal is 0V, and the high voltage is 15V.

[0016] Based on the further improvement of the above solution, the power supply voltage and the external initial voltage are both DC voltages.

[0017] Based on the further improvement of the above solution, the first to seventh switch tubes are all N-type depletion-type transistors.

[0018] On the other hand, an embodiment of the present invention provides a 8T2C depletion-type dual-gate driver threshold voltage compensation method, which includes: an initialization stage, a compensation stage, a data input stage, and a light-emitting stage; wherein:

[0019] The initialization stage is used to set the initial state of the depletion-type dual-gate drive tube and the compensation capacitor based on the external initial voltage; and discharge the storage capacitor;

[0020] The compensation stage is used to short-circuit the bottom gate and source, as well as the top gate and drain of the depletion-type dual-gate driver tube to achieve compensation for the threshold voltage;

[0021] The data input stage is used to charge the bottom gate and storage capacitor of the depletion-type dual-gate drive tube based on the data signal;

[0022] The light-emitting stage is used to turn on the depletion-type dual-gate drive tube to obtain the driving current of the light-emitting diode and drive the light-emitting diode to emit light.

[0023] Based on the further improvement of the above method, the initialization stage includes:

[0024] The first clock signal and the second clock signal are at high levels, and the first switch tube and the second switch tube are turned on; the third to sixth clock signals are at low levels, and the third to seventh switch tubes are turned off;

[0025] One end of the compensation capacitor is connected to an external initial voltage and charged, and the other end is grounded to obtain the initial state of the compensation capacitor; the top gate of the depletion-type dual-gate drive tube is connected to the external initial voltage, and the source and one end of the storage capacitor are grounded and discharged to obtain the initial state of the depletion-type dual-gate drive tube and the storage capacitor.

[0026] Based on the further improvement of the above method, the voltage compensation stage includes:

[0027] The second clock signal and the third clock signal are at high level, and the second to fourth switch tubes are turned on; the first, third to sixth clock signals are at low level, and the first, fifth to seventh switch tubes are turned off;

[0028] The bottom gate and source of the depletion-type dual-gate driver tube are short-circuited and grounded; the top gate and drain are short-circuited, so that the voltage of the top gate is discharged through the drain-source path of the depletion-type dual-gate driver tube, and the top gate voltage drops, causing the threshold voltage of the driver tube to move positively, thereby realizing compensation for the threshold voltage; since the bottom gate voltage of the driver tube and the source voltage of the driver tube are fixed at 0V, the voltage between the bottom gate and the source is greater than the threshold voltage and the top gate voltage difference of β times, so that the dual-gate driver tube gradually reaches a critical state of being about to be turned off; wherein, the β can be directly extracted in the experiment and is a fixed structural parameter greater than 0 and less than 1.

[0029] Based on the further improvement of the above method, the data input stage includes:

[0030] The fourth and data signals are at a high level, and the fifth switch tube is turned on; the first to third and sixth clock signals are at a low level, and the first to fourth, sixth and seventh switch tubes are turned off;

[0031] The data signal is input into the bottom grid of the depletion type dual-gate driving tube and one end of the storage capacitor to charge the bottom grid of the depletion type dual-gate driving tube and the storage capacitor.

[0032] Based on the further improvement of the above method, the light emitting stage includes:

[0033] Only the sixth clock signal is at a high level, the sixth switch tube and the seventh switch tube are turned on; the first to the data signal are at a low level, and the first to the fifth switch tubes are turned off;

[0034] The depletion-type dual-gate drive tube is turned on, and the power supply voltage is connected to the light-emitting diode through the sixth switch tube, the depletion-type dual-gate drive tube, and the seventh switch tube in sequence. The drive current of the light-emitting diode is obtained using the following formula:

[0035] I=k*(V BGS -V th0 +βV TG ) 2 (1)

[0036] Where, I represents the driving current of the light-emitting diode, μ represents the electron mobility of the depletion-type dual-gate driver, C ox represents the gate dielectric capacitance of the bottom gate, W represents the channel width of the depletion-type dual-gate driver tube, L represents the channel length of the depletion-type dual-gate driver tube, V BGS Represents the voltage between the bottom gate and source of the depletion-type dual-gate driver, V th0 It represents the threshold of the depletion-type dual-gate driver before threshold compensation, that is, the threshold of the bottom gate; V TG represents the top gate voltage, β represents a fixed structural parameter greater than 0 and less than 1;

[0037] V th =V th0 -βV TG (2)

[0038] Among them, V th It indicates the threshold value of the depletion-type dual-gate driver tube after threshold compensation;

[0039] Substituting formula (2) into formula (1) yields:

[0040] I=k*(V BGS -V th ) 2

[0041] The light emitting diode is driven based on the driving current to emit light with corresponding brightness.

[0042] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0043] 1. The circuit of the present invention can achieve the purpose of stable pixel compensation. Its power supply voltage, initial voltage and data signal are simple, so the peripheral control circuit is simple; among them, the data signal is a single pulse signal, and a lower duty cycle can be set to achieve the function of circuit stability;

[0044] 2. Compared with the single-gate device, the dual-gate device used in the present invention has a higher carrier mobility, a higher driving current, a stronger gate control capability and a smaller subthreshold slope, and can effectively suppress the short channel effect, which is more advantageous in terms of device size miniaturization;

[0045] 3. The initialization operation of the present invention ensures that the compensation capacitor, storage capacitor and depletion-type dual-gate drive tube are in their respective initial states before refreshing and will not be affected by the residual charge of the previous frame, so that the brightness of the light-emitting diode will not be affected by the brightness of the previous frame, which is beneficial to improving the display contrast.

[0046] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components;

[0048] Figure 1 An 8T2C depletion-type dual-gate drive tube threshold voltage compensation circuit shown in one embodiment of the present invention;

[0049] Figure 2 A schematic diagram of a clock signal according to an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of the initialization phase of an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of a compensation phase according to an embodiment of the present invention;

[0052] Figure 5 A schematic diagram of a data input stage according to an embodiment of the present invention;

[0053] Figure 6 A schematic diagram of the light-emitting phases according to an embodiment of the present invention;

[0054] Figure 7 A circuit simulation waveform diagram shown in one embodiment of the present invention;

[0055] Reference numerals:

[0056] 1-initialization stage; 2-compensation stage; 3-data input stage; 4-light-emitting stage. DETAILED DESCRIPTION

[0057] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0058] A dual-gate drive transistor with gates at both the bottom and top has good device performance and good threshold stability under voltage stress, and the threshold voltage of the bottom gate can be controlled by the top gate during normal operation. Based on this phenomenon, a new concept of using the top gate to compensate for threshold voltage changes is proposed. When applied in the field of displays, the bottom gate of the dual-gate drive transistor serves as the main gate, and the threshold voltage can be controlled by the top gate. When the threshold voltage of the Id-Vbg curve shifts positively, the increasing Vtg will cause the threshold voltage to shift negatively, and vice versa. In other words, by appropriately setting the top gate bias voltage, the driver transistor circuit using the bottom gate can get rid of the problem of threshold voltage offset, that is, using the top gate to compensate for the threshold voltage difference of the peripheral circuit in the driver and pixel circuit of the active organic light-emitting diode.

[0059] A specific embodiment of the present invention discloses an 8T2C depletion-type dual-gate driver threshold voltage compensation circuit, such as Figure 1 As shown. It includes: a light emitting diode OLED, a switch tube unit, a depletion-type dual-gate driving tube TFT1, a compensation capacitor C2, and a storage capacitor C1; wherein the switch tube unit includes the first to seventh switch tubes;

[0060] The drain of the first switch tube TFT2 is connected to the external initial voltage V initial, the source is connected to the top gate of the depletion-type dual-gate driving tube; the drain of the second switch tube TFT3 is connected to the source of the depletion-type dual-gate driving tube TFT1, and the source is connected to one end of the compensation capacitor C2 and the ground; the other end of the compensation capacitor C2 is connected to the top gate of the depletion-type dual-gate driving tube TFT1; the source of the third switch tube TFT4 is connected to the drain of the depletion-type dual-gate driving tube TFT1, and the drain is connected to the top gate of the depletion-type dual-gate driving tube TFT1; the source of the fourth switch tube TFT5 is connected to the source of the depletion-type dual-gate driving tube TFT1 and one end of the storage capacitor C1, and the drain is connected to the bottom gate of the depletion-type dual-gate driving tube TFT1 and the other end of the storage capacitor C1; the source of the fifth switch tube TFT6 is connected to the bottom gate of the depletion-type dual-gate driving tube TFT1, and the drain is connected to the data signal; the source of the sixth switch tube TFT7 is connected to the drain of the depletion-type dual-gate driving tube TFT1, and the drain is connected to the power supply voltage VDD; the drain of the seventh switch tube TFT8 is connected to the source of the depletion-type dual-gate driving tube TFT1, and the source is connected to the anode of the light-emitting diode OLED; the cathode of the light-emitting diode OLED is grounded.

[0061] It is worth noting that Figure 1 Point A in the middle represents the bottom gate, which is the main gate (PG), and point B represents the top gate, which is the auxiliary gate (AG).

[0062] In addition, it also includes the first to sixth clock signals input from the outside; wherein,

[0063] The first clock signal S0 controls the on and off of the first switch tube TFT2;

[0064] The second clock signal S1 controls the on and off of the second switch tube TFT3;

[0065] The third clock signal S2 controls the on and off of the third switch tube TFT4 and the fourth switch tube TFT5;

[0066] The fourth clock signal S3 controls the on and off of the fifth switch tube TFT6;

[0067] The data signal DATA is input to the drain of the fifth switch tube TFT6;

[0068] The sixth clock signal Em controls the on and off of the sixth switch tube TFT7 and the seventh switch tube TFT8.

[0069] like Figure 2 As shown, the marks 1-4 are the initialization stage, the compensation stage, the data input stage and the light-emitting stage respectively; in a single cycle, in order to prevent the risk and conflict of the clock signal and ensure that each working stage has sufficient completion time, the pulses of each clock signal are set according to the debugging experience in the experimental process:

[0070] In the initialization stage, the first clock signal and the second clock signal are at a high level; in the compensation stage, the second clock signal and the third clock signal are at a high level; in the data input stage, the fourth clock signal and the data signal are at a high level; in the light-emitting stage, the sixth clock signal is at a high level;

[0071] When the period is 500μs, within the period of 0-500μs:

[0072] The first clock signal S0: 100μs to the rising edge, pulse width 100μs;

[0073] The second clock signal S1: 90μs to the rising edge, pulse width 250μs;

[0074] The third clock signal S2: 200μs to the rising edge, pulse width 130μs;

[0075] The fourth clock signal S3: reaches the rising edge at 300μs, and the pulse width is 80μs;

[0076] Data signal DATA: 300μs to the rising edge, pulse width 90μs;

[0077] The sixth clock signal Em: reaches the rising edge at 410 μs, and the pulse width is 90 μs.

[0078] It should be noted that, in order to simplify the peripheral circuit, the power supply voltage and the external initial voltage in this embodiment are both DC voltages. For example, the power supply voltage VDD is 15V, and the external initial voltage V initial The peripheral voltage is set to be 10V; a larger value can reserve enough discharge capacity in the discharge stage to meet the positive drift of the threshold voltage to match the preset voltage of the bottom gate to achieve the critical shutdown state of the driver tube.

[0079] Preferably, the low voltage of the first to fourth and sixth clock signals is -5V, and the high voltage is 15V; the low voltage of the data signal DATA is 0V, and the high voltage is 15V; the clock signal is set to a single high level, which avoids increasing the signal complexity in a single cycle, and also reduces the difficulty of designing the peripheral clock signal control circuit. In addition, a single pulse signal can be set with a lower duty cycle, which is not prone to circuit failure in practical applications, and has low power consumption. Combined with the invariance of the power supply voltage in a single cycle, this embodiment has great potential in the application of high-frequency display circuits. In addition, a switching transistor is added to the anode of the light-emitting diode OLED to ensure that the light-emitting diode OLED will not be subjected to unnecessary light emission caused by capacitor charge leakage in the non-light-emitting stage, thereby enhancing the stability of the display.

[0080] In an optional manner of this embodiment, the first to seventh switch tubes are all N-type depletion-type transistors.

[0081] Another specific embodiment of the present invention discloses a 8T2C depletion-mode dual-gate driver threshold voltage compensation method, the steps comprising:

[0082] S1: Initialization phase, for initializing the voltage V initial Setting the initial states of the depletion-type dual-gate driving tube TFT1 and the compensation capacitor C2; and discharging the storage capacitor C1;

[0083] S2: Compensation stage, short-circuiting the bottom gate and source, as well as the top gate and drain of the depletion-type dual-gate driving tube TFT1 to achieve compensation for the threshold voltage;

[0084] S3: data input stage, used to charge the bottom gate of the depletion-type dual-gate driving tube TFT1 and the storage capacitor C1 based on the data signal DATA;

[0085] S4: a light emitting stage, which is used to turn on the depletion-type dual-gate driving tube TFT1 to obtain a driving current of the light emitting diode OLED, and drive the light emitting diode OLED to emit light.

[0086] Specifically, if Figure 3 As shown, the initialization phase, such as Figure 2 The stage indicated by 1 in the figure includes:

[0087] The first clock signal S0 and the second clock signal S1 are at high level, and the first switch tube TFT2 and the second switch tube TFT3 are turned on; the third to sixth clock signals are at low level, and the third to seventh switch tubes are turned off;

[0088] Connect one end of the compensation capacitor C2 to the external initial voltage V initial and charged, and the other end is grounded to obtain the initial state of the compensation capacitor C2; the top gate of the depletion-type dual-gate drive tube TFT1 is connected to the external initial voltage V initial , pre-charge voltage to external initial voltage V initial , used for later discharge; the source of the depletion-type dual-gate driving tube TFT1 and one end of the storage capacitor C1 are grounded for discharge, obtaining the initial state of the depletion-type dual-gate driving tube TFT1 and the storage capacitor C1.

[0089] The precharge process of the top gate of the depletion-type dual-gate driving tube TFT1 is very fast. In order to discharge the source end of the depletion-type dual-gate driving tube TFT1 to the initialization state as much as possible in the initialization stage, the second clock signal S1 will reach the rising edge earlier than the first clock signal S0.

[0090] Specifically, if Figure 4 As shown, the compensation stage, as Figure 2 The stage indicated in 2 includes:

[0091] The second clock signal S1 and the third clock signal S2 are at high levels, and the second to fourth switch tubes are turned on; the first, third to sixth clock signals are at low levels, and the first, fifth to seventh switch tubes are turned off;

[0092] The bottom gate and source of the depletion-type dual-gate drive tube TFT1 are short-circuited and grounded; the top gate and drain are short-circuited, so that the voltage of the top gate is discharged through the drain-source path of the depletion-type dual-gate drive tube TFT1, and the top gate voltage drops, causing the positive movement of the drive tube threshold voltage, thereby achieving compensation for the threshold voltage; since the bottom gate voltage and the source voltage of the drive tube TFT1 are fixed at 0V, the voltage between the bottom gate and the source is greater than the threshold voltage and β times the top gate voltage difference, so that the depletion-type dual-gate drive tube TFT1 gradually reaches a critical state of being about to be turned off; wherein, the β can be directly extracted in the experiment and is a fixed structural parameter greater than 0 and less than 1. The problem of negative drift of the threshold voltage during operation leading to unstable driving current is solved.

[0093] It is worth noting that the fourth clock signal S3 and the data signal DATA reach the rising edge in advance at this stage, so the data signal DATA can be input to the bottom gate of the depletion-type dual-gate driving transistor TFT1 in advance to ensure the complete input of the data signal DATA.

[0094] Specifically, if Figure 5 As shown, the data input stage is as follows Figure 2 The stage indicated by 3 in the above; including:

[0095] The fourth and data signals are at a high level, and the fifth switch tube TFT6 is turned on; the first to third and sixth clock signals are at a low level, and the first to fourth, sixth and seventh switch tubes are turned off;

[0096] The data signal DATA is input into the bottom gate of the depletion-type dual-gate driving tube TFT1 and one end of the storage capacitor C1 to charge the bottom gate of the depletion-type dual-gate driving tube TFT1 and the storage capacitor.

[0097] In this stage, the fourth clock signal S3 reaches the falling edge earlier than the data signal DATA, which can ensure that the fifth switch TFT6 always inputs the complete data signal DATA before being turned off. Figure 6 As shown, the light emitting stage, as Figure 2 The stage indicated by 4 in the above table includes:

[0098] Only the sixth clock signal Em is at a high level, the sixth switch tube and the seventh switch tube are turned on; the first to the data signals are at a low level, and the first to the fifth switch tubes are turned off;

[0099] The depletion-type dual-gate drive tube TFT1 is turned on, and the power supply voltage VDD is connected to the light-emitting diode OLED through the sixth switch tube TFT7, the depletion-type dual-gate drive tube TFT1, and the seventh switch tube TFT8 in sequence. The drive current of the light-emitting diode OLED is obtained by the following formula:

[0100] I=k*(V BGS -V th0 +βV TG ) 2 (1)

[0101] Where, I represents the driving current of the light emitting diode OLED, μ represents the electron mobility of the depletion-type dual-gate driver TFT1, C ox represents the gate dielectric capacitance of the bottom gate, W represents the channel width of the depletion-type dual-gate drive tube TFT1, L represents the channel length of the depletion-type dual-gate drive tube TFT1, V BGS Represents the voltage between the bottom gate and source of the depletion-type dual-gate driver TFT1, V th0 It represents the threshold value of depletion-type dual-gate drive tube TFT1 before threshold compensation, V TG represents the top gate voltage, β represents a fixed structural parameter greater than 0 and less than 1;

[0102] V th =V th0 -βV TG (2)

[0103] Among them, V th It represents the threshold value of the depletion-type dual-gate driving tube TFT1 after threshold compensation;

[0104] Substituting formula (2) into formula (1) yields:

[0105] I=k*(V BGS -V th ) 2

[0106] Since the V in the driving current formula of the light-emitting diode OLED th is the threshold value after threshold compensation, which is a fixed critical value; therefore, the change of the threshold voltage of the depletion-type dual-gate driving tube TFT1 no longer affects the magnitude of the driving current of the light-emitting diode OLED, and the brightness of the light-emitting diode OLED is stabilized.

[0107] In particular, in this phase, the sixth clock signal Em is delayed to reach the rising edge, so that the data signal DATA has a holding time, thereby ensuring the integrity of the data signal DATA.

[0108] The light emitting diode OLED is driven based on the driving current to emit light with corresponding brightness.

[0109] The circuit and method of the present invention are simulated, and five threshold voltage drift values ​​are set during the simulation. The circuit simulation waveform obtained is as follows: Figure 7 As shown, I24 / d represents the driving current of the light emitting diode OLED; it can be seen that through the compensation effect of this scheme, under different threshold voltage drift values, the voltage of the top gate of the depletion-type dual-gate driving tube TFT1 is also different, thereby realizing compensation for the bottom gate threshold and keeping the driving current stable.

[0110] Compared with the prior art, the circuit provided in this embodiment can achieve the purpose of stable pixel compensation. Its power supply voltage, initial voltage, and data signal are simple, so the peripheral control circuit is simple; wherein, the data signal is a single pulse signal, and a lower duty cycle can be set to achieve the function of circuit stability; compared with the single-gate device, the dual-gate device used in this embodiment has a larger carrier mobility, a larger driving current, a stronger gate control capability, and a smaller subthreshold slope, and can effectively suppress the short channel effect, and has more advantages in device size miniaturization; the initialization operation of this embodiment ensures that the compensation capacitor, the storage capacitor, and the depletion-type dual-gate drive tube are in their respective initial states before refreshing, and will not be affected by the residual charge of the previous frame, so that the brightness of the light-emitting diode will not be affected by the brightness of the previous frame, which is conducive to improving the display contrast.

[0111] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0112] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. An 8T2C depletion-type dual-gate driver threshold voltage compensation circuit, characterized in that: include: A light emitting diode, a switch tube unit, a depletion-type dual-gate driving tube, a compensation capacitor, and a storage capacitor; wherein the switch tube unit includes first to seventh switch tubes; The drain of the first switch tube is connected to the external initial voltage, and the source is connected to the top gate of the depletion-type dual-gate drive tube; the drain of the second switch tube is connected to the source of the depletion-type dual-gate drive tube, and the source is connected to one end of the compensation capacitor and the ground; the other end of the compensation capacitor is connected to the top gate of the depletion-type dual-gate drive tube; the source of the third switch tube is connected to the drain of the depletion-type dual-gate drive tube, and the drain is connected to the top gate of the depletion-type dual-gate drive tube; the source of the fourth switch tube is connected to the source of the depletion-type dual-gate drive tube and one end of the storage capacitor, and the drain is connected to the bottom gate of the depletion-type dual-gate drive tube and the other end of the storage capacitor; the source of the fifth switch tube is connected to the bottom gate of the depletion-type dual-gate drive tube, and the drain is connected to the data signal; the source of the sixth switch tube is connected to the drain of the depletion-type dual-gate drive tube, and the drain is connected to the power supply voltage; the drain of the seventh switch tube is connected to the source of the depletion-type dual-gate drive tube, and the source is connected to the anode of the light-emitting diode; the cathode of the light-emitting diode is grounded.

2. The 8T2C depletion-type dual-gate drive tube threshold voltage compensation circuit according to claim 1, characterized in that: It also includes the first to sixth clock signals input from the outside; wherein, The first clock signal controls the on and off of the first switch tube; The second clock signal controls the on and off of the second switch tube; The third clock signal controls the on and off of the third switch tube and the fourth switch tube; The fourth clock signal controls the on and off of the fifth switch tube; The data signal is input into the drain of the fifth switch tube; The sixth clock signal controls the on and off of the sixth switch tube and the seventh switch tube.

3. The 8T2C depletion-type dual-gate driver threshold voltage compensation circuit according to claim 2, characterized in that: The low voltage of the first to fourth and sixth clock signals is -5V, and the high voltage is 15V; the low voltage of the data signal is 0V, and the high voltage is 15V.

4. The 8T2C depletion-type dual-gate driver threshold voltage compensation circuit according to claim 1, characterized in that: The power supply voltage and the external initial voltage are both DC voltages.

5. The 8T2C depletion-mode dual-gate driver threshold voltage compensation method according to claim 1, characterized in that: The first to seventh switch tubes are all N-type depletion-type transistors.

6. A depletion-type dual-gate driver threshold voltage compensation method implemented by the circuit described in any one of claims 1 to 5, characterized in that: Including in order: Initialization phase, compensation phase, data input phase, light-emitting phase; among them, The initialization stage is used to set the initial state of the depletion-type dual-gate drive tube and the compensation capacitor based on the external initial voltage; and discharge the storage capacitor; The compensation stage is used to short-circuit the bottom gate and source, as well as the top gate and drain of the depletion-type dual-gate driver tube to achieve compensation for the threshold voltage; The data input stage is used to charge the bottom gate and storage capacitor of the depletion-type dual-gate drive tube based on the data signal; The light-emitting stage is used to turn on the depletion-type dual-gate drive tube to obtain the driving current of the light-emitting diode and drive the light-emitting diode to emit light.

7. The 8T2C depletion-mode dual-gate driver threshold voltage compensation method according to claim 6, characterized in that: The initialization phase includes: The first clock signal and the second clock signal are at high levels, and the first switch tube and the second switch tube are turned on; the third to sixth clock signals are at low levels, and the third to seventh switch tubes are turned off; One end of the compensation capacitor is connected to an external initial voltage and charged, and the other end is grounded to obtain the initial state of the compensation capacitor; the top gate of the depletion-type dual-gate drive tube is connected to the external initial voltage, and the source and one end of the storage capacitor are grounded and discharged to obtain the initial state of the depletion-type dual-gate drive tube and the storage capacitor.

8. The 8T2C depletion-mode dual-gate driver threshold voltage compensation method according to claim 6, characterized in that: The voltage compensation stage includes: The second clock signal and the third clock signal are at high level, and the second to fourth switch tubes are turned on; the first, third to sixth clock signals are at low level, and the first, fifth to seventh switch tubes are turned off; The bottom gate and source of the depletion-type dual-gate driver tube are short-circuited and grounded; the top gate and drain are short-circuited, so that the voltage of the top gate is discharged through the drain-source path of the depletion-type dual-gate driver tube, and the top gate voltage drops, causing the threshold voltage of the driver tube to move positively, thereby realizing compensation for the threshold voltage; since the bottom gate voltage of the driver tube and the source voltage of the driver tube are fixed at 0V, the voltage between the bottom gate and the source is greater than the threshold voltage and β times the top gate voltage difference, so that the depletion-type dual-gate driver tube gradually reaches a critical state of being about to be turned off; wherein, the β can be directly extracted in the experiment and is a fixed structural parameter greater than 0 and less than 1.

9. The 8T2C depletion-mode dual-gate driver threshold voltage compensation method according to claim 6, characterized in that: The data input stage includes: The fourth and data signals are at a high level, and the fifth switch tube is turned on; the first to third and sixth clock signals are at a low level, and the first to fourth, sixth and seventh switch tubes are turned off; The data signal is input into the bottom grid of the depletion type dual-gate driving tube and one end of the storage capacitor to charge the bottom grid of the depletion type dual-gate driving tube and the storage capacitor.

10. The 8T2C depletion-mode dual-gate driver threshold voltage compensation method according to claim 6, characterized in that: The lighting stage includes: Only the sixth clock signal is at a high level, the sixth switch tube and the seventh switch tube are turned on; the first to the data signal are at a low level, and the first to the fifth switch tubes are turned off; The depletion-type dual-gate drive tube is turned on, and the power supply voltage is connected to the light-emitting diode through the sixth switch tube, the depletion-type dual-gate drive tube, and the seventh switch tube in sequence. The drive current of the light-emitting diode is obtained using the following formula: I=k*(V BGS -V th0 +βV TG ) 2 (1) Where, I represents the driving current of the light-emitting diode, μ represents the electron mobility of the depletion-type dual-gate driver, C ox represents the gate dielectric capacitance of the bottom gate, W represents the channel width of the depletion-type dual-gate driver tube, L represents the channel length of the depletion-type dual-gate driver tube, V BGS Represents the voltage between the bottom gate and source of the depletion-type dual-gate driver, V th0 Represents the threshold of the depletion-type dual-gate driver before threshold compensation, V TG represents the top gate voltage, β represents a fixed structural parameter greater than 0 and less than 1; In th =V th0 -βV TG (2) Among them, V th It indicates the threshold value of the depletion-type dual-gate driver tube after threshold compensation; Substituting formula (2) into formula (1) yields: I=k*(V BGS -V th ) 2 The light emitting diode is driven based on the driving current to emit light with corresponding brightness.

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