Pixel circuit, display panel and display device

Abstract

The application discloses a pixel circuit, a display panel and a display device. The pixel circuit comprises a driving transistor and at least one switching transistor. The driving transistor comprises a first active layer, a first gate arranged on the first side of the first active layer, and a second gate arranged on the second side of the first active layer away from the first side. The at least one switching transistor comprises a second active layer, a third gate arranged on the first side of the second active layer, and a fourth gate arranged on the second side of the second active layer away from the first side. The first active layer and the second active layer are arranged in the same layer. The first gate serves as the control end of the driving transistor. The fourth gate serves as the control end of the switching transistor. The second gate is used for receiving a first constant potential. The third gate is used for receiving a second constant potential. The technical scheme provided by the application can simplify the process of the display panel and improve the performance of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are light-emitting materials that emit light through carrier injection and recombination under the influence of an electric field. Compared to liquid crystal displays (LCDs), OLEDs are thinner and lighter, and offer better viewing angles and contrast, thus attracting widespread attention.

[0003] Low-Temperature Polycrystalline Oxide (LTPO) display panels are a combination of Low-Temperature Poly-Silicon (LTPS) and Indium Gallium Zinc Oxide (IGZO) technologies in organic light-emitting diode (OLED) displays. However, this combination makes the display panel manufacturing process more complex, imposes requirements on the compatibility of the display panel, and increases the production cost. Summary of the Invention

[0004] This invention provides a pixel circuit, a display panel, and a display device to improve display panel performance while simplifying the display panel manufacturing process.

[0005] In a first aspect, embodiments of the present invention provide a pixel circuit, including: a driving transistor and at least one switching transistor;

[0006] The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side.

[0007] At least one of the switching transistors includes a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side;

[0008] The first active layer and the second active layer are disposed on the same layer; the first gate serves as the control terminal of the driving transistor; the fourth gate serves as the control terminal of the switching transistor; the second gate is used to receive a first constant potential; and the third gate is used to receive a second constant potential.

[0009] Secondly, embodiments of the present invention provide a pixel circuit, including: a driving transistor and at least one switching transistor;

[0010] The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side.

[0011] At least one of the switching transistors includes a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side;

[0012] The first active layer and the second active layer are disposed on the same layer; the first gate serves as the control terminal of the driving transistor; the second gate is used to receive a third constant potential; and the third gate and the fourth gate serve as the control terminals of the switching transistor.

[0013] Thirdly, embodiments of the present invention provide a pixel circuit, including: a driving transistor and at least one switching transistor;

[0014] The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side.

[0015] At least one of the switching transistors includes a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side;

[0016] The first active layer and the second active layer are disposed on the same layer; the first gate and the second gate serve as the control terminals of the driving transistor; the fourth gate serves as the control terminal of the switching transistor; and the third gate is used to receive a fourth constant potential.

[0017] Fourthly, embodiments of the present invention also provide a display panel, including the pixel circuit provided in any embodiment of the present invention.

[0018] Fifthly, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention.

[0019] In this invention, the pixel circuit includes a driving transistor and at least one switching transistor. The driving transistor includes a first active layer and a first gate and a second gate on opposite sides of the first active layer. The switching transistor includes a second active layer and a third gate and a fourth gate on opposite sides of the second active layer. The first and second active layers are disposed on the same layer, and the first and third gates are disposed on the same side, as are the second and fourth gates. In this embodiment, at least one of the first and second gates can be used as the control terminal of the driving transistor, and at least one of the third and fourth gates can be used as the control terminal of the switching transistor. The control methods of the driving transistor control terminal and the switching transistor control terminal are different to achieve different electrical performances, so that the switching transistor has high mobility and the driving transistor has strong stability. In this embodiment, only one all-oxide active layer is set to balance the stability of the driving transistor and the high mobility of the switching transistor. Therefore, this embodiment does not need to set multiple active layers to simultaneously integrate LTPS and IGZO technologies to meet different electrical performances, simplifying the display panel process, significantly reducing process costs, and improving circuit layout space. In addition, compared to the LTPO process, this embodiment is less susceptible to moisture and other factors, reducing the difficulty of the process and making it easier to meet the mass production requirements of display panels. Attached Figure Description

[0020] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the structure of an LTPO display panel provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0024] Figure 5 A circuit diagram of a pixel circuit provided for an embodiment of the invention;

[0025] Figure 6 for Figure 5 Layout diagram of the mid-pixel circuit;

[0026] Figure 7 for Figure 5 A schematic diagram of the cross-sectional structure of the middle pixel circuit along line segment a-a';

[0027] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0028] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0029] Figure 10 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0030] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0032] This invention provides a pixel circuit, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. It includes: a driving transistor T1 and at least one switching transistor T2;

[0033] The driving transistor T1 includes a first active layer 11, a first gate 12 disposed on a first side of the first active layer 11, and a second gate 13 disposed on the first active layer 11 away from the first side;

[0034] At least one switching transistor T2 includes a second active layer 14, a third gate 15 disposed on a first side of the second active layer 14, and a fourth gate 16 disposed on the second active layer 14 away from the first side.

[0035] The first active layer 11 and the second active layer 14 are disposed on the same layer; the first gate 12 serves as the control terminal of the driving transistor T1; the fourth gate 16 serves as the control terminal of the switching transistor T2; the second gate 13 is used to receive the first constant potential V1; and the third gate 15 is used to receive the second constant potential V2.

[0036] In this embodiment of the invention, the pixel circuit includes a driving transistor and at least one switching transistor. The driving transistor includes a first active layer and a first gate and a second gate on opposite sides of the first active layer. The switching transistor includes a second active layer and a third gate and a fourth gate on opposite sides of the second active layer. The first and second active layers are disposed on the same layer, and the first and third gates are disposed on the same side, as are the second and fourth gates. In this embodiment, at least one of the first and second gates can be used as the control terminal of the driving transistor, and at least one of the third and fourth gates can be used as the control terminal of the switching transistor. The control methods of the driving transistor control terminal and the switching transistor control terminal are different to achieve different electrical performances, so that the switching transistor has high mobility and the driving transistor has strong stability. In this embodiment, only one all-oxide active layer is set to balance the stability of the driving transistor and the high mobility of the switching transistor. Therefore, this embodiment does not need to set multiple active layers to simultaneously integrate LTPS and IGZO technologies to meet different electrical performances, simplifying the display panel process, significantly reducing process costs, and improving circuit layout space. In addition, compared to the LTPO process, this embodiment is less susceptible to moisture and other factors, reducing the difficulty of the process and making it easier to meet the mass production requirements of display panels.

[0037] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0038] The pixel circuit includes a driving transistor T1 and at least one switching transistor T2. The driving transistor T1 generates a driving current to drive the corresponding light-emitting element 111, while the switching transistor T2 controls the voltages at the gate and source / drain of the driving transistor T1, thereby controlling the magnitude of the driving current output by the driving transistor T1. Figure 1As shown, the display panel includes a substrate 31 and pixel circuits and light-emitting elements 111 sequentially disposed on the substrate 31. The driving transistor T1 includes a first active layer 11, a first gate 12 on a first side of the first active layer 11, and a second gate 13 away from the first side of the first active layer 11. That is, the driving transistor T1 includes two gates respectively disposed on opposite sides of the first active layer 11. Similarly, the switching transistor T2 includes a second active layer 14, a third gate 15 on a first side of the second active layer 14, and a third gate 15 away from the first side of the second active layer 14. The switching transistor T2 includes two gates respectively disposed on opposite sides of the second active layer 14. In this embodiment, the first side of the first active layer 11 can be the side closer to the substrate 31 or the side away from the substrate 31. This embodiment does not specifically limit this; it is merely an example. Figure 1 The side of the first active layer 11 and the second active layer 14 closest to the substrate 31 is designated as the first side. For example... Figure 1 As shown, the first active layer 11 and the second active layer 14 are disposed in the same active layer and manufactured using the same process. Therefore, the first gate 12 and the third gate 15 are disposed on the same side of the active layer, and the second gate 13 and the fourth gate 16 are disposed on the same side of the active layer. Optionally, in this embodiment, the active layer can be an all-oxide layer, and the all-oxide layer can achieve electrical adjustment or device optimization during the adjustment of the two gate potentials of the transistor, achieving compatibility of transistors with different performance in the same display panel. Specifically, the potential control method of the two gates of the driving transistor T1 is different from the potential control method of the two gates of the switching transistor T2. Furthermore, the display panel may also include a source-drain layer 17, which can connect adjacent transistors to realize the transmission of current signals.

[0039] Optionally, the first gate 12 serves as the control terminal of the driving transistor T1, and the second gate 13 is connected to the first constant potential V1; the fourth gate 16 serves as the control terminal of the switching transistor T2, and the third gate 15 is connected to the second constant potential V2. For the driving transistor T1, with the first gate 12 as the control terminal, the first constant potential V1 of the second gate 13 affects the first active layer 11, which can significantly change the subthreshold swing of the first active layer 11. In this embodiment, the subthreshold swing of the first active layer 11 is increased by the first constant potential V1. The subthreshold swing represents the amount of change in the voltage value of the control terminal required for a tenfold change in the source-drain current (driving current) of the driving transistor T1. When the subthreshold swing is larger, if the voltage value of the control terminal fluctuates slightly, the driving current generated by the driving transistor T1 will not be significantly disturbed, and the stability is stronger. Especially in low grayscale display screens, the driving force of the driving transistor T1 is strong, the screen is stable, and the display effect is good. For the switching transistor T2, the second constant potential V2 of the third gate 15 can control the speed at which the carriers of the second active layer 14 form the inversion layer, increase the movement speed of the carriers in the electric field, so that the switching transistor T2 has high mobility, improves conductivity, and achieves a smaller subthreshold swing.

[0040] This embodiment uses only one active layer and employs dual gates for each transistor, using different control methods for the gates of driving transistor T1 and switching transistor T2, thereby adjusting the electrical performance of the devices with different transistors. This embodiment uses fewer film layers and a simpler film layer process to simultaneously ensure the different device performance of driving transistor T1 and switching transistor T2. Figure 2 This is a schematic diagram of the structure of an LTPO display panel provided in an embodiment of the present invention. In the prior art, to simultaneously accommodate the different device performances of driving transistors and switching transistors, LTPO fabrication processes are employed, such as... Figure 2As shown, a transistor T1' fabricated using LTPO technology, a transistor T2' fabricated using IGZO technology, and a light-emitting element 111' are disposed on the substrate 11'. The active layer 12' of transistor T1' is made of low-temperature polycrystalline silicon, which requires a large aspect ratio to increase the subthreshold swing. The active layer 13' of transistor T2' is made of indium gallium zinc oxide, which has a high carrier mobility. LTPO display panels require two active layers made of different materials, making the process complex and demanding high compatibility with hybrid devices, leading to increased costs. Furthermore, each pixel circuit occupies a large layout space, further complicating the development of the display panel. In addition, because LTPO needs to balance the performance of both IGZO and LTPS devices, the electrical properties of IGZO devices are easily affected by moisture, requiring high performance at the process edges. LTPS, to ensure low grayscale visual effects and image uniformity, requires a larger aspect ratio of the driving transistors, further increasing the layout space of the pixel circuits and affecting the PPI of the display panel. This embodiment employs a simple film layer structure with minimal structural changes, while simultaneously being compatible with the different device performance of the driving transistor T1 and the switching transistor T2. Compared to the LTPO process, this embodiment features a simplified process flow, eliminating the need for a large aspect ratio in the driving transistor T1, reducing layout space, and simplifying device development. Furthermore, the switching transistor T2 exhibits low sensitivity and strong stability. This embodiment also allows for autonomous adjustment of device electrical properties via a first constant potential V1 and a second constant potential V2 to meet various display requirements.

[0041] Optionally, the materials of the first active layer 11 and the second active layer 14 can both be oxides of a designated metal; the designated metal includes at least one of the following: gallium, hafnium, tin, lanthanum, indium, praseodymium, and zinc. With the gradual maturation of LTPO technology, this embodiment uses an all-oxide process to reduce costs. The all-oxide is an oxide of a designated metal, which can include rare metals such as tin and hafnium, rare earth metals such as lanthanum and praseodymium, rare dispersed metals such as gallium and indium, or more widely distributed metal elements such as zinc, forming the all-oxide first active layer 11 and the second active layer 14. This eliminates the need for an active layer of low-temperature polycrystalline silicon material, effectively simplifying the pixel circuit process.

[0042] Figure 3This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Optionally, both the first active layer 11 and the second active layer 14 may include a first oxide layer 21 and a second oxide layer 22; the first oxide layer is disposed on the side of the second oxide layer 22 near the first gate 12 or the third gate 15; the carrier mobility of the first oxide layer 21 is less than the carrier mobility of the second oxide layer 22. In this embodiment, both the first active layer 11 and the second active layer 14 may include a double oxide layer: a first oxide layer 21 and a second oxide layer 22, and the first oxide layer 21 and the second oxide layer 22 may be configured to have different electrical properties. For example, because the first oxide layer 21 is disposed on the first side of the active layer, near the control terminal of the driving transistor T1, the first oxide layer 21 can be configured as a semiconductor layer with low mobility and high stability to meet the device performance of the driving transistor T1; because the second oxide layer 22 is disposed on the side of the active layer away from the first side, near the control terminal of the switching transistor T2, the second oxide layer 22 can be configured as a semiconductor layer with high mobility and low stability to meet the device performance of the switching transistor T2. Optionally, the second oxide layer 22 may contain a higher proportion of metals such as gallium, tin, lanthanum, and hafnium to achieve a lower carrier mobility. Furthermore, the double-layer all-oxide structure can further amplify the advantages of structural changes; for example, the thickness ratio of the first oxide layer 21 to the second oxide layer 22 can be adjusted to further refine the performance of each device.

[0043] Optionally, the thickness ratio of the first oxide layer 21 and the second oxide layer 22 can be in the range of 3:1 to 1:1. Adjusting the thickness ratio of the first oxide layer 21 and the second oxide layer 22 can adjust the mobility and stability of the entire active layer. In this embodiment, it is necessary to ensure the stability of the driving transistor T1 while reducing the aspect ratio of the driving transistor T1. In this embodiment, the closer first oxide layer 21 can be set to have a thicker film layer. Because in the LTPS process, it is necessary to increase the subthreshold swing by increasing the aspect ratio, which will increase the layout space of the pixel circuit and affect the PPI of the display panel. In this embodiment, it is only necessary to increase the thickness of the first oxide layer 21 to increase the subthreshold swing of the entire active layer. Moreover, the first oxide layer 21 is located on the side close to the control terminal of the driving transistor T1. The first oxide layer 21 serves as the main driving layer of the driving transistor T1, further increasing the stability of the driving transistor T1. The second oxide layer 22 is set close to the control terminal of the switching transistor T2. The second oxide layer 22 serves as the main driving layer of the switching transistor T2, increasing the stability of the driving transistor T1 while maintaining the high mobility characteristics of the switching transistor T2.

[0044] Optionally, the first oxide layer 21 may include indium oxide, gallium oxide, and zinc oxide; the second oxide layer 22 may include indium oxide, gallium oxide, zinc oxide, and tin oxide. In this embodiment, the first oxide layer 21 includes indium oxide, gallium oxide, and zinc oxide, and is formed by sintering three oxide powders to form a target material, which can be called IGZO; the second oxide layer 22 includes indium oxide, gallium oxide, zinc oxide, and tin oxide, and is formed by sintering four oxide powders to form a target material, which can be called IGZTO. Compared with the first oxide layer 21, the second oxide layer 22 adds tin oxide, thereby improving the carrier mobility of the second oxide layer 22. When the first oxide layer 21 is made of IGZO material and the second oxide layer 22 is made of IGZTO material, the thickness ratio of the first oxide layer 21 to the second oxide layer 22 can optionally be 2:1, so that the first oxide layer 21 meets the high subthreshold swing performance requirements of the driving transistor T1 and the second oxide layer 22 meets the high mobility performance requirements of the switching transistor T2. Only one active layer is set to be compatible with the electrical performance of different transistor devices. In addition, both the driving transistor T1 and the switching transistor T2 can maintain a small aspect ratio, reduce the area occupied by the pixel circuit, and improve the PPI of the display panel.

[0045] Of course, the first oxide layer 21 and the second oxide layer 22 can also be other materials. For example, the first oxide layer 21 can be a praseodymium (Pr) doped oxide (ITZO) system containing indium, tin, and zinc, i.e., ITZO:Pr. The above material has excellent light stability but low mobility. The second active layer 14 can also be an ITZO with a high indium content (In-rich ITZO). In-rich ITZO material has high mobility but poor light stability. Therefore, the above two materials form a coupling relationship between mobility and stability. ITZO:Pr forms an auxiliary photoelectron relaxation layer (CRL), and In-rich ITZO forms a carrier transport layer (CTL). When the active layer includes a first oxide layer 21 and a second oxide layer 22, the thickness ratio of the first oxide layer 21 and the second oxide layer 22 can be adjusted, as shown in Table 1. Table 1 is a parameter table for the thickness ratio of the first oxide layer and the second oxide layer. The total thickness of the first oxide layer 21 and the second oxide layer 22 can be set to 30 nm. The thickness ratio of the first oxide layer 21 and the second oxide layer 22 can be defined separately, and the mobility μ can be calculated. FE And the offset ΔVth of the threshold voltage under negative bias illumination stress NBIS. Specifically, as shown in Table 1, when the active layer structure of 30nm is all ITZO:Pr, the mobility μ FEThe efficiency is 16.2, and the threshold voltage offset ΔVth is -0.71. It exhibits low carrier mobility, small threshold voltage offset, and excellent stability. In a 30nm active layer structure, with a CTL thickness of 5nm and a CRL thickness of 25nm, its mobility μ... FE The threshold voltage offset ΔVth is 27.2, and the carrier mobility gradually increases, the threshold voltage offset gradually increases, and the stability decreases. Similarly, in a 30nm active layer structure, the CTL thickness is 10nm and the CRL thickness is 20nm, then its mobility μ FE The value is 36.4, and the threshold voltage offset ΔVth is -1.12. In a 30nm active layer structure, with a CTL thickness of 15nm and a CRL thickness of 15nm, the mobility μ is... FE The value is 43.3, and the threshold voltage offset ΔVth is -1.70. In a 30nm active layer structure, with a CTL thickness of 20nm and a CRL thickness of 10nm, the mobility μ is... FE The value is 50.1, and the threshold voltage offset ΔVth is -9.13; when the entire active layer structure of a 30nm active layer is In-rich ITZO (CRL), its mobility μ FE The value is 51.6, and the threshold voltage offset ΔVth is greater than -15. This indicates that the mobility is high when the CTL thickness increases. When the thickness ratio of CTL to CRL reaches 20 / 10, it is close to being entirely In-rich ITZO. However, at this point, the proportion of CRL is relatively small, which cannot meet the stability requirements of NBIS.

[0046] Table 1: Thickness ratio parameter of the first oxide layer and the second oxide layer

[0047]

[0048]

[0049] Based on Table 1 above, this embodiment further increases the thickness of the CRL, resulting in Table 2. Table 2 shows the adjusted thickness ratio parameters of the first oxide layer and the second oxide layer. Because the CTL achieves a high mobility at a thickness of 20 nm, the CTL thickness can be maintained at 20 nm while the CRL thickness is further increased. As shown in Table 1, with a CTL thickness of 20 nm and a CRL thickness of 10 nm, the mobility μ... FE The value is 50.1, and the threshold voltage offset ΔVth is -9.13. Referring to Table 2, with a CTL thickness of 20 nm and a CRL thickness of 20 nm, their mobility μ FE The value is 47.1, the threshold voltage offset ΔVth is -4.66; the CTL thickness is 20nm, the CRL thickness is 30nm, then its mobility μFE The threshold voltage offset ΔVth is 46.8, and the threshold voltage offset ΔVth is -1.56. As shown in Table 2, keeping the CTL thickness constant and increasing the CRL thickness ratio does not significantly change the mobility, but improves the stability of the NBIS. In this embodiment, if the first oxide layer 21 is a CRL and the second oxide layer 22 is a CTL, the thickness of the first oxide layer 21 can be set to 30 nm and the thickness of the second oxide layer 22 to 20 nm. This satisfies both the high subthreshold swing requirement of the driving transistor T1 and the high mobility requirement of the switching transistor T2.

[0050] Table 2: Adjusted Thickness Ratio Parameters of the First and Second Oxide Layers

[0051] CTL / CRL <![CDATA[μ FE (cm 2 / Vs)]]> NBIS△Vth(V) 20 / 10 50.1 -9.13 20 / 20 47.1 -4.66 20 / 30 46.8 -1.56

[0052] Continue to refer to Figure 1 Optionally, the display panel where the pixel circuit is located may at least include a substrate 31, a first metal layer 32, an active layer 33, and a second metal layer 34 stacked together; the first active layer 11 and the second active layer 14 are both disposed on the active layer 33; the first gate 12 and the third gate 15 are disposed on the first metal layer 32; and the fourth gate 16 and the second gate 13 are disposed on the second metal layer 34. In this embodiment, the pixel circuit includes a first metal layer 32, an active layer 33, and a second metal layer 34 disposed sequentially away from the substrate 31. The active layer 33 is provided with the first active layer 11 and the second active layer 14, the first metal layer 32 is provided with the first gate 12 and the third gate 15, and the second metal layer 34 is provided with the fourth gate 16 and the second gate 13. Of course, in other embodiments of the present invention, such as... Figure 4 As shown, Figure 4This is a schematic diagram of another pixel circuit structure provided by an embodiment of the present invention. The first gate 12 and the third gate 15 can also be disposed on the second metal layer 34, and the fourth gate 16 and the second gate 13 can be disposed on the first metal layer 32. In this embodiment, compatibility with transistors of different electrical characteristics can be achieved using only the three-layer structure of the first metal layer 32, the active layer 33, and the second metal layer 34. The process flow is simpler than the LTPO process, improving the mass production efficiency of the display panel. Furthermore, the active layer 33 can be a double-layer structure, further amplifying the advantages brought by the structural change and achieving performance adjustment. The thickness ratio of the double-layer structure can further adjust the device performance to meet the performance requirements of different types of transistors. For example, when the double-layer structure is a low-mobility first oxide layer 21 and a high-mobility second oxide layer 22, the first gate 12 near the first oxide layer 21 is used as the control terminal for driving the transistor, and the fourth gate 16 near the second oxide layer 22 is used as the control terminal for switching the transistor. For the driving transistor, which is bottom-gate driven with a constant potential input to the top gate, the subthreshold swing can be significantly increased, improving stability and ensuring low grayscale display performance. Furthermore, by setting the first oxide layer 21 to have low mobility, stability is further enhanced. For the switching transistor, which is top-gate driven with a constant potential input to the bottom gate, a smaller aspect ratio is ensured, resulting in a smaller subthreshold swing and high mobility. By adjusting the constant potential of the bottom gate, the electrical properties can be autonomously adjusted and the device stability optimized.

[0053] Optionally, the first constant potential V1 can range from 0V to 1.5V; the second constant potential V2 can range from -3V to 0V. In the dual-gate structure, if one gate is used as the control terminal, the other gate can be used as the auxiliary control terminal. The constant potential connected to the auxiliary control terminal can be set according to requirements, and different constant potentials result in different auxiliary effects. The first gate 12 of the driving transistor T1 is the control terminal, and the second gate 13 is used as the auxiliary control terminal connected to a constant voltage of 0V to 1.5V. The fourth gate 16 of the switching transistor T2 is the control terminal, and the third gate 15 is used as the auxiliary control terminal connected to a constant voltage of -3V to 0V. Furthermore, because the second gate 13 is a top-gate structure, the first constant potential V1 connected to the second gate 13 can achieve fine control of the control terminal of the driving transistor T1. The third gate 15 is a bottom-gate structure, and the second constant potential V2 connected to the third gate 15 is used to control the switching speed and stability of the switching transistor T2.

[0054] Optionally, the first constant potential V1 and the second constant potential V2 can be the same. Then, the second gate 13 of the driving transistor T1 and the third gate 15 of the switching transistor T2 can share a signal line to obtain a constant potential, reducing the wiring density of the display panel and further improving the layout space of the display panel.

[0055] Optionally, the second constant potential V2 can be reused as the reference voltage signal Vref in the pixel circuit. Since the value range of the second constant potential V2 is preferably -3V to 0V, in this embodiment, the second constant potential V2 can be reused as the reference voltage signal Vref in the pixel circuit to further reduce panel wiring and panel power consumption. However, the thickness of the gate insulating layer between the top gate and the active layer is relatively thin. If the first constant potential V1 is negative, it will have a significant impact on the threshold voltage of the driving transistor T1, reducing the stability of the driving transistor T1. Therefore, the driving transistor T1 is preferably positive to improve the subthreshold swing of the driving transistor T1, and the second constant potential V2 is preferably negative to improve the switching speed of the switching transistor T2. Optionally, both the driving transistor T1 and the switching transistor T2 can be N-type transistors. Since the active layer in this embodiment is made of all-oxide material, each transistor in the pixel circuit can be set as an N-type transistor.

[0056] Taking the N-type transistor as an example, Figure 5 A circuit diagram of a pixel circuit is provided for an embodiment of the invention. Figure 6 for Figure 5 Layout diagram of the mid-pixel circuit. Figure 7 for Figure 5 A schematic diagram of the cross-sectional structure of the mid-pixel circuit along line segment a-a'. (Reference) Figures 5 to 7Optionally, the pixel circuit may further include: a storage capacitor Cst and a light-emitting element 111; the switching transistor T2 includes: a first light-emitting control transistor M1, a second light-emitting control transistor M6, a first reset transistor M5, a second reset transistor M7, a threshold compensation transistor M4, and a data writing transistor M2; the control terminal of the first light-emitting control transistor M1 is connected to the light-emitting control signal EMIT; the first terminal of the first light-emitting control transistor M1 is connected to the first power supply signal PVDD; the second terminal of the first light-emitting control transistor M1 is electrically connected to the first terminal of the driving transistor T1; the control terminal of the driving transistor T1 is connected to the first power supply signal PVDD through the storage capacitor Cst; the second terminal of the driving transistor T1 is electrically connected to the first terminal of the second light-emitting control transistor M6; the control terminal of the second light-emitting control transistor M6 is used to connect to the light-emitting control signal EMIT; the second terminal of the second light-emitting control transistor M6 is electrically connected to the first electrode of the light-emitting element 111, and the second electrode of the light-emitting element 111 is connected to the second power supply signal... PVEE; The control terminal of the first reset transistor M5 is connected to the first scan signal SCAN1; The first terminal of the first reset transistor M5 is connected to the reference voltage signal Vref; The second terminal of the first reset transistor M5 is electrically connected to the control terminal of the driving transistor T1; The control terminal of the second reset transistor M7 is connected to the second scan signal SCAN2; The first terminal of the second reset transistor M7 is connected to the reference voltage signal Vref; The second terminal of the second reset transistor M7 is electrically connected to the second terminal of the driving transistor T1; The control terminal of the threshold compensation transistor M4 is connected to the third scan signal SCAN3; The first terminal of the threshold compensation transistor M4 is electrically connected to the control terminal of the driving transistor T1; The second terminal of the threshold compensation transistor M4 is electrically connected to the second terminal of the driving transistor T1; The control terminal of the data writing transistor M2 is connected to the fourth scan signal SCAN4; The first terminal of the data writing transistor M2 is connected to the data signal Vdata; The second terminal of the data writing transistor M2 is electrically connected to the first terminal of the driving transistor T1.

[0057] This embodiment provides a schematic diagram of a 7T1C pixel circuit. It includes one driving transistor T1 and six switching transistors T2 (a first light-emitting control transistor M1, a second light-emitting control transistor M6, a first reset transistor M5, a second reset transistor M7, a threshold compensation transistor M4, and a data writing transistor M2). Figure 5 As shown, each transistor has a dual-gate structure. It should be noted that... Figure 5In the dual-gate structure shown for each transistor, the darker grayscale gate is the top gate, and the lighter grayscale gate is the bottom gate. Therefore, the bottom gate of the driving transistor T1 is the control terminal, and the top gate is connected to the first constant potential V1; for other switching transistors T2, the bottom gate is connected to the second constant potential V2, and the top gate serves as the control terminal. The first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, and the light emission control signal EMIT are used to control the light emission of the pixel circuit. Optionally, the third scan signal SCAN3 is multiplexed to become the fourth scan signal SCAN4. Furthermore, as... Figure 6 As shown, in order to further simplify the film layer setting of the display panel in this embodiment, the first constant potential V1 and the second constant potential V2 are set to be the same. Therefore, this embodiment only needs to set one constant potential transmission line 18.

[0058] refer to Figure 6 and Figure 7 It only shows the film layers of substrate 31, first metal layer 32, active layer 33, second metal layer 34, and source / drain layer 17. Furthermore, Figure 6 A third metal layer 35 is also shown. The third metal layer 35 can be disposed on the side of the first metal layer 32 near the substrate 31, or it can be disposed between the source / drain layer 17 and the substrate 31, so that the first metal layer 32 can be electrically connected to the constant potential transmission line 18 of the third metal layer 35 through the crossover line 19 on the source / drain layer 17. The first metal layer 32 can be provided with a first gate 12 and a third gate 15; the active layer 33 is provided with a first active layer 11 and a second active layer 14; the second metal layer 34 is provided with a second gate 13 and a fourth gate 16; the source / drain layer 17 can be provided with a data line 20 for the output data signal Vdata and the crossover line 19.

[0059] Figure 7 The diagram shows a driving transistor T1 and a switching transistor M5. The top gate (fourth gate 16) of the switching transistor M5 serves as its control terminal, and its bottom gate (third gate 15) is used to connect a constant voltage. The top gate (second gate 13) of the driving transistor T1 is connected to a constant voltage via a connection line 171, and its bottom gate (first gate 12) is electrically connected to the switching transistor M5 as its control terminal. Figure 6 and Figure 7As shown, compared to LTPO display panels, this embodiment modifies the existing complex LTPO process through structural design changes, making the concept of an all-oxide active layer 33 possible. The top gate of the switching transistor serves as the control terminal, and the bottom gate is connected to a constant voltage. The advantage of this structure is that it can autonomously adjust electrical properties and optimize device stability. The bottom gate of the driving transistor T1 serves as the control terminal, and the top gate is connected to a constant voltage, which can significantly increase the subthreshold swing (SS), ensuring low grayscale performance. At the same time, the width-to-length ratio (W / L) requirement for the driving transistor T1 is low, and small-sized devices can meet the performance requirements of the driving transistor T1. Based on this, the active layer 33 adopts a double-layer design (combining a high-mobility film layer and a low-mobility film layer), which can further amplify the advantages brought by the structural changes, meeting the requirements of the switching transistor for low W / L, low SS, and high mobility, and the requirements of the driving transistor for low W / L, high SS, and low mobility, ensuring high PPI. Moreover, the film layer structure is simple, greatly improving the layout space and simplifying the device development difficulty. It is also less susceptible to moisture and other factors, reducing process difficulty and facilitating the mass production requirements of display panels.

[0060] Figure 8 A schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 8 As shown, in another embodiment of the present invention, the present invention also provides a pixel circuit, including:

[0061] The driving transistor T1 includes a driving transistor T3 and at least one switching transistor T4. The driving transistor T1 includes a first active layer 112, a first gate 121 disposed on a first side of the first active layer 112, and a second gate 131 disposed on the first active layer 112 away from the first side. The at least one switching transistor T4 includes a second active layer 141, a third gate 151 disposed on a first side of the second active layer 141, and a fourth gate 161 disposed on the second active layer 141 away from the first side. The first active layer 112 and the second active layer 141 are disposed on the same layer. The first gate 121 serves as the control terminal of the driving transistor T3. The second gate 131 is used to receive a third constant potential V3. The third gate 151 and the fourth gate 161 serve as the control terminals of the switching transistor T4.

[0062] In this embodiment of the invention, the pixel circuit includes a driving transistor and at least one switching transistor. The driving transistor includes a first active layer and a first gate and a second gate on opposite sides of the first active layer. The switching transistor includes a second active layer and a third gate and a fourth gate on opposite sides of the second active layer. The first and second active layers are disposed on the same layer, and the first and third gates are disposed on the same side, as are the second and fourth gates. In this embodiment, the first gate can be used as the control terminal of the driving transistor, and the second gate receives a third constant potential to control the precision of the control terminal. The third and fourth gates are used as the control terminals of the switching transistor. The control methods of the driving transistor control terminal and the switching transistor control terminal are different to achieve different electrical performances, so that the switching transistor has high mobility and the driving transistor has strong stability. In this embodiment, only one all-oxide active layer is set to balance the stability of the driving transistor and the high mobility of the switching transistor. Therefore, this embodiment does not need to set multiple active layers to simultaneously integrate LTPS technology and IGZO technology to meet different electrical performances, simplifying the display panel process, significantly reducing process costs, and improving circuit layout space. In addition, compared to the LTPO process, this embodiment is less susceptible to moisture and other factors, reducing the difficulty of the process and making it easier to meet the mass production requirements of display panels.

[0063] Figure 9 A schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 9 As shown, in another embodiment of the present invention, the present invention also provides a pixel circuit, including:

[0064] A driving transistor T5 and at least one switching transistor T6 are provided. The driving transistor T5 includes a first active layer 113, a first gate 122 disposed on a first side of the first active layer 113, and a second gate 132 disposed on the first active layer 113 away from the first side. The at least one switching transistor T6 includes a second active layer 142, a third gate 152 disposed on a first side of the second active layer 142, and a fourth gate 162 disposed on the second active layer 142 away from the first side. The first active layer 113 and the second active layer 142 are disposed on the same layer. The first gate 122 and the second gate 132 serve as control terminals of the driving transistor T5. The fourth gate 162 serves as control terminal of the switching transistor T6. The third gate 152 is used to receive a fourth constant potential V4.

[0065] In this embodiment of the invention, the pixel circuit includes a driving transistor and at least one switching transistor. The driving transistor includes a first active layer and a first gate and a second gate on opposite sides of the first active layer. The switching transistor includes a second active layer and a third gate and a fourth gate on opposite sides of the second active layer. The first and second active layers are disposed on the same layer, and the first and third gates are disposed on the same side, as are the second and fourth gates. In this embodiment, the first and second gates can be used as the control terminals of the driving transistor, and the fourth gate can be used as the control terminal of the switching transistor. The third gate is connected to a fourth constant potential to control the switching speed and stability of the switching transistor. The control methods of the driving transistor and the switching transistor are different to achieve different electrical performances, so that the switching transistor has high mobility and the driving transistor has strong stability. In this embodiment, only one all-oxide active layer is set to balance the stability of the driving transistor and the high mobility of the switching transistor. Therefore, this embodiment does not need to set multiple active layers to simultaneously integrate LTPS and IGZO technologies to meet different electrical performances, simplifying the display panel process, significantly reducing process costs, and improving circuit layout space. In addition, compared to the LTPO process, this embodiment is less susceptible to moisture and other factors, reducing the difficulty of the process and making it easier to meet the mass production requirements of display panels.

[0066] Based on the same idea, embodiments of the present invention also provide a display panel, such as... Figure 10 As shown, Figure 10 This is a schematic diagram of a display panel provided in an embodiment of the present invention, including a pixel circuit 100 provided in any embodiment of the present invention.

[0067] The display panel provided in the embodiments of the present invention includes the technical features of the pixel circuit provided in any embodiment of the present invention, and has the beneficial effects of the corresponding technical features.

[0068] This invention also provides a display device. Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 11 As shown, the display device provided in this embodiment of the invention includes the display panel 200 described in any embodiment of the invention. The display device can be as follows: Figure 11 The mobile phone shown can also be a computer, television, smart wearable device, etc., and this embodiment does not make any special limitation on it.

[0069] In this embodiment, the display device includes the technical features of the display panel provided in any embodiment of the present invention, and has the beneficial effects of the corresponding features, which will not be described in detail here.

[0070] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: A driving transistor and at least one switching transistor; The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side. At least one of the switching transistors includes a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side; Wherein, the first active layer and the second active layer are disposed on the same layer; the first gate serves as the control terminal of the driving transistor; the fourth gate serves as the control terminal of the switching transistor; the second gate is used to receive a first constant potential; and the third gate is used to receive a second constant potential. The display panel containing the pixel circuit includes at least a substrate, a first metal layer, an active layer, and a second metal layer stacked together. The first active layer and the second active layer are both disposed on the active layer; the first gate and the third gate are disposed on the first metal layer; the fourth gate and the second gate are disposed on the second metal layer.

2. The pixel circuit according to claim 1, characterized in that, The materials of the first active layer and the second active layer are both oxides of a specified metal; The specified metal includes at least one of the following: gallium, hafnium, tin, lanthanum, indium, and zinc.

3. The pixel circuit according to claim 1, characterized in that, Both the first active layer and the second active layer include a first oxide layer and a second oxide layer; The first oxide is disposed on the side of the second oxide layer near the first gate or the third gate; The carrier mobility of the first oxide layer is less than that of the carrier mobility of the second oxide layer.

4. The pixel circuit according to claim 3, characterized in that, The thickness ratio of the first oxide layer to the second oxide layer ranges from 3:1 to 1:

1.

5. The pixel circuit according to claim 3, characterized in that, The first oxide layer comprises indium oxide, gallium oxide, and zinc oxide; The second oxide layer comprises indium oxide, gallium oxide, zinc oxide, and tin oxide.

6. The pixel circuit according to claim 5, characterized in that, The thickness ratio of the first oxide layer to the second oxide layer is 2:

1.

7. The pixel circuit according to claim 1, characterized in that, The first constant potential ranges from 0V to 1.5V; The range of the second constant potential is -3V to 0V.

8. The pixel circuit according to claim 7, characterized in that, The second constant potential is multiplexed as the reference voltage signal in the pixel circuit.

9. The pixel circuit according to claim 6, characterized in that, The first constant potential is the same as the second constant potential.

10. The pixel circuit according to claim 2, characterized in that, Both the driving transistor and the switching transistor are N-type transistors.

11. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes: a storage capacitor and a light-emitting element; the switching transistor includes: a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, a threshold compensation transistor, and a data writing transistor; The control terminal of the first light-emitting control transistor is connected to a light-emitting control signal; the first terminal of the first light-emitting control transistor is connected to a first power supply signal; the second terminal of the first light-emitting control transistor is electrically connected to the first terminal of the driving transistor; the control terminal of the driving transistor is connected to the first power supply signal through the storage capacitor; the second terminal of the driving transistor is electrically connected to the first terminal of the second light-emitting control transistor; the control terminal of the second light-emitting control transistor is used to connect to the light-emitting control signal; the second terminal of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is connected to a second power supply signal. The control terminal of the first reset transistor is connected to a first scan signal; the first terminal of the first reset transistor is connected to a reference voltage signal; the second terminal of the first reset transistor is electrically connected to the control terminal of the driving transistor; the control terminal of the second reset transistor is connected to a second scan signal; the first terminal of the second reset transistor is connected to a reference voltage signal; the second terminal of the second reset transistor is electrically connected to the second terminal of the driving transistor. The control terminal of the threshold compensation transistor is connected to a third scan signal; the first terminal of the threshold compensation transistor is electrically connected to the control terminal of the driving transistor; the second terminal of the threshold compensation transistor is electrically connected to the second terminal of the driving transistor; the control terminal of the data writing transistor is connected to a fourth scan signal; the first terminal of the data writing transistor is connected to a data signal; and the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor.

12. A pixel circuit, characterized in that, include: A driving transistor and at least one switching transistor; The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side. At least one of the switching transistors includes a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side; Wherein, the first active layer and the second active layer are disposed on the same layer; the first gate serves as the control terminal of the driving transistor; the second gate is used to receive a third constant potential; the third gate and the fourth gate serve as the control terminals of the switching transistor; The display panel containing the pixel circuit includes at least a substrate, a first metal layer, an active layer, and a second metal layer stacked together. Both the first active layer and the second active layer are disposed on the active layer; the first gate and the third gate are disposed on the first metal layer; The fourth gate and the second gate are disposed on the second metal layer.

13. A pixel circuit, characterized in that, include: A driving transistor and at least one switching transistor; The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side. At least one of the switching transistors includes a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side; Wherein, the first active layer and the second active layer are disposed on the same layer; the first gate and the second gate serve as the control terminals of the driving transistor; the fourth gate serves as the control terminal of the switching transistor; and the third gate is used to receive a fourth constant potential. The display panel containing the pixel circuit includes at least a substrate, a first metal layer, an active layer, and a second metal layer stacked together. The first active layer and the second active layer are both disposed on the active layer; the first gate and the third gate are disposed on the first metal layer; the fourth gate and the second gate are disposed on the second metal layer.

14. A display panel, characterized in that, Includes the pixel circuit described in any one of claims 1-13.

15. A display device, characterized in that, Includes the display panel described in claim 14.

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