Display device

Abstract

The invention provides a display device which comprises a display panel, and the display panel comprises a gate drive circuit. The gate driving circuit comprises a first power input end, a second power input end and a plurality of cascaded gate driving sub-circuits, wherein each gate driving sub-circuit comprises a plurality of oxide semiconductor transistors. Wherein a grid electrode of the first transistor is electrically connected with a first node, a source electrode is electrically connected with a clock signal input end, and a drain electrode is electrically connected with a scanning signal output end; the source electrode of the second transistor is electrically connected with the first power supply input end; the source electrode of the third transistor is electrically connected with the second power input end. The voltage value of the first power supply input end is higher than the voltage value of the second power supply input end, and negative gate-source voltage bias of the first transistor is formed, so that the leakage current of the first transistor is effectively inhibited, and the problem of abnormal horizontal grain display of the display device is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] In oxide semiconductor display panels, the gate driving circuit is usually implemented by integrating it on the display panel. This design can reduce production costs and improve product integration.

[0003] However, due to the characteristics of oxide semiconductor materials, the threshold voltage of transistors made from them may be offset. In particular, if the threshold voltage of the output control transistor in the gate drive circuit is too small, the display panel may leak. This leakage will cause the scan signal output end to be unable to maintain a stable low level state during the non-selection period, causing display anomalies such as horizontal stripes on the display screen.

[0004] At present, the industry usually adopts methods such as optimizing the transistor process or adding compensation circuits to solve the above problems. However, these solutions either increase the process difficulty and cost, or make the circuit structure more complicated, which is not conducive to improving product yield and reliability. Therefore, how to effectively solve the leakage problem of the gate drive circuit in the oxide semiconductor display panel without significantly increasing the process difficulty and cost has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0005] An object of the present invention is to provide a display device to effectively suppress leakage current of an output control transistor in a gate drive circuit.

[0006] An embodiment of the present application provides a display device, including a display panel, wherein the display panel includes a gate driving circuit, wherein the gate driving circuit includes a first power input terminal, a second power input terminal and a plurality of cascaded gate driving sub-circuits, each of the gate driving sub-circuits includes a plurality of oxide semiconductor transistors, and the plurality of oxide semiconductor transistors in the gate driving sub-circuit include: a first transistor, wherein a gate of the first transistor is electrically connected to a first node of the gate driving sub-circuit, a source is electrically connected to a clock signal input terminal of the gate driving sub-circuit, and a drain is electrically connected to a scan signal output terminal of the gate driving sub-circuit; a second transistor, wherein a gate of the second transistor is electrically connected to a second node of the gate driving sub-circuit, a source is electrically connected to the first power input terminal, and a drain is electrically connected to the scan signal output terminal; and a third transistor, wherein a gate of the third transistor is electrically connected to the second node, a source is electrically connected to the second power input terminal, and a drain is electrically connected to the first node; wherein a voltage value of the first power input terminal is different from a voltage value of the second power input terminal.

[0007] In the above display device, a voltage value of the first power input terminal is higher than a voltage value of the second power input terminal.

[0008] In the above display device, the display device further includes: a source driver chip, the source driver chip is electrically connected to the second power input terminal; and a power management chip, the power management chip is electrically connected to the first power input terminal.

[0009] In the above display device, the source driver chip is also electrically connected to the first power input terminal, and the power management chip is also electrically connected to the second power input terminal.

[0010] In the above display device, the source driver chip includes multiple output terminals. When the source driver chip provides voltage to the first power input terminal, the output impedance of the output terminal of the source driver chip corresponding to the first power input terminal is greater than 1 megohm.

[0011] In the above display device, the display device further includes a flexible circuit board, which connects the power management chip and the display panel; on the flexible circuit board, a first resistor is arranged between the power management chip and the second power input terminal.

[0012] In the above display device, the source driver chip is insulated from the first power input terminal, the source driver chip is electrically connected to the second power input terminal, the power management chip is insulated from the second power input terminal, and the power management chip is electrically connected to the first power input terminal.

[0013] In the above-mentioned display device, the voltage value output by the source driver chip is the same as the voltage value output by the power management chip, a second resistor is arranged between the source driver chip and the second power input terminal, and a third resistor is arranged between the power management chip and the first power input terminal, and the resistance value of the third resistor is greater than the resistance value of the second resistor.

[0014] In the above display device, the voltage value of the first power input terminal is -8.8V to -7.2V, and the voltage value of the second power input terminal is -10.8V to -9.2V.

[0015] In the above display device, the voltage value of the first power input terminal is -8V, and the voltage value of the second power input terminal is -10V.

[0016] In an embodiment of the present application, the first transistor of the gate drive subcircuit serves as an output control transistor, and its gate is electrically connected to the first node. The source of the third transistor is electrically connected to the second power input terminal, and its drain is electrically connected to the first node to pull the potential of the first node down to the voltage value of the second power input terminal. The source of the second transistor is electrically connected to the first power input terminal, and its drain is electrically connected to the scan signal output terminal to pull the potential of the scan signal output terminal down to the voltage value of the first power input terminal. Since the voltage value of the first power input terminal is higher than the voltage value of the second power input terminal (for example, the first power input terminal is -8V and the second power input terminal is -10V), the source (drain) voltage of the first transistor is higher than its gate voltage, forming a negative gate-source voltage bias. This bias voltage can ensure that the control transistor is reliably turned off in a non-conducting state, thereby effectively suppressing the leakage current of the output control transistor in the gate drive circuit, and solving the problem of abnormal horizontal stripes display in the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of a display device provided in an embodiment of the present application.

[0018] Figure 2 yes Figure 1 Schematic diagram of a gate driving sub-circuit in a display device shown.

[0019] Figure 3 yes Figure 2 Schematic diagram of a partial circuit of the gate drive subcircuit shown. DETAILED DESCRIPTION

[0020] The specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0021] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0022] The embodiments of the present application may be combined with each other.

[0023] like Figure 1 As shown, the display device provided in the embodiment of the present application includes a display panel, a timing controller (not shown in the figure), a source driving circuit DIC and a power management chip PMIC. The display panel may be, for example, a liquid crystal display panel.

[0024] The display panel includes a display area AA and a non-display area. The display area AA is provided with m×n pixel units P arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area AA and is used to arrange the drive circuit and various signal lines. The display panel also includes a plurality of scan lines, a plurality of data lines and a gate drive circuit GOA. The plurality of scan lines extend along a first direction and are arranged along a second direction, and the plurality of data lines extend along a second direction and are arranged along the first direction, and the first direction is perpendicular to the second direction. The gate drive circuit GOA is arranged in the non-display area and is electrically connected to the plurality of scan lines. The source drive circuit DIC is electrically connected to the plurality of data lines through a flexible circuit board. The timing controller is electrically connected to the gate drive circuit GOA and the source drive circuit DIC, respectively.

[0025] The display panel includes a thin film transistor array substrate, an opposing substrate, and a liquid crystal layer disposed between the two substrates. The thin film transistor array substrate includes a glass substrate, a first metal layer disposed on the glass substrate, a gate insulating layer disposed on the first metal layer, a semiconductor layer disposed on the gate insulating layer, a second metal layer disposed on the semiconductor layer, a passivation layer disposed on the second metal layer, and a pixel electrode disposed on the passivation layer. The first metal layer includes a scan line, a gate electrode, etc. The second metal layer includes a data line, a source electrode, a drain electrode, etc. The opposing substrate includes a glass substrate, a black matrix disposed on the glass substrate, a color filter layer disposed on the black matrix, and a common electrode disposed on the color filter layer.

[0026] Each pixel unit P includes at least one thin film transistor and a pixel electrode. The gate of the thin film transistor is electrically connected to the corresponding scan line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the corresponding pixel electrode. When the scan line outputs a high-level scan signal, the thin film transistor is turned on, and the data signal on the data line is transmitted to the pixel electrode through the thin film transistor; when the scan line outputs a low-level scan signal, the thin film transistor is turned off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0027] The gate drive circuit GOA includes n-stage cascaded gate drive subcircuits, and each stage of the gate drive subcircuit is electrically connected to a scan line. Under the control of the timing controller, the gate drive subcircuit outputs scan signals in sequence to scan each row of pixel units P in the display area AA line by line. Under the control of the timing controller, the source drive circuit DIC generates and outputs data signals according to the image data. The timing controller is used to receive and process external input image data and timing signals, generate control signals, and transmit image data to the source drive circuit DIC. The power management chip is used to provide operating voltages for various parts of the display device, including providing a common voltage for the common electrode of the liquid crystal display panel, providing a gate drive voltage for the gate drive circuit GOA, and providing a gamma voltage for the source drive circuit DIC.

[0028] like Figure 1 , Figure 2 and Figure 3 As shown, an embodiment of the present application provides a display device, including a display panel, the display panel including a plurality of pixels and at least one gate driving circuit. Two gate driving circuits are arranged on both sides of the display area AA of the display panel. Among them, the gate driving circuit includes a first power input terminal VSSG, a second power input terminal VSSQ and a plurality of cascaded gate driving sub-circuits. Each gate driving sub-circuit includes a plurality of oxide semiconductor transistors, and the plurality of oxide semiconductor transistors in the gate driving sub-circuit include a first transistor T21, a second transistor T32 and a third transistor T42.

[0029] The gate of the first transistor T21 is electrically connected to the first node Q of the gate driving subcircuit, the source of the first transistor T21 is electrically connected to the clock signal input terminal CKn of the gate driving subcircuit, and the drain of the first transistor T21 is electrically connected to the scan signal output terminal Gn of the gate driving subcircuit. The first transistor T21 serves as an output control transistor.

[0030] The gate of the second transistor T32 is electrically connected to the second node K of the gate driving subcircuit, the source of the second transistor T32 is electrically connected to the first power input terminal VSSG, and the drain of the second transistor T32 is electrically connected to the scan signal output terminal Gn.

[0031] The gate of the third transistor T42 is electrically connected to the second node K, the source of the third transistor T42 is electrically connected to the second power input terminal VSSQ, and the drain of the third transistor T42 is electrically connected to the first node Q.

[0032] The voltage value of the first power input terminal VSSG is different from the voltage value of the second power input terminal VSSQ.

[0033] The voltage value of the first power input terminal VSSG is higher than the voltage value of the second power input terminal VSSQ.

[0034] The voltage value of the first power input terminal VSSG is -8.8V to -7.2V, and the voltage value of the second power input terminal VSSQ is -10.8V to -9.2V.

[0035] Preferably, the voltage value of the first power input terminal VSSG is -8V, and the voltage value of the second power input terminal VSSQ is -10V.

[0036] The display device also includes a source driver chip DIC and a power management chip PMIC. The source driver chip DIC is electrically connected to the second power input terminal VSSQ, and the power management chip PMIC is electrically connected to the first power input terminal VSSG. The source driver chip DIC provides a voltage to the second power input terminal VSSQ; the power management chip PMIC provides a voltage to the first power input terminal VSSG. The voltage value of the first power input terminal VSSG is -8 volts, and the voltage value of the second power input terminal VSSQ is -10 volts. By setting the above different voltage values, the leakage current of the first transistor T21 can be effectively suppressed.

[0037] The embodiments of the present application provide two solutions for implementing dual VSS power supplies:

[0038] In the first solution, the source driver chip DIC and the power management chip PMIC are both electrically connected to the first power input terminal VSSG and the second power input terminal VSSQ. That is, on the basis that the source driver chip DIC is electrically connected to the second power input terminal VSSQ and the power management chip PMIC is electrically connected to the first power input terminal VSSG, the source driver chip DIC is also electrically connected to the first power input terminal VSSG, and the power management chip PMIC is also electrically connected to the second power input terminal VSSQ.

[0039] The display device further includes a flexible circuit board, which connects the power management chip PMIC and the display panel. On the flexible circuit board, a first resistor is arranged between the power management chip PMIC and the second power input terminal VSSQ.

[0040] The flexible circuit board adopts a multi-layer metal routing structure to transmit VSSG and VSSQ signals respectively. Specifically, the flexible circuit board adopts a four-layer metal structure, in which the first and fourth metal layers are used to transmit VSSG signals, and the second and third metal layers are used to transmit VSSQ signals. Adjacent metal layers are connected by via arrays to form electrical connections.

[0041] The source driver chip DIC includes a plurality of output terminals, and when the source driver chip DIC provides a voltage to the first power input terminal VSSG, the output impedance of the output terminal of the source driver chip DIC corresponding to the first power input terminal VSSG is greater than 1 megohm. That is, when the power management chip PMIC provides a voltage to the first power input terminal VSSG, the output impedance of the output terminal of the source driver chip DIC connected to the first power input terminal VSSG is greater than 1 megohm.

[0042] On the flexible circuit board, a first resistor is arranged between the power management chip PMIC and the second power input terminal VSSQ, and the first resistor is used for voltage division.

[0043] In the second solution, the source driver chip DIC is only electrically connected to the second power input terminal VSSQ, and the power management chip PMIC is only electrically connected to the first power input terminal VSSG. This solution can be implemented in the following two ways:

[0044] Method 1: The voltage value output by the source driver chip DIC is different from the voltage value output by the power management chip PMIC. Specifically, the source driver chip DIC outputs a voltage of -10 volts, and the power management chip PMIC outputs a voltage of -8 volts, directly forming the required voltage difference.

[0045] At this time, the source driver chip DIC is insulated from the first power input terminal VSSG, the source driver chip DIC is electrically connected to the second power input terminal VSSQ, the power management chip PMIC is insulated from the second power input terminal VSSQ, and the power management chip PMIC is electrically connected to the first power input terminal VSSG.

[0046] Method 2: The voltage value output by the source driver chip DIC is the same as the voltage value output by the power management chip PMIC, but a second resistor is set between the source driver chip DIC and the second power input terminal VSSQ, and a third resistor is set between the power management chip PMIC and the first power input terminal VSSG, and the resistance value of the third resistor is greater than the resistance value of the second resistor, and the voltage difference between the two input terminals is achieved through different voltage-dividing resistors.

[0047] The gate drive subcircuit also includes: a start signal input terminal STV / a second-level transmission signal output terminal STn-4, for receiving a start trigger signal; a reset signal input terminal Reset, for receiving a reset signal; a clock signal input terminal CKn, for receiving a clock signal; a first control signal input terminal LC1, for receiving a first control signal; a second control signal input terminal LC2, for receiving a second control signal; a touch signal input terminal TP, for receiving a touch control signal. A scan signal output terminal Gn, for outputting a gate drive signal; a first-level transmission signal output terminal STn, for transmitting a cascade signal. A first power supply input terminal VSSG, for providing a first low-level power supply; a second power supply input terminal VSSQ, for providing a second low-level power supply. A first node Q, as a key control node; a second node K, as a first reset control node; a third node P, as a second reset control node.

[0048] The gate driving sub-circuit includes a first pull-down unit 101 and a second pull-down unit 102 .

[0049] The first pull-down unit 101 includes a first inverter 1011 and a first pull-down maintainer 1012. The first pull-down maintainer 1012 includes a second transistor T32, a third transistor T42 and a fourth transistor T72. The gate of the second transistor T32 is electrically connected to the second node K, the source of the second transistor T32 is electrically connected to the first power input terminal VSSG, and the drain of the second transistor T32 is electrically connected to the scan signal output terminal Gn. The gate of the third transistor T42 is electrically connected to the second node K, the source of the third transistor T42 is electrically connected to the second power input terminal VSSQ, and the drain of the third transistor T42 is electrically connected to the first node Q. The gate of the fourth transistor T72 is electrically connected to the second node K, the source of the fourth transistor T72 is electrically connected to the second power input terminal VSSQ, and the drain of the fourth transistor T72 is electrically connected to the first stage signal output terminal STn. The first inverter 1011 includes a fifth transistor TrQ, a sixth transistor T55, a seventh transistor T52, an eighth transistor T54, a ninth transistor T51, a tenth transistor T511, and an eleventh transistor T53. The gate of the fifth transistor TrQ is electrically connected to the reset signal input terminal Reset, the source of the fifth transistor TrQ is electrically connected to the second power input terminal VSSQ, and the drain of the fifth transistor TrQ is electrically connected to the second node K. The gate of the sixth transistor T55 is electrically connected to the start signal input terminal STV / the second stage transmission signal output terminal STn-4, the source of the sixth transistor T55 is electrically connected to the second power input terminal VSSQ, and the drain of the sixth transistor T55 is electrically connected to the second node K. The gate of the seventh transistor T52 is electrically connected to the first node Q, and the source of the seventh transistor T52 is electrically connected to the second power input terminal VSSQ. The gate of the eighth transistor T54 is electrically connected to the first node Q, the source of the eighth transistor T54 is electrically connected to the second power supply input terminal VSSQ, and the drain of the eighth transistor T54 is electrically connected to the second node K. The gate of the ninth transistor T51 is electrically connected to the first control signal input terminal LC1, the source of the ninth transistor T51 is electrically connected to the drain of the tenth transistor T511, and the drain of the ninth transistor T51 is electrically connected to the drain of the seventh transistor T52. The gate of the tenth transistor T511 is electrically connected to the first control signal input terminal LC1, and the source of the tenth transistor T511 is electrically connected to the first control signal input terminal LC1. The gate of the eleventh transistor T53 is electrically connected to the drain of the seventh transistor T52, the source of the eleventh transistor T53 is electrically connected to the source of the tenth transistor T511, and the drain of the eleventh transistor T53 is electrically connected to the second node K. The second pull-down unit 102 includes a second inverter 1021 and a second pull-down maintainer 1022. The second pull-down maintainer 1022 includes a twelfth transistor T33, a thirteenth transistor T43 and a fourteenth transistor T73.The gate of the twelfth transistor T33 is electrically connected to the third node P, the source of the twelfth transistor T33 is electrically connected to the first power input terminal VSSG, and the drain of the twelfth transistor T33 is electrically connected to the scan signal output terminal Gn. The gate of the thirteenth transistor T43 is electrically connected to the third node P, the source of the thirteenth transistor T43 is electrically connected to the second power input terminal VSSQ, and the drain of the thirteenth transistor T43 is electrically connected to the first node Q. The gate of the fourteenth transistor T73 is electrically connected to the third node P, the source of the fourteenth transistor T73 is electrically connected to the second power input terminal VSSQ, and the drain of the fourteenth transistor T73 is electrically connected to the first-stage transmission signal output terminal STn.

[0050] The second inverter 1021 includes a fifteenth transistor TrP, a sixteenth transistor T65, a seventeenth transistor T62, an eighteenth transistor T64, a nineteenth transistor T61, a twentieth transistor T611, and a twenty-first transistor T63. The gate of the fifteenth transistor TrP is electrically connected to the reset signal input terminal Reset, the source of the fifteenth transistor TrP is electrically connected to the second power input terminal VSSQ, and the drain of the fifteenth transistor TrP is electrically connected to the third node P. The gate of the sixteenth transistor T65 is electrically connected to the start signal input terminal STV / the second stage transmission signal output terminal STn-4, the source of the sixteenth transistor T65 is electrically connected to the second power input terminal VSSQ, and the drain of the sixteenth transistor T65 is electrically connected to the third node P. The gate of the seventeenth transistor T62 is electrically connected to the first node Q, and the source of the seventeenth transistor T62 is electrically connected to the second power input terminal VSSQ. The gate of the eighteenth transistor T64 is electrically connected to the first node Q, the source of the eighteenth transistor T64 is electrically connected to the second power supply input terminal VSSQ, and the drain of the eighteenth transistor T64 is electrically connected to the third node P. The gate of the nineteenth transistor T61 is electrically connected to the second control signal input terminal LC2, the source of the nineteenth transistor T61 is electrically connected to the drain of the twentieth transistor T611, and the drain of the nineteenth transistor T61 is electrically connected to the drain of the seventeenth transistor T62. The gate of the twentieth transistor T611 is electrically connected to the second control signal input terminal LC2, and the source of the twentieth transistor T611 is electrically connected to the second control signal input terminal LC2. The gate of the twenty-first transistor T63 is electrically connected to the drain of the seventeenth transistor T62, the source of the twenty-first transistor T63 is electrically connected to the second control signal input terminal LC2, and the drain of the twenty-first transistor T63 is electrically connected to the third node P.

[0051] The gate driving sub-circuit further includes a 22nd transistor T11, a 23rd transistor TrQ, a 24th transistor T31, a 25th transistor T41, a 26th transistor T81 and a capacitor Cb. The gate of the 22nd transistor T11 is electrically connected to the start signal input terminal STV / the second stage transmission signal output terminal STn-4, the source of the 22nd transistor T11 is electrically connected to the start signal input terminal STV / the second stage transmission signal output terminal STn-4, and the drain of the 22nd transistor T11 is electrically connected to the first node Q. The gate of the 23rd transistor TrQ is electrically connected to the reset signal input terminal Reset, the source of the 23rd transistor TrQ is electrically connected to the second power supply input terminal VSSQ, and the drain of the 23rd transistor TrQ is electrically connected to the first node Q. The gate of the 24th transistor T31 is electrically connected to the third stage transmission signal output terminal STn+4 / reset signal input terminal Reset, the source of the 24th transistor T31 is electrically connected to the first power supply input terminal VSSG, and the drain of the 24th transistor T31 is electrically connected to the scan signal output terminal Gn. The gate of the twenty-fifth transistor T41 is electrically connected to the fourth-stage transmission signal output terminal STn+6 / reset signal input terminal Reset, the source of the twenty-fifth transistor T41 is electrically connected to the second power input terminal VSSQ, and the drain of the twenty-fifth transistor T41 is electrically connected to the first node Q. The gate of the twenty-sixth transistor T81 is electrically connected to the touch signal input terminal TP, the source of the twenty-sixth transistor T81 is electrically connected to the first power input terminal VSSG, and the drain of the twenty-sixth transistor T81 is electrically connected to the scan signal output terminal Gn. One plate of the capacitor Cb is electrically connected to the scan signal output terminal Gn, and the other plate of the capacitor Cb is electrically connected to the first node Q.

[0052] In the gate driving sub-circuit of the display device of the present application, the first transistor T21 to the twenty-sixth transistor T81 are all N-type thin film transistors.

[0053] In the gate driving subcircuit of the display device of the present application, under normal working conditions, the first power input terminal VSSG provides a voltage of -8 volts, and the second power input terminal VSSQ provides a voltage of -10 volts. A voltage difference of 2 volts is formed between the two power input terminals, and the voltage difference can effectively suppress the leakage current of the first transistor T21.

[0054] Specifically, the potential of the first node Q is pulled down to the level of the second power input terminal VSSQ (-10 volts) through the third transistor T42 or the thirteenth transistor T43, and the potential of the scan signal output terminal Gn is pulled down to the level of the first power input terminal VSSG (-8 volts) through the second transistor T32 or the twelfth transistor T33. Since the source voltage (-8 volts) of the first transistor T21 (the source and drain of the thin film transistor can be interchanged, so the source is represented here) is higher than its gate voltage (-10 volts), the gate-source voltage Vgs (the gate-source voltage difference is represented here because the source and drain of the thin film transistor can be interchanged) of the first transistor T21 is -2 volts, which is much smaller than its threshold voltage. Even if the threshold voltage of the first transistor T21 is less than 0 volts, it can be ensured to be in a reliable off state, thereby effectively preventing leakage.

[0055] In the gate driving subcircuit of the display device of the present application, when the start signal STV / second-stage transmission signal output terminal STn-4 of the current-stage gate driving subcircuit is at a high level, the first node Q is charged to a high level; under the control of the clock signal CKn, the scanning signal output terminal Gn is pulled high through the first transistor T21; when the reset signal Reset is at a high level, the first node Q is discharged to a low level through the twenty-third transistor TrQ. The first pull-down unit 101 (including the first inverter 1011 and the first pull-down maintainer 1012) and the second pull-down unit 102 (including the second inverter 1021 and the second pull-down maintainer 1022) work alternately. When the first pull-down unit 101 works, the second node K is at a high level and the third node P is at a low level; when the second pull-down unit 102 works, the second node K is at a low level and the third node P is at a high level. This alternating working mode reduces the working time of each pull-down subcircuit and improves the reliability of the gate driving subcircuit.

[0056] When the touch signal input terminal TP is at a high level, the scan signal output terminal Gn is pulled down to the level of the first power input terminal VSSG through the twenty-sixth transistor T81, thereby realizing time division multiplexing of display driving and touch driving.

[0057] As an improvement, the display device of the present application further includes a temperature sensor for detecting the operating temperature of the display panel. The temperature sensor is implemented by an NTC thermistor, and the sensitivity of its resistance value to temperature change is not less than 4% / °C, so as to accurately detect the temperature change of the display panel under different working environments.

[0058] The display device adjusts the voltage values ​​of VSSG and VSSQ according to the temperature value detected by the temperature sensor. Specifically, in the low temperature range of -20°C to 0°C, the voltage difference between VSSG and VSSQ increases linearly with decreasing temperature, and the increase slope is 0.05V / °C. For example, when the temperature is -20°C, the voltage difference can reach 3V; when the temperature is -10°C, the voltage difference is about 2.75V; when the temperature is 0°C, the voltage difference is 2.5V.

[0059] In the normal temperature range of 0° C. to 50° C., the voltage difference between the first power signal VSSG and the second power signal VSSQ remains unchanged at 2 V. This is because in this temperature range, the characteristics of the oxide semiconductor device are relatively stable and no temperature compensation is required.

[0060] In the high temperature range of 50℃ to 85℃, the voltage difference decreases linearly with increasing temperature, with a slope of 0.02V / ℃. For example, when the temperature is 50℃, the voltage difference is 2V; when the temperature is 70℃, the voltage difference is about 1.6V; when the temperature reaches 85℃, the voltage difference decreases to 1.5V. This dynamic adjustment method can effectively adapt to the characteristic changes of oxide semiconductor devices at different temperatures.

[0061] Through the above technical solution, the display device of the present application can maintain a stable working state under different temperature environments. In a low temperature environment, since the carrier mobility of the oxide semiconductor device is reduced and the leakage current itself is small, the voltage difference between the first power signal VSSG and the second power signal VSSQ can be appropriately reduced to reduce power consumption. In a high temperature environment, since the threshold voltage of the oxide semiconductor device will drift and cause the leakage current to increase, the ability to suppress the transistor leakage current is enhanced by increasing the voltage difference to ensure the normal operation of the circuit.

[0062] In an embodiment of the present application, the first transistor T21 of the gate driving subcircuit serves as an output control transistor, and its gate is electrically connected to the first node Q. The source of the third transistor T42 is electrically connected to the second power input terminal VSSQ, and its drain is electrically connected to the first node Q, so as to pull the potential of the first node Q down to the voltage value of the second power input terminal VSSQ. The source of the second transistor T32 is electrically connected to the first power input terminal VSSG, and its drain is electrically connected to the scan signal output terminal Gn, so as to pull the potential of the scan signal output terminal Gn down to the voltage value of the first power input terminal VSSG. Since the voltage value of the first power input terminal VSSG is higher than the voltage value of the second power input terminal VSSQ (for example, the first power input terminal VSSG is -8V, and the second power input terminal VSSQ is -10V), the source (drain) voltage of the first transistor T21 is higher than its gate voltage, forming a negative gate-source voltage bias. This bias voltage can ensure that the control transistor is reliably turned off in the non-conducting state, thereby effectively suppressing the leakage current of the output control transistor in the gate drive circuit and solving the problem of abnormal horizontal stripes display in the display device.

[0063] The embodiments of the present application are described in detail above, and the contents of this specification should not be construed as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: A display panel is included, wherein the display panel includes a gate driving circuit, wherein the gate driving circuit includes a first power input terminal, a second power input terminal and a plurality of cascaded gate driving sub-circuits, each of the gate driving sub-circuits includes a plurality of oxide semiconductor transistors, and the plurality of oxide semiconductor transistors in the gate driving sub-circuit include: a first transistor, wherein a gate of the first transistor is electrically connected to a first node of the gate driving subcircuit, a source of the first transistor is electrically connected to a clock signal input terminal of the gate driving subcircuit, and a drain of the first transistor is electrically connected to a scan signal output terminal of the gate driving subcircuit; a second transistor, wherein a gate of the second transistor is electrically connected to the second node of the gate driving sub-circuit, a source of the second transistor is electrically connected to the first power input terminal, and a drain of the second transistor is electrically connected to the scan signal output terminal; and a third transistor, wherein a gate of the third transistor is electrically connected to the second node, a source of the third transistor is electrically connected to the second power input terminal, and a drain of the third transistor is electrically connected to the first node; Wherein, a voltage value of the first power input terminal is different from a voltage value of the second power input terminal.

2. The display device according to claim 1, characterized in that The voltage value of the first power input terminal is higher than the voltage value of the second power input terminal.

3. The display device according to claim 2, characterized in that: The display device further includes: a source driver chip, the source driver chip being electrically connected to the second power input terminal; and A power management chip is electrically connected to the first power input terminal.

4. The display device according to claim 3, characterized in that: The source driver chip is also electrically connected to the first power input terminal, and the power management chip is also electrically connected to the second power input terminal.

5. The display device according to claim 4, characterized in that: The source driver chip includes a plurality of output terminals. When the source driver chip provides a voltage to the first power input terminal, an output impedance of an output terminal in the source driver chip corresponding to the first power input terminal is greater than 1 megohm.

6. The display device according to claim 3, characterized in that: The display device further comprises a flexible circuit board, wherein the flexible circuit board connects the power management chip and the display panel; On the flexible circuit board, a first resistor is arranged between the power management chip and the second power input terminal.

7. The display device according to claim 3, characterized in that: The source driver chip is insulated from the first power input terminal, the source driver chip is electrically connected to the second power input terminal, the power management chip is insulated from the second power input terminal, and the power management chip is electrically connected to the first power input terminal.

8. The display device according to claim 3, characterized in that: The voltage value output by the source driver chip is the same as the voltage value output by the power management chip. A second resistor is arranged between the source driver chip and the second power input terminal. A third resistor is arranged between the power management chip and the first power input terminal. The resistance value of the third resistor is greater than the resistance value of the second resistor.

9. The display device according to claim 2, characterized in that: The voltage value of the first power input terminal is -8.8V to -7.2V, and the voltage value of the second power input terminal is -10.8V to -9.2V.

10. The display device according to claim 9, characterized in that: The voltage value of the first power input terminal is -8V, and the voltage value of the second power input terminal is -10V.

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