Display panel and display device

Abstract

The present application belongs to the field of display technology, and specifically relates to a display panel and a display device. The display panel includes a substrate, a pixel unit, a first scan line, and a second scan line. The plurality of pixel units are arranged in an array in the row and column directions, and the first scan line and the second scan line are spaced apart from each other and both extend in the row direction. The pixel unit includes three sub-pixels, one of which is a first sub-pixel and the other two are second sub-pixels; or one of the three sub-pixels is a second sub-pixel and the other two are first sub-pixels. The first sub-pixel and the second sub-pixel each include a transistor, each transistor including a gate. The gate of the first sub-pixel is connected to the first scan line, and the gate of the second sub-pixel is connected to the second scan line. The present application can solve the macroscopic brightness difference of the display panel and improve the shaking head wrinkles.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to a display panel and a display device. Background Art

[0002] In the field of display technology, display panels and display devices are typically driven by thin-film transistors. With the advancement of display technology, a half-source (also known as dual-gate) drive method is often used to drive pixel arrays to reduce costs. This dual-gate drive method can halve the number of data lines compared to traditional drive methods, thereby reducing the number of source driver circuits, and thus the number of driver chips, thereby lowering costs.

[0003] However, existing dual-gate drive display panels are prone to vertical stripe defects such as shaking head stripes. Summary of the Invention

[0004] The purpose of the present application is to solve the problem of shaking head wrinkles occurring in dual-gate drive display panels in the prior art.

[0005] In a first aspect, the present application provides a display panel, comprising a base substrate and a pixel unit formed on the base substrate, wherein a plurality of the pixel units are arranged in an array in row and column directions, and the display panel further comprises a first scan line and a second scan line arranged between two adjacent rows of the pixel units, the first scan line and the second scan line being spaced apart from each other and both extending in the row direction; the pixel unit comprises three sub-pixels, one of the three sub-pixels being a first sub-pixel and the other two of the three sub-pixels being second sub-pixels; or one of the three sub-pixels being a second sub-pixel and the other two of the three sub-pixels being first sub-pixels; the first sub-pixel and the second sub-pixel both comprising a transistor, the transistor both comprising a gate, the gate in the first sub-pixel being connected to the first scan line, and the gate in the second sub-pixel being connected to the second scan line.

[0006] In an exemplary embodiment of the present application, the pixel units in adjacent rows are arranged in the same manner.

[0007] In an exemplary embodiment of the present application, the arrangement of the pixel units in the nth row is the same as the arrangement of the pixel units in the n+1th row, the arrangement of the pixel units in the n+2th row is the same as the arrangement of the pixel units in the n+3th row, and the arrangement of the pixel units in the n+2th row is different from the arrangement of the pixel units in the n+1th row;

[0008] Wherein, n=1+4N, and N is a natural number greater than or equal to 0.

[0009] In an exemplary embodiment of the present application, the transistor further includes a semiconductor layer and a source electrode and a drain electrode respectively connected to opposite ends of the semiconductor layer, and an orthographic projection of the semiconductor layer on the substrate is located within an orthographic projection of the gate electrode on the substrate;

[0010] The source electrodes of the first sub-pixel and the second sub-pixel each include a protrusion and an extension portion connected to each other, the protrusion pointing to the drain, an orthographic projection of the protrusion on the substrate overlapping an orthographic projection of the semiconductor layer on the substrate, and the extension portion being provided on a side of the protrusion away from the drain;

[0011] The direction from the source electrode to the drain electrode in the first sub-pixel is the same as the direction from the source electrode to the drain electrode in the second sub-pixel.

[0012] In an exemplary embodiment of the present application, the first sub-pixel further includes a first pixel electrode, the first pixel electrode including a first electrode body portion, a first electrode connecting portion, and a first electrode line for connecting the first electrode body portion and the first electrode connecting portion, an orthographic projection of the first electrode connecting portion on the base substrate and an orthographic projection of an extension portion of the source electrode in the first sub-pixel on the base substrate having at least an overlapping area, and the first electrode connecting portion is electrically connected to the extension portion in the first sub-pixel through a first via hole;

[0013] The second sub-pixel also includes a second pixel electrode, which includes a second electrode body portion, a second electrode connecting portion, and a second electrode line for connecting the second electrode body portion and the second electrode connecting portion. The orthographic projection of the second electrode connecting portion on the base substrate and the orthographic projection of the extension portion of the source electrode in the second sub-pixel on the base substrate have at least an overlapping area, and the second electrode connecting portion is electrically connected to the extension portion in the second sub-pixel through a second via hole.

[0014] In an exemplary embodiment of the present application, a plurality of closed first openings are provided on the first scanning line, the first openings correspond one-to-one to the first sub-pixels, and the orthographic projections of the first electrode connecting portions on the base substrate are located within the orthographic projections of the first openings on the base substrate;

[0015] A plurality of closed second openings are provided on the second scanning line, the second openings corresponding to the second sub-pixels one-to-one, and the orthographic projection of the second electrode connecting portion on the base substrate is located within the orthographic projection of the second opening on the base substrate.

[0016] In an exemplary embodiment of the present application, the first sub-pixel and the second sub-pixel each include a common electrode, the common electrode including a main frame, an extended electrode block, and an extension line connecting the main frame and the extended electrode block; the common electrodes between adjacent sub-pixels are connected via the main frame; an orthographic projection of the extended electrode block on the base substrate and an orthographic projection of the extension portion on the base substrate have at least an overlapping area;

[0017] The extended electrode block of the first sub-pixel and the extended electrode block of the second sub-pixel are respectively arranged on opposite sides of the main frame, the extension line of the first sub-pixel is extended in the direction from the first scanning line to the second scanning line, and the extension line of the second sub-pixel is extended in the direction from the second scanning line to the first scanning line.

[0018] In an exemplary embodiment of the present application, the display panel further includes a data line extending in the column direction, wherein the data line is connected to the drain electrode;

[0019] The first scan line includes a first connection line, a second connection line, and a third connection line, the first connection line and the third connection line are extended in the row direction, and the first connection line and the third connection line are parallel to each other, one end of the second connection line is connected to the first connection line, and the other end of the second connection line is connected to the third connection line, the second connection line is extended in the column direction, the orthographic projection of the second connection line on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the first electrode connection portion on the base substrate, and the end of the third connection line away from the second connection line is connected to the gate of the first sub-pixel;

[0020] The second scan line includes a fourth connection line, a fifth connection line and a sixth connection line, the fourth connection line and the sixth connection line are extended in the row direction, and the fourth connection line is parallel to the first connection line, the sixth connection line is parallel to the third connection line, one end of the fifth connection line is connected to the fourth connection line, and the other end of the fifth connection line is connected to the sixth connection line, the fifth connection line is extended in the column direction and is parallel to the second connection line, the orthographic projection of the fifth connection line on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the second electrode connection portion on the base substrate, and the end of the sixth connection line away from the fifth connection line is connected to the gate of the second sub-pixel.

[0021] In an exemplary embodiment of the present application, the length of the second electrode line in the column direction is greater than the length of the first electrode line in the column direction;

[0022] The first pixel electrode further includes a first electrode strip, the first electrode strip being provided on a side of the first electrode body away from the first electrode line and extending in a direction away from the first electrode connecting portion, and the first electrode strip and the first electrode line being located in the same column;

[0023] The second pixel electrode further includes a second electrode strip, the second electrode strip being provided on a side of the second electrode body away from the second electrode line and extending in a direction away from the second electrode connecting portion, and the second electrode strip and the second electrode line being located in the same column;

[0024] The sum of the lengths of the first electrode strips and the first electrode lines in the column direction is equal to the sum of the lengths of the second electrode strips and the second electrode lines in the column direction.

[0025] A second aspect of the present application provides a display device, comprising: a flexible circuit board; a chip-on-film connected to the flexible circuit board; and a display panel as described in any one of the above, wherein the display panel is electrically connected to the flexible circuit board via the chip-on-film.

[0026] The display panel and display device of the present application have at least the following beneficial effects:

[0027] The display panel of the present application includes a substrate and pixel units, wherein the plurality of pixel units are arranged in an array in row and column directions. The display panel also includes a first scan line and a second scan line disposed between two adjacent rows of pixel units, the first scan line and the second scan line being spaced apart and both extending in the row direction. The pixel unit includes three sub-pixels, one of which is a first sub-pixel and the other two of which are second sub-pixels; or one of which is a second sub-pixel and the other two of which are first sub-pixels. The first sub-pixel and the second sub-pixel each include a transistor, each transistor including a gate, the gate of the first sub-pixel being connected to the first scan line and the gate of the second sub-pixel being connected to the second scan line. The first scan line and the second scan line are used to control the turning on and off of different sub-pixels, respectively, so that some sub-pixels in the same pixel unit are in an on state and others are in an off state. This can reduce the macroscopic brightness difference caused by turning all sub-pixels on and off in the same pixel unit of the display panel, thereby improving head shake wrinkles.

[0028] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0029] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0031] Figure 1 A schematic diagram of the planar structure of the first display panel provided in the first or sixth embodiment of the present application is shown.

[0032] Figure 2 A schematic diagram of the planar structure of the second display panel provided in the first or sixth embodiment of the present application is shown.

[0033] Figure 3 A schematic diagram of the planar structure of the third display panel provided in the first or sixth embodiment of the present application is shown.

[0034] Figure 4 A schematic diagram of the planar structure of the fourth display panel provided in the first or sixth embodiment of the present application is shown.

[0035] Figure 5 A schematic diagram of the planar structure of the fifth display panel provided in the first or sixth embodiment of the present application is shown.

[0036] Figure 6 A schematic diagram of the planar structure of the sixth display panel provided in the first or sixth embodiment of the present application is shown.

[0037] Figure 7 A schematic structural diagram of the first sub-pixel and the second sub-pixel provided in the first or sixth embodiment of the present application is shown.

[0038] Figure 8 It shows a structural schematic diagram of the data line, the first / second source electrode, the first / second drain electrode and the first / second semiconductor layer provided on the base substrate according to the first or sixth embodiment of the present application.

[0039] Figure 9 A schematic structural diagram of the first / second scan lines and the first / second common electrode lines provided in the first or sixth embodiment of the present application are provided on the base substrate is shown.

[0040] Figure 10 A schematic structural diagram of the first pixel electrode and the second pixel electrode provided in Example 1 or Example 6 of the present application is shown.

[0041] Figure 11 Schematic diagrams of the cross-sectional structure of a storage capacitor formed by the common electrode and the first / second pixel electrode provided in Embodiments 1 to 6 of the present application are shown.

[0042] Figure 12 A schematic cross-sectional structure diagram of a storage capacitor formed by the first / second source and the pixel electrode provided in Embodiments 1 to 6 of the present application is shown.

[0043] Figure 13 A schematic structural diagram of the first sub-pixel and the second sub-pixel provided in the second or sixth embodiment of the present application is shown.

[0044] Figure 14 A structural schematic diagram is shown in which the first pixel electrode provided in the third or sixth embodiment of the present application is provided with a first electrode strip and the second pixel electrode is provided with a second electrode strip.

[0045] Figure 15 A schematic structural diagram of the pixel electrode provided in the third, fifth or sixth embodiment of the present application is shown.

[0046] Figure 16 A schematic structural diagram showing that the first / second source provided in the fourth or sixth embodiment of the present application also includes a first / second overlapping portion.

[0047] Figure 17 A schematic structural diagram of the first / second source and the first / second drain provided in the fourth or sixth embodiment of the present application is shown.

[0048] Figure 18 It shows a structural schematic diagram in which the first pixel electrode provided in the fourth or sixth embodiment of the present application further includes a fifth / sixth electrode block.

[0049] Figure 19 A structural schematic diagram of the first / second openings provided in the fifth or sixth embodiment of the present application is shown.

[0050] Figure 20 A schematic structural diagram of the first / second electrode connection portion located in the first / second opening in the fifth or sixth embodiment of the present application is shown.

[0051] Figure 21 A schematic structural diagram of the second type of the first / second electrode connection portion located in the first / second opening in the fifth or sixth embodiment of the present application is shown.

[0052] Description of reference numerals:

[0053] 10. Display device; 100. Display panel; 110. Base substrate;

[0054] 120, pixel unit; 120a, first pixel unit; 120b, second pixel unit; 120c, third pixel unit; 120d, fourth pixel unit;

[0055] 1210, first sub-pixel; 1211, first transistor; 12110, first gate; 12111, first semiconductor layer; 12112, first source; 12112a, first protrusion; 12112b, first extension; 12112c, first overlapping portion; 12113, first drain;

[0056] 1212, first common electrode; 12120, first main frame; 121200, ring frame; 121201, second electrode trunk; 12121, first extended electrode block; 12122, first extension line;

[0057] 1213, first pixel electrode; 12130, first electrode connecting portion; 12131, first electrode body; 121310, first column trunk; 121311, first row trunk; 12132, first electrode line; 12133, first electrode strip; 12134, fifth electrode block;

[0058] 1220, second sub-pixel; 1221, second transistor; 12210, second gate; 12211, second semiconductor layer; 12212, second source; 12212a, second protrusion; 12212b, second extension; 12212c, second overlapping portion; 12213, second drain;

[0059] 1222, second common electrode; 12220, second main frame; 12221, second extended electrode block; 12222, second extension line;

[0060] 1223, second pixel electrode; 12230, second electrode connecting portion; 12231, second electrode body; 122310, second column trunk; 122311, second row trunk; 12232, second electrode line; 12233, second electrode strip; 12234, sixth electrode block;

[0061] 130, first scanning line; 131, first connecting line; 1310, first extension portion; 132, second connecting line; 133, third connecting line; 134, first opening;

[0062] 140, second scanning line; 141, fourth connecting line; 1410, second extension portion; 142, fifth connecting line; 143, sixth connecting line; 144, second opening;

[0063] 150, first via hole; 160, second via hole; 170, data line; 171, main data line; 172, first branch data line; 173, second branch data line; 200, flexible circuit board; 300, chip-on-film; M, main pixel unit. DETAILED DESCRIPTION

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0065] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0066] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0067] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0068] Example 1

[0069] Figure 1 A schematic diagram of the planar structure of the first display panel provided in this application is shown. Figure 2 A schematic diagram of the planar structure of the second display panel provided in this application is shown. Figure 3 A schematic diagram of the planar structure of the third display panel provided in this application is shown. Figure 4A schematic diagram of the planar structure of the fourth display panel provided in this application is shown. Figure 5 A schematic diagram of the planar structure of the fifth display panel provided in the present application is shown. Figure 6 A schematic diagram of the planar structure of the sixth display panel provided in the present application is shown.

[0070] See also Figures 1 to 6 As shown, the first embodiment of the present application provides a display panel 100 , which may include a base substrate 110 and a plurality of pixel units 120 .

[0071] The base substrate 110 can be a glass substrate, but can also be a substrate made of other materials, such as PI material.

[0072] See also Figures 1 to 6 As shown, a plurality of pixel units 120 may be arranged in an array along a row direction X and a column direction Y on the base substrate 110 .

[0073] In some embodiments of this application, see Figures 1 to 6 As shown, the display panel 100 further includes a first scan line 130 and a second scan line 140. The first scan line 130 and the second scan line 140 are sequentially arranged in a column direction Y, and the first scan line 130 is located above the second scan line 140. The first scan line 130 and the second scan line 140 are both extended in the row direction X.

[0074] In some embodiments of this application, see Figure 1 As shown, each pixel unit 120 may include three sub-pixels, one of which is a first sub-pixel 1210 and the other two are second sub-pixels 1220. Alternatively, one of the three sub-pixels is a second sub-pixel 1220 and the other two are first sub-pixels 1210.

[0075] In some embodiments, each pixel unit 120 may also include more than three sub-pixels, as long as not all of the sub-pixels in the pixel unit 120 are first sub-pixels 1210 or not all of the sub-pixels in the pixel unit 120 are second sub-pixels 1220 .

[0076] Figure 7 A schematic structural diagram of the first sub-pixel and the second sub-pixel of the present application is shown. Figure 8 A schematic structural diagram of the data line, semiconductor layer, source electrode and drain electrode of the present application is shown. Figure 9 A schematic diagram of the common electrode, gate, first scan line and second scan line of the present application is shown.

[0077] In some embodiments of this application, see Figures 7 to 9As shown, the first sub-pixel 1210 may include a first transistor 1211. The first transistor 1211 includes a first gate electrode 12110, a first semiconductor layer 12111, and a first source electrode 12112 and a first drain electrode 12113 disposed on the same layer. The first gate electrode 12110 is connected to the first scan line 130 to transmit a first scan signal. A gate insulating layer (not shown) is disposed between the first gate electrode 12110 and the first semiconductor layer 12111 to insulate the first gate electrode 12110 from the first semiconductor layer 12111.

[0078] It should be noted that, see Figure 7 As shown, the orthographic projection of the first semiconductor layer 12111 on the base substrate 110 can be located within the orthographic projection of the first gate 12110 on the base substrate 110. The first source electrode 12112 and the first drain electrode 12113 are respectively overlapped on the source and drain doped regions of the first semiconductor layer 12111; that is, the first source electrode 12112 and the first drain electrode 12113 are respectively overlapped on opposite ends of the first semiconductor layer 12111.

[0079] Accordingly, see Figures 7 to 9 As shown, the second sub-pixel 1220 may include a second transistor 1221. The second transistor 1221 includes a second gate electrode 12210, a second semiconductor layer 12211, and a second source electrode 12212 and a second drain electrode 12213 disposed on the same layer. The second gate electrode 12210 is connected to the second scan line 140 to transmit a second scan signal. A gate insulating layer is provided between the second gate electrode 12210 and the second semiconductor layer 12211 to insulate the second gate electrode 12210 from the second semiconductor layer 12211.

[0080] It is worth mentioning that the scan signal on the first scan line 130 controls the first transistor 1211 of the first sub-pixel 1210 in the pixel unit 120 to turn on or off, and the scan signal on the second scan line 140 controls the second transistor 1221 of the second sub-pixel 1220 in the pixel unit 120 to turn on or off, and both control different sub-pixels in the pixel unit 120 respectively.

[0081] The first scanning line 130 and the second scanning line 140 can be made of metal or alloy materials, such as molybdenum, aluminum and titanium, to ensure good electrical conductivity, but are not limited thereto and can also be made of other materials with good electrical conductivity.

[0082] It should be noted that the orthographic projection of the second semiconductor layer 12211 on the base substrate 110 may be located within the orthographic projection of the second gate 12210 on the base substrate 110. The second source electrode 12212 and the second drain electrode 12213 are respectively overlapped on the source and drain doped regions of the second semiconductor layer 12211; that is, the second source electrode 12212 and the second drain electrode 12213 are respectively overlapped on opposite ends of the second semiconductor layer 12211.

[0083] In addition, the first gate electrode 12110, the second gate electrode 12210, the first scan line 130 and the second scan line 140 are arranged on the same layer, the first source electrode 12112, the first drain electrode 12113, the second source electrode 12212, the second drain electrode 12213 and the data line 170 described below are arranged on the same layer, and the first semiconductor layer 12111 and the second semiconductor layer 12211 are arranged on the same layer.

[0084] In addition, in this application, "same-layer arrangement" refers to the use of the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to a mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0085] It is worth mentioning that the number and arrangement of the first sub-pixels 1210 and the second sub-pixels 1220 in the pixel units of adjacent rows are the same.

[0086] In the same row, the number of first sub-pixels 1210 and the number of second sub-pixels 1220 in adjacent pixel units 120 may be equal or unequal.

[0087] For example, in the same row, a pixel unit 120 includes one first sub-pixel 1210 and two second sub-pixels 1220, and an adjacent pixel unit 120 may include one first sub-pixel 1210 and two second sub-pixels 1220, that is, the number of first sub-pixels 1210 and the number of second sub-pixels 1220 in adjacent pixel units 120 are equal. Alternatively, in the same row, a pixel unit 120 includes one first sub-pixel 1210 and two second sub-pixels 1220, and an adjacent pixel unit 120 may include one second sub-pixel 1220 and two first sub-pixels 1210, that is, the number of first sub-pixels 1210 and the number of second sub-pixels 1220 in adjacent pixel units 120 are not equal.

[0088] In addition, in the same row, the arrangement of the first sub-pixels 1210 and the second sub-pixels 1220 in adjacent pixel units 120 may be the same or different.

[0089] For example, in the same row, adjacent pixel units 120 include the same number of first sub-pixels 1210 and second sub-pixels 1220, and each pixel unit 120 includes one first sub-pixel 1210 and two second sub-pixels 1220. The sub-pixels in one pixel unit 120 may be arranged as a first sub-pixel 1210, a second sub-pixel 1220, and a second sub-pixel 1220, while the sub-pixels in the adjacent pixel unit 120 may be arranged as a first sub-pixel 1210, a second sub-pixel 1220, and a second sub-pixel 1220. That is, in the same row, the sub-pixels of adjacent pixel units 120 are arranged in the same manner. Alternatively, the arrangement of the sub-pixels in a pixel unit 120 may be the first sub-pixel 1210, the second sub-pixel 1220, and the second sub-pixel 1220, and the arrangement of the sub-pixels in the adjacent pixel unit 120 may be the second sub-pixel 1220, the first sub-pixel 1210, and the second sub-pixel 1220, that is, in the same row: the arrangement of the sub-pixels in adjacent pixel units 120 is different.

[0090] In some embodiments of the present application, the display panel 100 includes a plurality of main pixel units M arranged in an array on a base substrate 110. The sub-pixels in two adjacent rows of main pixel units M are arranged in the same manner. Each main pixel unit M includes a first pixel unit 120 a, a second pixel unit 120 b, a third pixel unit 120 c, and a fourth pixel unit 120 d, and the first pixel unit 120 a, the second pixel unit 120 b, the third pixel unit 120 c, and the fourth pixel unit 120 d are arranged sequentially in the same row direction X.

[0091] The following description will provide an exemplary description of the arrangement of sub-pixels in the first pixel unit 120 a , the second pixel unit 120 b , the third pixel unit 120 c , and the fourth pixel unit 120 d , but the present invention is not limited thereto.

[0092] For an example of the first option, see Figure 1As shown, the first pixel unit 120a includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged in the following manner: a red second sub-pixel 1220, a green second sub-pixel 1220, and a blue first sub-pixel 1210 in the row direction X. The second pixel unit 120b includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged in the following manner: a red first sub-pixel 1210, a green second sub-pixel 1220, and a blue second sub-pixel 1220 in the row direction X. The third pixel unit 120c includes two first sub-pixels 1210 and one second sub-pixel 1220, and the sub-pixels are arranged in the following manner: a red first sub-pixel 1210, a green first sub-pixel 1210, and a blue second sub-pixel 1220 in the row direction X. The fourth pixel unit 120 d includes two first sub-pixels 1210 and one second sub-pixel 1220 , and the sub-pixels are arranged in the row direction X as follows: a red second sub-pixel 1220 , a green first sub-pixel 1210 , and a blue first sub-pixel 1210 .

[0093] For a second alternative example, see Figure 2 As shown, the first pixel unit 120a includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged in the following manner: a red first sub-pixel 1210, a green second sub-pixel 1220, and a blue second sub-pixel 1220 in the row direction X. The second pixel unit 120b includes two first sub-pixels 1210 and one second sub-pixel 1220, and the sub-pixels are arranged in the following manner: a red first sub-pixel 1210, a green first sub-pixel 1210, and a blue second sub-pixel 1220 in the row direction X. The third pixel unit 120c includes two first sub-pixels 1210 and one second sub-pixel 1220, and the sub-pixels are arranged in the following manner: a red second sub-pixel 1220, a green first sub-pixel 1210, and a blue first sub-pixel 1210 in the row direction X. The fourth pixel unit 120 d includes two second sub-pixels 1220 and one first sub-pixel 1210 , and the sub-pixels are arranged in the row direction X as follows: a red second sub-pixel 1220 , a green second sub-pixel 1220 , and a blue first sub-pixel 1210 .

[0094] For a third alternative example, see Figure 3As shown, the first pixel unit 120a includes two first sub-pixels 1210 and one second sub-pixel 1220, and the sub-pixels are arranged in the following manner: a red first sub-pixel 1210, a green first sub-pixel 1210, and a blue second sub-pixel 1220 in the row direction X. The second pixel unit 120b includes two first sub-pixels 1210 and one second sub-pixel 1220, and the sub-pixels are arranged in the following manner: a red second sub-pixel 1220, a green first sub-pixel 1210, and a blue first sub-pixel 1210 in the row direction X. The third pixel unit 120c includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged in the following manner: a red second sub-pixel 1220, a green second sub-pixel 1220, and a blue first sub-pixel 1210 in the row direction X. The fourth pixel unit 120 d includes two second sub-pixels 1220 and one first sub-pixel 1210 , and the sub-pixels are arranged in the row direction X as follows: a red first sub-pixel 1210 , a green second sub-pixel 1220 , and a blue second sub-pixel 1220 .

[0095] For a fourth alternative example, see Figure 4 As shown, the first pixel unit 120a includes two first sub-pixels 1210 and one second sub-pixel 1220, and the sub-pixels are arranged in the following manner: a red second sub-pixel 1220, a green first sub-pixel 1210, and a blue first sub-pixel 1210 in the row direction X. The second pixel unit 120b includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged in the following manner: a red second sub-pixel 1220, a green second sub-pixel 1220, and a blue first sub-pixel 1210 in the row direction X. The third pixel unit 120c includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged in the following manner: a red first sub-pixel 1210, a green second sub-pixel 1220, and a blue second sub-pixel 1220 in the row direction X. The fourth pixel unit 120 d includes two first sub-pixels 1210 and one second sub-pixel 1220 , and the sub-pixels are arranged in the row direction X as follows: a red first sub-pixel 1210 , a first green sub-pixel, and a blue second sub-pixel 1220 .

[0096] For a fifth alternative example, see Figure 5As shown, the first pixel unit 120a includes two first sub-pixels 1210 and one second sub-pixel 1220, and the sub-pixels are arranged in the following manner: a red first sub-pixel 1210, a green second sub-pixel 1220, and a blue first sub-pixel 1210 in the row direction X. The second pixel unit 120b includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged in the following manner: a red second sub-pixel 1220, a green first sub-pixel 1210, and a blue second sub-pixel 1220 in the row direction X. The third pixel unit 120c is the same as the first pixel unit 120a, and includes two first sub-pixels 1210 and one second sub-pixel 1220, and the sub-pixels are arranged in the following manner: a red first sub-pixel 1210, a green second sub-pixel 1220, and a blue first sub-pixel 1210 in the row direction X. The fourth pixel unit 120d is the same as the second pixel unit 120b, and includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged as follows: in the row direction X, a red second sub-pixel 1220, a green first sub-pixel 1210, and a blue second sub-pixel 1220.

[0097] For the sixth optional example, see Figure 6 As shown, the first pixel unit 120a includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged in the following manner: a red second sub-pixel 1220, a green first sub-pixel 1210, and a blue second sub-pixel 1220 in the row direction X. The second pixel unit 120b includes two first sub-pixels 1210 and one second sub-pixel 1220, and the sub-pixels are arranged in the following manner: a red first sub-pixel 1210, a green second sub-pixel 1220, and a blue first sub-pixel 1210 in the row direction X. The third pixel unit 120c is the same as the first pixel unit 120a, and includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged in the following manner: a red second sub-pixel 1220, a green first sub-pixel 1210, and a blue second sub-pixel 1220 in the row direction X. The fourth pixel unit 120d is the same as the second pixel unit 120b, and includes two first sub-pixels 1210 and one second sub-pixel 1220, and the sub-pixels are arranged in the row direction X: a red first sub-pixel 1210, a green second sub-pixel 1220, and a blue first sub-pixel 1210.

[0098] It is worth mentioning that the arrangement of adjacent pixel units 120 in the display panel 100 is not limited to the above arrangement, and may also be other arrangements.

[0099] For example, adjacent pixel units 120 are arranged in the same manner. The display panel 100 includes a plurality of main pixel units M arranged in an array on a base substrate 110. Each main pixel unit M includes a first pixel unit 120a, a second pixel unit 120b, a third pixel unit 120c, and a fourth pixel unit 120d. The first pixel unit 120a includes two second sub-pixels 1220 and one first sub-pixel 1210, and the sub-pixels are arranged in the following manner: a red second sub-pixel 1220, a green first sub-pixel 1210, and a blue second sub-pixel 1220 in the row direction X. The second pixel unit 120b, the third pixel unit 120c, and the fourth pixel unit 120d all have the same arrangement as the first pixel unit 120a: a red second sub-pixel 1220, a green first sub-pixel 1210, and a blue second sub-pixel 1220.

[0100] It can be understood that the red first / second sub-pixel, the green first / second sub-pixel and the blue first / second sub-pixel correspond to sub-pixels emitting corresponding color light. For example, the red first / second sub-pixel emits red light, the green first / second sub-pixel emits green light, and the blue first / second sub-pixel emits blue light.

[0101] In the present application, the first scan line 130 controls the opening and closing of the first sub-pixel 1210, and the second scan line 140 controls the opening and closing of the second sub-pixel 1220. By setting different sub-pixels in the same pixel unit 120, the molecular pixels inside the same pixel unit 120 are turned on and the other part is turned off. This can weaken the macroscopic brightness difference caused by all the sub-pixels in the pixel unit 120 in the display panel 100 being turned on and off, thereby improving the shaking head phenomenon and improving the display effect of the display panel 100.

[0102] It is worth mentioning that see Figure 7 As shown, the channel curvature direction of the first transistor 1211 in the first sub-pixel 1210 is the same as the channel curvature direction of the second transistor 1221 in the second sub-pixel 1220. That is, the direction from the first source 12112 to the first drain 12113 is the same as the direction from the second source 12212 to the second drain 12213. This prevents differences in the parasitic capacitance Cgs generated between the first source 12112 and the first gate 12110 and between the second source 12212 and the second gate 12210 due to manufacturing process factors. This ensures consistent brightness between adjacent sub-pixels at the same grayscale, further reducing the appearance of head shake lines and improving the quality of the display panel 100.

[0103] For example, the direction from the first source electrode 12112 to the first drain electrode 12113 and the direction from the second source electrode 12212 to the second drain electrode 12213 are designed to be the same. When the first / second semiconductor layer shifts left or right due to manufacturing process reasons, the area covered by the first semiconductor layer 12111 in the first sub-pixel 1210 and the area covered by the first semiconductor layer 12111 in the second sub-pixel 1220 are the same. In other words, the parasitic capacitance Cgs generated between the first source electrode 12112 and the first gate electrode 12110 is the same as the parasitic capacitance Cgs generated between the second source electrode 12212 and the second gate electrode 12210. This ensures consistent pixel brightness at the same grayscale, reduces the appearance of head shake lines, and improves the quality of the display panel 100.

[0104] In some embodiments of the present application, the scanning direction in the present application is scanned from the first scanning line 130 to the second scanning line 140 (G1→G2), that is, the first transistor 1211 of the first sub-pixel 1210 in the pixel unit 120 is first turned on, and then the second transistor 1221 of the second sub-pixel 1220 in the pixel unit 120 is turned on.

[0105] In this way, when the first scan line 130 controls the first transistor 1211 in the first sub-pixel 1210 to turn on, the second sub-pixel 1220 is affected by the parasitic capacitance Cgs between the first source 12112 and the first gate 12110 in the first sub-pixel 1210 and generates a feedthrough voltage (Feedthrough△V). However, after scanning the first scan line 130, the second scan line 140 is scanned again, so that the second sub-pixel 1220 is charged with its own preset signal. The final charging effect of the second sub-pixel 1220 will not be affected by the feedthrough voltage (Feedthrough△V) generated by the parasitic capacitance Cgs between the first source 12112 and the first gate 12110 in the first sub-pixel 1210, thereby reducing the difference in brightness between the first sub-pixel 1210 and the second sub-pixel 1220, further reducing the shaking head problem of the display panel 100, and improving the display quality of the display panel 100.

[0106] For example, a first scan line G1, a second scan line G2, a third scan line G3, and a fourth scan line G4 are sequentially provided from top to bottom. The first scan line G1 and the second scan line G2 are located between two adjacent rows of pixel units 120, and the third scan line G3 and the fourth scan line G4 are located between another two adjacent rows of pixel units 120. They are respectively connected to transistors in different sub-pixels. For example, the first scan line G1 is connected to the first sub-pixel 1210, the second scan line G2 is connected to the second sub-pixel 1220, the third scan line G3 is connected to the third sub-pixel, and the fourth scan line G4 is connected to the fourth sub-pixel. The first sub-pixel 1210 and the second sub-pixel 1220 are arranged in the same row and adjacent to each other, the first sub-pixel 1210 and the third sub-pixel are arranged in the same column and adjacent to each other, the third sub-pixel and the fourth sub-pixel are arranged in the same row and adjacent to each other, and the second sub-pixel 1220 and the fourth sub-pixel are arranged in the same column and adjacent to each other.

[0107] The scanning direction is the direction of the first scan line G1, the second scan line G2, the third scan line G3, and the fourth scan line G4 (G1→G2→G3→G4). When the second scan line G2 is turned on, the third sub-pixel is affected by the feedthrough voltage (Feedthrough△V) generated by the parasitic capacitance Cgs between the gate and the source of the second sub-pixel 1220. However, when the third scan line G3 is turned on immediately afterwards, the third sub-pixel is charged with its own preset signal. The final charging effect of the third sub-pixel is not affected by the feedthrough voltage (Feedthrough△V) generated by the parasitic capacitance Cgs between the gate and the source of the second sub-pixel 1220. When the second scan line G2 or the third scan line G3 is turned on, the fourth sub-pixel is affected by the feedthrough voltage (Feedthrough△V) generated by the parasitic capacitance Cgs between the source and gate in the second sub-pixel 1220 and the third sub-pixel, respectively. That is, the fourth sub-pixel is affected by the first feedthrough voltage △V1 in the second sub-pixel 1220 and the second feedthrough voltage △V2 in the third sub-pixel. However, when the fourth scan line G4 is subsequently turned on, the fourth sub-pixel will charge its own preset signal, and the final charging effect of the fourth sub-pixel will not be affected by the feedthrough voltage (Feedthrough△V) generated by the parasitic capacitance Cgs of the second scan line G2 and the parasitic capacitance Cgs of the third scan line G3.

[0108] In this way, the novel pixel architecture in the present application is not affected by the feedthrough voltage (Feedthrough△V) generated by the parasitic capacitance Cgs of the adjacent scan lines, thereby reducing the brightness difference between adjacent sub-pixels and better alleviating the shaking head wrinkle problem.

[0109] In some embodiments of this application, see Figure 8As shown, the first source electrode 12112 includes a first protrusion 12112a and a first extension portion 12112b connected to each other. The first protrusion 12112a points to the first drain electrode 12113. The orthographic projection of the first protrusion 12112a on the base substrate 110 overlaps with the orthographic projection of the first semiconductor layer 12111 on the base substrate 110, that is, the first protrusion 12112a overlaps one end of the first semiconductor layer 12111. The first extension portion 12112b is provided on a side of the first protrusion 12112a away from the first drain electrode 12113.

[0110] Accordingly, see Figure 8 As shown, the second source electrode 12212 includes a second protrusion 12212a and a second extension portion 12212b connected to each other. The second protrusion 12212a points to the second drain electrode 12213. The orthographic projection of the second protrusion 12212a on the base substrate 110 overlaps with the orthographic projection of the second semiconductor layer 12211 on the base substrate 110, that is, the second protrusion 12212a overlaps one end of the second semiconductor layer 12211. The second extension portion 12212b is provided on a side of the second protrusion 12212a away from the second drain electrode 12213.

[0111] In some embodiments of this application, see Figure 9 As shown, the first sub-pixel 1210 further includes a first common electrode 1212 , and the first common electrode 1212 can be provided in the same layer as the first scan line 130 , the second scan line 140 , the first gate 12110 , and the second gate 12210 .

[0112] Among them, see Figure 9 As shown, the first common electrode 1212 includes a first main frame 12120 , a first extended electrode block 12121 , and a first extension line 12122 connecting the first main frame 12120 and the first extended electrode block 12121 .

[0113] In some embodiments of the present application, the orthographic projection of the first extended electrode block 12121 on the base substrate 110 and the orthographic projection of the first extension portion 12112b on the base substrate 110 have at least an overlapping area, thereby increasing the storage capacitance Cst of the first sub-pixel 1210, thereby ensuring that the first sub-pixel 1210 has sufficient storage capacitance Cst to maintain the voltage maintenance capability of the first sub-pixel 1210 and reduce the influence of the parasitic capacitance Cgs generated by its own scanning line and the parasitic capacitance Cpd between the data line 170 and the pixel electrode described below on the first sub-pixel 1210.

[0114] For example, see Figure 7As shown, the orthographic projection of the first extended electrode block 12121 on the base substrate 110 completely coincides with the orthographic projection of the first extension portion 12112b on the base substrate 110, and the first extended electrode block 12121 and the first extension portion 12112b of the first source electrode 12112 form a storage capacitor Cst to ensure that the first sub-pixel 1210 has sufficient storage capacitor Cst to maintain the voltage maintenance capability of the first sub-pixel 1210 and reduce the influence of the parasitic capacitance Cgs generated by its own scanning line and the parasitic capacitance Cpd between the data line 170 and the pixel electrode described below on the first sub-pixel 1210.

[0115] Accordingly, see Figure 9 As shown, the second sub-pixel 1220 further includes a second common electrode 1222 , and the second common electrode 1222 can be provided in the same layer as the first scan line 130 , the second scan line 140 , the first gate 12110 , and the second gate 12210 .

[0116] Among them, see Figure 9 As shown, the second common electrode 1222 includes a second main frame 12220 , a second extended electrode block 12221 , and a second extension line 12222 connecting the second main frame 12220 and the second extended electrode block 12221 .

[0117] The orthographic projection of the second extended electrode block 12221 on the base substrate 110 and the orthographic projection of the second extension portion 12212b on the base substrate 110 have at least an overlapping area, thereby increasing the storage capacitance Cst of the second sub-pixel 1220, thereby ensuring that the second sub-pixel 1220 has sufficient storage capacitance Cst to maintain the voltage maintenance capability of the second sub-pixel 1220 and reduce the influence of the parasitic capacitance Cgs generated by its own scanning line and the parasitic capacitance Cpd between the data line 170 and the pixel electrode described below on the second sub-pixel 1220.

[0118] For example, see Figure 7As shown, the orthographic projection of the second extended electrode block 12221 on the substrate 110 completely overlaps with the orthographic projection of the second extension portion 12212b on the substrate 110. The second extended electrode block 12221 and the second extension portion 12212b of the second source electrode 12212 form a storage capacitor Cst, ensuring that the second sub-pixel 1220 has sufficient storage capacitance Cst to maintain the sustain voltage capability of the second sub-pixel 1220 and reduce the impact of the parasitic capacitance Cgs generated by the scan line itself and the parasitic capacitance Cpd between the data line 170 and the pixel electrode described below on the second sub-pixel 1220. In addition, the formation of the storage capacitor Cst by the second extended electrode block 12221 and the second extension portion 12212b ensures that the storage capacitance Cst of the second sub-pixel 1220 is the same as the storage capacitance Cst of the first sub-pixel 1210, reducing the difference in parasitic capacitance between adjacent sub-pixels and, in turn, reducing the difference in brightness between adjacent sub-pixels.

[0119] It is worth mentioning that the first main frame 12120 of the first sub-pixel 1210 and the second main frame 12220 of the second sub-pixel 1220 are extended in the row direction X, and the first main frame 12120 and the second main frame 12220 are located in the same row. The common electrodes between adjacent sub-pixels can be connected through the main frame. For example, the first sub-pixel 1210 and the second sub-pixel 1220 can be connected through the first main frame 12120, the first sub-pixel 1210 and the second sub-pixel 1220 can also be connected through the main frame, and the second sub-pixel 1220 and the second sub-pixel 1220 can be connected through the second main frame 12220.

[0120] In some embodiments of this application, see Figure 7 and Figure 9 As shown, the first extended electrode block 12121 and the first extended line 12122 and the second extended electrode block 12221 and the second extended line 12222 are respectively located on different sides of the main frame to avoid overlap between the extended electrode blocks and the extension lines and the first scan line 130 and the second scan line 140, and to rationally arrange the first common electrode 1212, the second common electrode 1222, the first scan line 130 and the second scan line 140.

[0121] For example, see Figure 7As shown, the first extended electrode block 12121 and the first extended line 12122 are located below the first main frame 12120, and the second extended electrode block 12221 and the second extended line 12222 are located above the second main frame 12220. In this way, the first source electrode 12112 in the first sub-pixel 1210 corresponds to the first extended electrode block 12121 of its corresponding first common electrode 1212, and the second source electrode 12212 in the second sub-pixel 1220 corresponds to the second extended electrode block 12221 of its adjacent second common electrode 1222 in the column direction Y. This ensures that the second extended electrode block 12221 and the second extended line 12222 do not overlap with the first scan line 130 and the second scan line 140, resulting in a rational layout and improved pixel aperture ratio.

[0122] The first extension line 12122 is arranged in the direction from the first scan line 130 to the second scan line 140, that is, it extends from top to bottom. The orthographic projection of the first extension line 12122 on the base substrate 110 has no overlapping area with the first scan line 130 and the second scan line 140, thereby avoiding the first scan line 130 and the second scan line 140. The second extension line 12222 is arranged in the direction from the second scan line 140 to the first scan line 130, that is, it extends from bottom to top. The orthographic projection of the second extension line 12222 on the base substrate 110 has no overlapping area with the first scan line 130 and the second scan line 140, thereby avoiding the first scan line 130 and the second scan line 140.

[0123] Figure 10 A structural schematic diagram is shown in which the first sub-pixel is provided with a first pixel electrode and the second sub-pixel is provided with a second pixel electrode in the present application. Figure 11 A cross-sectional schematic diagram of the pixel electrode and the common electrode of the present application is shown. Figure 12 A cross-sectional schematic diagram of the pixel electrode, common electrode and source electrode of the present application is shown.

[0124] In some embodiments of this application, see Figure 7 and Figure 10 As shown, the first sub-pixel 1210 further includes a first pixel electrode 1213 . The first pixel electrode 1213 can be connected to the first source electrode 12112 through the first via hole 150 , so that a data signal on the data line 170 described below can be written into the first pixel electrode 1213 .

[0125] See also Figure 7 and Figure 10 As shown, the second sub-pixel 1220 further includes a second pixel electrode 1223 . The second pixel electrode 1223 can be connected to the second source electrode 12212 through a second via hole 160 , so that a data signal on the data line 170 described below can be written into the second pixel electrode 1223 .

[0126] The first pixel electrode 1213 and the second pixel electrode 1223 of the embodiment of the present application may be transparent electrodes. For example, they may be made of ITO (indium tin oxide) material to improve light transmittance, but are not limited thereto and may also be made of other transparent conductive materials.

[0127] For example, see Figure 12 As shown, the first pixel electrode 1213 may be formed after the first source 12112 and the first drain 12113 of the first transistor 1211 are formed, and the second pixel electrode 1223 may be formed after the second source 12212 and the second drain 12213 of the second transistor 1221 are formed. Furthermore, an insulating layer may be provided between the first pixel electrode 1213 and the second pixel electrode 1223 and the metal layer where the source and drain of the transistor are located. The first pixel electrode 1213 may be connected to the first source 12112 of the first transistor 1211 via a first via 150 penetrating this insulating layer, and the second pixel electrode 1223 may be connected to the second source 12212 of the second transistor 1221 via a second via 160 penetrating this insulating layer.

[0128] Among them, see Figure 10 As shown, the first pixel electrode 1213 includes a first electrode connecting portion 12130, a first electrode body portion 12131, and a first electrode line 12132 for connecting the first electrode connecting portion 12130 and the first electrode body portion 12131. The first electrode connecting portion 12130 is electrically connected to the first extension portion 12112b of the first source electrode 12112 through a first via 150, so that a data signal on the first extension portion 12112b is transmitted to the first electrode body portion 12131 through the first via 150, the first electrode connecting portion 12130, and the first electrode line 12132, thereby controlling the deflection angle of the liquid crystal molecules in the display panel 100.

[0129] See also Figure 7 As shown, the orthographic projection of the first electrode connecting portion 12130 on the base substrate 110 overlaps with the orthographic projection of the first extension portion 12112b on the base substrate 110, so as to ensure that the first extension portion 12112b can be electrically connected to the first electrode connecting portion 12130 through the first via 150, thereby ensuring the stability of signal transmission and the convenience of opening the first via 150.

[0130] For example, the orthographic projection of the first electrode connecting portion 12130 on the base substrate 110 completely overlaps with the orthographic projection of the first extension portion 12112 b on the base substrate 110 .

[0131] See also Figure 10As shown, the first electrode body 12131 is a slit electrode, which includes a first column trunk 121310 extending in the column direction Y and a first row trunk 121311 extending in the row direction X. The first column trunk 121310 and the first row trunk 121311 intersect and divide the first electrode body 12131 into four first slit electrode parts (not shown in the figure). The first slit electrode part has a plurality of electrode branches arranged at intervals, and a slit is formed between two adjacent electrode branches in the first slit electrode part.

[0132] Accordingly, see Figure 7 and Figure 10 As shown, the second pixel electrode 1223 includes a second electrode connecting portion 12230, a second electrode main body portion 12231 and a second electrode line 12232 for connecting the second electrode connecting portion 12230 and the second electrode main body portion 12231. The second electrode connecting portion 12230 is electrically connected to the second extension portion 12212b of the second source electrode 12212 through the second via 160, so that the data signal on the second extension portion 12212b is transmitted to the second electrode main body portion 12231 through the second via 160, the second electrode connecting portion 12230 and the second electrode line 12232 to control the deflection angle of the liquid crystal molecules in the display panel 100.

[0133] The orthographic projection of the second electrode connecting portion 12230 on the base substrate 110 overlaps with the orthographic projection of the second extension portion 12212b on the base substrate 110 to ensure that the second extension portion 12212b can be electrically connected to the second electrode connecting portion 12230 through the second via 160, thereby ensuring signal transmission stability and convenience in opening the second via 160.

[0134] For example, the orthographic projection of the second electrode connecting portion 12230 on the base substrate 110 completely overlaps with the orthographic projection of the second extension portion 12212 b on the base substrate 110 .

[0135] See also Figure 10 As shown, the second electrode body 12231 is a slit electrode, which includes a second column trunk 122310 extending in the column direction Y and a second row trunk 122311 extending in the row direction X. The second column trunk 122310 and the second row trunk 122311 intersect and divide the second electrode body 12231 into four second slit electrode parts (not shown in the figure). The second slit electrode part has a plurality of electrode branches arranged at intervals, and a slit is formed between two adjacent electrode branches in the second slit electrode part.

[0136] It is worth mentioning that the storage capacitor Cst in the first sub-pixel 1210 also includes the storage capacitor formed by the first electrode body 12131 and the first main frame 12120. The storage capacitor in the second sub-pixel 1220 also includes the storage capacitor formed by the second electrode body 12231 and the second main frame 12220.

[0137] The conventional common electrode includes a ring-shaped annular frame 121200, and a first electrode trunk (not shown) and a second electrode trunk 121201 disposed within the annular frame 121200. The first electrode trunk and the second electrode trunk 121201 are perpendicular to each other, and the first electrode trunk extends along the column direction Y, while the second electrode trunk 121201 extends along the row direction X. The storage capacitor formed by the conventional common electrode and the pixel electrode includes the storage capacitor formed by the first electrode trunk and the first electrode body 12131, the second electrode trunk 121201 and the first electrode body 12131, and the outer edge of the annular frame 121200 and the first electrode body 12131.

[0138] See also Figure 7 As shown, since there is an overlap between the first extension portion 12112b of the first source electrode 12112 and the first extended electrode block 12121, and there is an overlap between the second extension portion 12212b of the second source electrode 12212 and the second extended electrode block 12221, the storage capacitance of the first sub-pixel 1210 is increased, and the storage capacitance of the second sub-pixel 1220 is increased. Therefore, the storage capacitance formed by the original first electrode trunk and the first electrode main body portion 12131 and the first electrode trunk and the second electrode main body portion 12231 can be removed, that is, the first electrode trunk is removed.

[0139] At this time, the storage capacitor of the first sub-pixel 1210 includes the storage capacitor formed by the second electrode trunk 121201 and the first electrode body 12131, the annular frame 121200 and the first electrode body 12131, and the first extension portion 12112b and the first extended electrode block 12121. The storage capacitor of the second sub-pixel 1220 includes the storage capacitor formed by the second electrode trunk 121201 and the second electrode body 12231, the annular frame 121200 and the second electrode body 12231, and the second extension portion 12212b and the second extended electrode block 12221, thereby reducing the provision of the first electrode trunk in the common electrode.

[0140] Since there is no obstruction by the first electrode trunk, the pixel aperture ratio of the first sub-pixel 1210 and the second sub-pixel 1220 is increased, the pixel penetration rate is improved, and the product competitiveness is enhanced.

[0141] In addition, since the first electrode trunk in the common electrode is reduced, the width of the first column trunk 121310 in the first electrode body portion 12131 and the second column trunk 122310 in the second electrode body portion 12231 can be reduced; for example, the width of the first column trunk 121310 and the second column trunk 122310 can be reduced from 8μm to 4μm, thereby improving pixel penetration and enhancing the competitiveness of the display panel 100.

[0142] It is worth mentioning that see Figure 11 and Figure 12 As shown, the first extension portion 12112b and the second extension portion 12212b are closer to the base substrate 110 than the first electrode main body portion 12131 and the second electrode main body portion 12231. Therefore, for the same overlapping area, the storage capacitor Cst formed by the first extension portion 12112b and the first extension electrode block 12121 is greater than the storage capacitor formed by the pixel electrode and the common electrode, and the storage capacitor Cst formed by the second extension portion 12212b and the second extension electrode block 12221 is greater than the storage capacitor formed by the pixel electrode and the common electrode.

[0143] In some embodiments of this application, see Figure 1 and Figure 8 As shown, the display panel 100 further includes a data line 170 extending in the column direction Y. The data line 170 can be connected to the first drain 12113 of the first transistor 1211, and the data line 170 can be connected to the second drain 12213 of the second transistor 1221, so as to write a data signal to the first source 12112 of the first transistor 1211 and write a data line 170 signal to the second source 12212 of the second transistor 1221.

[0144] Optionally, the data line 170 may be provided in the same layer as the first source 12112 and the first drain 12113 of the first transistor 1211 and the second source 12212 and the second drain 12213 of the second transistor 1221 .

[0145] The data line 170 may be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good electrical conductivity, but is not limited thereto and may also be made of other materials with good electrical conductivity.

[0146] In some embodiments of this application, see Figure 9 As shown, the first scan line 130 includes a first connection line 131 , a second connection line 132 and a third connection line 133 .

[0147] The first and third connection lines 131, 133 extend in the row direction X, parallel to each other. One end of the second connection line 132 connects to the first connection line 131, and the other end connects to the third connection line 133. The second connection line 132 extends in the column direction Y. The orthographic projection of the second connection line 132 on the substrate 110 is located between the orthographic projection of the data line 170 on the substrate 110 and the orthographic projection of the first electrode connection portion 12130 on the substrate 110. This shields the lateral parasitic capacitance Cpd formed between the data line 170 and the first electrode connection portion 12130, as well as the lateral parasitic capacitance Cpd formed between the first electrode line 12132 and the data line 170, thereby improving panel crosstalk. The end of the third connection line 133, remote from the second connection line 132, is connected to the first gate 12110 to transmit scan signals to the first gate 12110.

[0148] It can be understood that the data line 170 signal on the data line 170 is different from the data signal on the first electrode connecting portion 12130 and the first electrode line 12132, so that the second connecting line 132 can shield the lateral parasitic capacitance Cpd between the data line 170 and the first electrode connecting portion 12130 and the first electrode line 12132 and the data line 170, thereby improving the crosstalk problem.

[0149] Accordingly, see Figure 9 As shown, the second scan line 140 includes a fourth connection line 141 , a fifth connection line 142 and a sixth connection line 143 .

[0150] The fourth connection line 141 and the sixth connection line 143 are extended in the row direction X, and the fourth connection line 141 is parallel to the first connection line 131, and the sixth connection line 143 is parallel to the third connection line 133. One end of the fifth connection line 142 is connected to the fourth connection line 141, and the other end of the fifth connection line 142 is connected to the sixth connection line 143. The fifth connection line 142 is extended in the column direction Y and is parallel to the second connection line 132. The orthographic projection of the fifth connection line 142 on the base substrate 110 is located between the orthographic projection of the data line 170 on the base substrate 110 and the orthographic projection of the second electrode connection portion 12230 on the base substrate 110, so as to shield the lateral parasitic capacitance Cpd formed between the data line 170 and the second electrode connection portion 12230 and the lateral parasitic capacitance Cpd formed between the second electrode line 12232 and the data line 170, thereby improving the panel crosstalk problem. One end of the sixth connection line 143 away from the fifth connection line 142 is connected to the second gate 12210 to transmit the scan signal parasitic capacitance Cpd to the second gate 12210 to improve the crosstalk problem.

[0151] It can be understood that the data signal on the data line 170 is different from the data signal on the second electrode connecting portion 12230 and the second electrode line 12232, so that the fifth connecting line 142 can shield the lateral parasitic capacitance Cpd between the data line 170 and the second electrode connecting portion 12230 and the second electrode line 12232 and the data line 170, thereby improving the crosstalk problem.

[0152] In some embodiments of this application, see Figure 9 As shown, the first connection line 131 includes a first extension portion 1310, which extends toward the first extension line 12122. The orthographic projection of the first extension portion 1310 on the base substrate 110 is located between the orthographic projection of the first main frame 12120 on the base substrate 110 and the orthographic projection of the first extension electrode block 12121 on the base substrate 110. The orthographic projection of the first extension portion 1310 on the base substrate 110 and the orthographic projection of the first electrode line 12132 on the base substrate 110 have an overlapping area, thereby further increasing the storage capacitance Cst of the first sub-pixel 1210. In addition, the first extension portion 1310 can also be used to shield the vertical parasitic capacitance formed by the first extension portion 12112b and the first main frame 12120, thereby improving vertical crosstalk.

[0153] Accordingly, see Figure 9 As shown, the fourth connecting line 141 includes a second extension portion 1410, which is extended toward the second extension line 12222. The orthographic projection of the second extension portion 1410 on the base substrate 110 is located between the orthographic projection of the second main frame 12220 on the base substrate 110 and the orthographic projection of the second extension electrode block 12221 on the base substrate 110. The second extension portion 1410 is used to shield the vertical parasitic capacitance formed by the second extension portion 12212b and the second main frame 12220, thereby improving the vertical crosstalk.

[0154] In addition, the orthographic projections of the first connection line 131 and the sixth connection line 143 on the base substrate 110 and the orthographic projection of the second electrode line 12232 on the base substrate 110 have an overlapping area, so as to increase the storage capacitance of the second sub-pixel 1220 .

[0155] It is worth mentioning that the parasitic capacitance Cgs generated by the first gate 12110 and the first source 12112 in the first sub-pixel 1210 will be shielded by the fourth connecting line 141 and the sixth connecting line 143 in the second scanning line 140, thereby reducing the influence of the feedthrough voltage (Feedthrough△V), reducing the brightness difference between the sub-pixels, and thus better reducing the shaking head wrinkle problem.

[0156] In addition, the sub-pixels in the same column direction Y have the same color, that is, the first sub-pixels 1210 in the same column have the same color, and the second sub-pixels 1220 in the same column have the same color.

[0157] In some embodiments of this application, see Figure 1 As shown, the data line 170 includes a data main line 171, a first data branch line 172 and a second data branch line 173. The first data branch line 172 and the second data branch line 173 are both connected to the data main line 171. The first data branch line 172 and the second data branch line 173 are respectively connected to the first drain 12113 in the first sub-pixel 1210 and the second drain 12213 in the second sub-pixel 1220.

[0158] For example, the first data branch line 172 is connected to the drain of the Xth (X≥1) sub-pixel in the first pixel unit 120a, and the second data branch line 173 is connected to the drain of the Xth (X≥1) sub-pixel in the third pixel unit 120c.

[0159] For example, the first data branch line 172 is connected to the drain of the first sub-pixel in the first pixel unit 120a, and the second data branch line 173 is connected to the drain of the first sub-pixel in the third pixel unit 120c. The first data branch line 172 is connected to the drain of the second sub-pixel in the first pixel unit 120a, and the second data branch line 173 is connected to the drain of the second sub-pixel in the third pixel unit 120c, and so on.

[0160] In this way, the number of data lines 170 can be reduced, driving cost can be lowered, and production cost can be reduced.

[0161] Example 2

[0162] The difference between Example 2 of the present application and Example 1 is that in Example 2, the arrangement of the pixel units 120 in the nth row is the same as the arrangement of the pixel units 120 in the n+1th row, the arrangement of the pixel units 120 in the n+2th row is the same as the arrangement of the pixel units 120 in the n+3th row, and the arrangement of the pixel units 120 in the n+2th row is different from the arrangement of the pixel units 120 in the n+1th row; wherein n=1+4N, N is a natural number greater than or equal to 0.

[0163] For example, the arrangement of the first pixel units 120a in the first row and the arrangement of the first pixel units 120a in the second row can be a red second sub-pixel 1220, a green second sub-pixel 1220, and a blue first sub-pixel 1210; the arrangement of the first pixel units 120a in the third row and the arrangement of the first pixel units 120a in the fourth row can be a red first sub-pixel 1210, a green first sub-pixel 1210, and a blue second sub-pixel 1220.

[0164] The arrangement of the second pixel units 120b in the first row and the arrangement of the second pixel units 120b in the second row can be red first sub-pixel 1210, green second sub-pixel 1220, and blue second sub-pixel 1220; the arrangement of the second pixel units 120b in the third row and the arrangement of the second pixel units 120b in the fourth row can be red second sub-pixel 1220, green first sub-pixel 1210, and blue first sub-pixel 1210.

[0165] The arrangement of the third pixel units 120c in the first row and the arrangement of the third pixel units 120c in the second row can be a red first sub-pixel 1210, a green first sub-pixel 1210, and a blue second sub-pixel 1220. The arrangement of the third pixel units 120c in the third row and the arrangement of the third pixel units 120c in the fourth row can be a red second sub-pixel 1220, a green second sub-pixel 1220, and a blue first sub-pixel 1210.

[0166] The arrangement of the fourth pixel units 120d in the first row and the arrangement of the fourth pixel units 120d in the second row can be a red second sub-pixel 1220, a green first sub-pixel 1210, and a blue first sub-pixel 1210. The arrangement of the fourth pixel units 120d in the third row and the arrangement of the fourth pixel units 120d in the fourth row can be a red first sub-pixel 1210, a green second sub-pixel 1220, and a blue second sub-pixel 1220.

[0167] That is, the arrangement of the first sub-pixel 1210 and the second sub-pixel 1220 of the main pixel unit M in the first row is the same as the arrangement of the first sub-pixel 1210 and the second sub-pixel 1220 of the main pixel unit M in the second row.

[0168] By arranging the first sub-pixel 1210 and the second sub-pixel 1220 of the main pixel unit M in the first row in the same manner as the first sub-pixel 1210 and the second sub-pixel 1220 in the main pixel unit M in the second row, the scan lines can be scanned in sequence (G1→G2→G3→G4...→Gm), that is, a conventional progressive scan mode; the scan lines can also be scanned in an interlaced (DLG mode), scanning two rows of sub-pixels at a time, and then copying the pixel data of the two adjacent rows, so that the refresh rate can be doubled, for example, scanning the first scan line 130 /

[0169] The first scan line 130 in the second row is scanned, and then the second scan line 140 in the first row / the second scan line 140 in the second row are scanned (G1 / G3→G2 / G4...→Gm / Gm+2).

[0170] In addition, this method can also weaken the macro brightness difference caused by fully turning on and off the sub-pixels in the pixel unit 120 in the display panel 100, thereby improving the shaking head phenomenon and enhancing the display effect of the display panel 100.

[0171] Example 3

[0172] The difference between the third embodiment of the present application and the first embodiment is that the first pixel electrode 1213 further includes a first electrode strip 12133 , and the second pixel electrode 1223 further includes a second electrode strip 12233 .

[0173] Figure 14 A schematic structural diagram of a display panel is shown. Figure 15 A schematic structural diagram of the present application is shown in which the first pixel electrode is provided with a first electrode strip and the second pixel electrode is provided with a second electrode strip.

[0174] In some embodiments of this application, see Figure 14 and Figure 15 As shown, the length of the first electrode line 12132 in the column direction Y is smaller than the length of the second electrode line 12232 in the column direction Y.

[0175] See also Figure 14 and Figure 15 As shown, the first electrode strip 12133 is arranged on a side of the first electrode body 12131 away from the first electrode line 12132, and extends in the direction from the second scanning line 140 to the first scanning line 130, that is, the first electrode strip 12133 extends upward, and the first electrode strip 12133 and the first electrode line 12132 are located on the same column.

[0176] Accordingly, see Figure 14 and Figure 15 As shown, the second electrode strip 12233 is arranged on a side of the second electrode body 12231 away from the second electrode line 12232, and extends in the direction from the second scanning line 140 to the first scanning line 130, that is, the second electrode strip 12233 extends upward, and the second electrode strip 12233 and the second electrode line 12232 are located on the same column.

[0177] Among them, see Figure 14 and Figure 15 As shown, the length of the first electrode strip 12133 is greater than the length of the second electrode strip 12233, and the sum of the lengths of the first electrode strip 12133 and the first electrode line 12132 in the column direction Y is equal to the sum of the lengths of the second electrode strip 12233 and the second electrode line 12232 in the column direction Y.

[0178] It is worth mentioning that the first electrode strips 12133 , the first electrode lines 12132 , the second electrode strips 12233 , and the second electrode lines 12232 have the same width.

[0179] By ensuring that the sum of the lengths of the first electrode strips 12133 and the first electrode lines 12132 in the column direction Y is equal to the sum of the lengths of the second electrode strips 12233 and the second electrode lines 12232 in the column direction Y, each data line 170 can be equally affected by the parasitic capacitance generated by adjacent pixel electrodes, thereby improving vertical stripes and crosstalk in the panel and enhancing the quality of the display panel 100.

[0180] Example 4

[0181] The difference between the fourth embodiment of the present application and the first to third embodiments is that the storage capacitor of the first sub-pixel 1210 and the storage capacitor of the second sub-pixel 1220 are further increased.

[0182] Figure 16 A schematic structural diagram showing that the first / second source provided by an embodiment of the present application also includes a first / second overlapping portion. Figure 17 A schematic structural diagram of the first / second source and the first / second drain provided in an embodiment of the present application is shown. Figure 18 A schematic structural diagram showing the first / second pixel electrodes provided in an embodiment of the present application further including a fifth / sixth electrode block is shown.

[0183] In some embodiments of this application, see Figures 16 to 18 As shown, the first source electrode 12112 further includes a first overlapping portion 12112c, which is connected to the first extension portion 12112b. The first pixel electrode 1213 further includes a fifth electrode block 12134, which is connected to the first electrode connecting portion 12130. The orthographic projection of the fifth electrode block 12134 on the base substrate 110 overlaps with the orthographic projection of the first overlapping portion 12112c on the base substrate 110. The fifth electrode block 12134 is connected to the first overlapping portion 12112c through a first via 150 to receive the data signal from the first source electrode 12112.

[0184] The orthographic projection of the fifth electrode block 12134 on the base substrate 110 overlaps with the orthographic projection of the first extension line 12122 on the base substrate 110 , so that the fifth electrode block 12134 and the first extension line 12122 form a storage capacitor to further enhance the storage capacitance of the first sub-pixel 1210 .

[0185] See also Figure 16As shown, since the storage capacitor formed by the fifth electrode block 12134 and the first extension line 12122 further increases the storage capacitance in the first sub-pixel 1210, the second electrode trunk 121201 in the first main frame 12120 can be cancelled and the width of the first row trunk 121311 can be reduced to further increase the pixel aperture ratio and the pixel penetration rate, thereby improving the market competitiveness of the display panel 100.

[0186] Accordingly, see Figures 16 to 18 As shown, the second source electrode 12212 further includes a second overlapping portion 12212c, which is connected to the second extension portion 12212b. The second pixel electrode 1223 further includes a sixth electrode block 12234, which is connected to the second electrode connecting portion 12230. The orthographic projection of the sixth electrode block 12234 on the base substrate 110 overlaps with the orthographic projection of the second overlapping portion 12212c on the base substrate 110. The sixth electrode block 12234 is connected to the second overlapping portion 12212c through a second via 160 to receive the data signal from the second source electrode 12212.

[0187] The orthographic projection of the sixth electrode block 12234 on the base substrate 110 overlaps with the orthographic projection of the second extension line 12222 on the base substrate 110 , so that the sixth electrode block 12234 and the second extension line 12222 form a storage capacitor to further increase the storage capacitance of the second sub-pixel 1220 .

[0188] Since the storage capacitor formed by the sixth electrode block 12234 and the second extension line 12222 further increases the storage capacitance in the second sub-pixel 1220, the second electrode trunk 121201 in the second main frame 12220 can be cancelled and the width of the second row trunk 122311 can be reduced to further increase the pixel aperture ratio and pixel penetration rate, thereby improving the market competitiveness of the display panel 100.

[0189] Optionally, the width of the first row of stems 121311 and the second row of stems 122311 is reduced from 8 μm to 4 μm.

[0190] It is worth mentioning that arranging the first via 150 and the second via 160 at the fifth electrode block 12134 and the sixth electrode block 12234 can make the vias further away from the pixel electrodes, thereby reducing the impact of the vias on the pixel electrodes in the display area and ensuring the display effect.

[0191] Example 5

[0192] The difference between the fifth embodiment of the present application and the first embodiment is that the first extension line 12122 and the first extension electrode block 12121 of the first common electrode 1212 and the second extension line 12222 and the second extension electrode block 12221 of the second common electrode 1222 are eliminated, and the closed openings are provided on both the first scan line 130 and the second scan line 140.

[0193] Figure 19 It shows a structural schematic diagram of the first / second openings formed on the first / second scanning lines of the present application. Figure 20 A schematic diagram of the structure of the first / second electrode connecting portion of the present application is shown, in which the first / second electrode connecting portion is located in the first / second opening. Figure 21 A schematic diagram of the structure in which the first / second electrode connecting portion is located in the first / second opening in the second embodiment of the present invention is shown.

[0194] In some embodiments of this application, see Figure 19 As shown, a first opening 134 is defined on the first scan line 130 , and a second opening 144 is defined on the second scan line 140 .

[0195] Among them, see Figure 19 As shown, the first extension portion 1310 on the first connecting line 131 can continue to extend toward the side of the first gate 12110 and be connected to the first gate 12110, then the first opening 134 can be formed by the first gate 12110, the first connecting line 131, the second connecting line 132 and the third connecting line 133; the second extension portion 1410 on the second connecting line 132 can continue to extend toward the side of the second gate 12210 and be connected to the second gate 12210, then the second opening 144 can be formed by the second gate 12210, the fourth connecting line 141, the fifth connecting line 142 and the sixth connecting line 143.

[0196] The first opening 134 corresponds to the first sub-pixel 1210 , and the second opening 144 corresponds to the second sub-pixel 1220 .

[0197] See also Figure 20 or Figure 21As shown, the orthographic projection of the first electrode connection portion 12130 on the base substrate 110 is located within the orthographic projection of the first opening 134 on the base substrate 110. The orthographic projection of the second electrode connection portion 12230 on the base substrate 110 is located within the orthographic projection of the second opening 144 on the base substrate 110. In this way, when an offset occurs during the preparation of the pixel electrode, when the electrode connection portion of the pixel electrode offsets up, down, left, or right, the parasitic capacitance generated between the electrode connection portion of the pixel electrode and the scan line is a constant value, which can effectively improve the parasitic capacitance difference between the electrode connection portion of the pixel electrode and the scan line between different sub-pixels due to process reasons, and can also improve the quality difference between the same encoding chips of the display panel 100, thereby effectively improving the quality and product yield of the display panel 100, and improving product efficiency and competitiveness.

[0198] It can be understood that the parasitic capacitance generated by the first electrode connection portion 12130 and the first scan line 130 in the first opening 134 is the same as the parasitic capacitance generated by the second electrode connection portion 12230 and the second scan line 140 in the second opening 144, so as to ensure that the parasitic capacitance between different sub-pixels is the same, thereby ensuring the quality and product yield of the display panel 100.

[0199] In addition, see Figure 20 or Figure 21 As shown, the orthographic projection of the first / second electrode connecting portion 12230 on the base substrate 110 is located at the center of the orthographic projection of the first / second opening 144 on the base substrate 110. In other words, the first / second electrode connecting portion 12230 is centered to ensure that the parasitic capacitance between the first / second electrode connecting portion 12230 and the first / second scan line 140 does not change due to process factors. This can effectively reduce the parasitic capacitance differences between different sub-pixels, thereby improving the quality and product yield of the display panel 100.

[0200] Example 6

[0201] See also Figures 1 to 6 As shown, embodiment 6 of the present application provides a display device 10, which includes a flexible circuit board 200, a chip-on-film, and the display panel 100 provided by embodiments 1 to 5. The display panel 100 can be electrically connected to the flexible circuit board 200 through the chip-on-film.

[0202] According to the embodiments of the present application, the specific type of the display device 10 is not particularly limited, and any type of display device 10 commonly used in the field can be used, such as liquid crystal displays, mobile phones, laptop computers and other mobile devices, wearable devices such as watches, VR devices, etc. Those skilled in the art can make corresponding choices based on the specific purpose of the display device, which will not be repeated here.

[0203] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0204] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A display panel comprising a base substrate and pixel units formed on the base substrate, wherein a plurality of the pixel units are arranged in an array in row and column directions, characterized in that: The display panel further includes a first scan line and a second scan line provided between two adjacent rows of pixel units, wherein the first scan line and the second scan line are spaced apart from each other and both extend in the row direction; The pixel unit includes three sub-pixels, one of the three sub-pixels is a first sub-pixel, and the other two of the three sub-pixels are second sub-pixels; or one of the three sub-pixels is a second sub-pixel, and the other two of the three sub-pixels are first sub-pixels; The first sub-pixel and the second sub-pixel each include a transistor, each of the transistors includes a gate, the gate in the first sub-pixel is connected to the first scan line, and the gate in the second sub-pixel is connected to the second scan line; The first sub-pixel further includes a first pixel electrode, the first pixel electrode including a first electrode body portion, a first electrode connecting portion, and a first electrode line for connecting the first electrode body portion and the first electrode connecting portion; the second sub-pixel further includes a second pixel electrode, the second pixel electrode including a second electrode body portion, a second electrode connecting portion, and a second electrode line for connecting the second electrode body portion and the second electrode connecting portion; A plurality of closed first openings are provided on the first scanning line, the first openings corresponding to the first sub-pixels one by one, and the orthographic projections of the first electrode connecting portions on the base substrate are located at the centers of the orthographic projections of the first openings on the base substrate; A plurality of closed second openings are provided on the second scanning line, the second openings corresponding to the second sub-pixels one-to-one, and the orthographic projection of the second electrode connecting portion on the base substrate is located at the center of the orthographic projection of the second opening on the base substrate; The length of the second electrode line in the column direction is greater than the length of the first electrode line in the column direction; The first pixel electrode further includes a first electrode strip, the first electrode strip being provided on a side of the first electrode body away from the first electrode line and extending in a direction away from the first electrode connecting portion, and the first electrode strip and the first electrode line being located in the same column; The second pixel electrode further includes a second electrode strip, the second electrode strip being provided on a side of the second electrode body away from the second electrode line and extending in a direction away from the second electrode connecting portion, and the second electrode strip and the second electrode line being located in the same column; The sum of the lengths of the first electrode strips and the first electrode lines in the column direction is equal to the sum of the lengths of the second electrode strips and the second electrode lines in the column direction.

2. The display panel according to claim 1, wherein: The pixel units in adjacent rows are arranged in the same manner.

3. The display panel according to claim 1, wherein The arrangement of the pixel units in the nth row is the same as the arrangement of the pixel units in the n+1th row, the arrangement of the pixel units in the n+2th row is the same as the arrangement of the pixel units in the n+3th row, and the arrangement of the pixel units in the n+2th row is different from the arrangement of the pixel units in the n+1th row; Wherein, n=1+4N, N is a natural number greater than or equal to 0.

4. The display panel according to claim 2 or 3, wherein: The transistor further includes a semiconductor layer and a source electrode and a drain electrode respectively connected to opposite ends of the semiconductor layer, wherein the orthographic projection of the semiconductor layer on the substrate is located within the orthographic projection of the gate electrode on the substrate; The source electrodes of the first sub-pixel and the second sub-pixel each include a protrusion and an extension portion connected to each other, the protrusion pointing to the drain, an orthographic projection of the protrusion on the substrate overlapping an orthographic projection of the semiconductor layer on the substrate, and the extension portion being provided on a side of the protrusion away from the drain; The direction from the source electrode to the drain electrode in the first sub-pixel is the same as the direction from the source electrode to the drain electrode in the second sub-pixel.

5. The display panel according to claim 4, wherein: The orthographic projection of the first electrode connecting portion on the base substrate and the orthographic projection of the extension portion of the source electrode in the first sub-pixel on the base substrate have at least an overlapping area, and the first electrode connecting portion is electrically connected to the extension portion in the first sub-pixel through a first via hole; The orthographic projection of the second electrode connecting portion on the base substrate and the orthographic projection of the extension portion of the source electrode in the second sub-pixel on the base substrate have at least an overlapping area, and the second electrode connecting portion is electrically connected to the extension portion in the second sub-pixel through a second via hole.

6. The display panel according to claim 5, wherein: The first sub-pixel and the second sub-pixel each include a common electrode, the common electrode including a main frame, an extended electrode block, and an extension line connecting the main frame and the extended electrode block. The common electrodes between adjacent sub-pixels are connected via the main frame. The orthographic projection of the extended electrode block on the base substrate and the orthographic projection of the extension portion on the base substrate have at least an overlapping area. The extended electrode block of the first sub-pixel and the extended electrode block of the second sub-pixel are respectively arranged on opposite sides of the main frame, the extension line of the first sub-pixel is extended in the direction from the first scanning line to the second scanning line, and the extension line of the second sub-pixel is extended in the direction from the second scanning line to the first scanning line.

7. The display panel according to claim 5, wherein: The display panel further includes a data line extending in the column direction, wherein the data line is connected to the drain electrode; The first scan line includes a first connection line, a second connection line, and a third connection line, the first connection line and the third connection line are extended in the row direction, and the first connection line and the third connection line are parallel to each other, one end of the second connection line is connected to the first connection line, and the other end of the second connection line is connected to the third connection line, the second connection line is extended in the column direction, the orthographic projection of the second connection line on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the first electrode connection portion on the base substrate, and the end of the third connection line away from the second connection line is connected to the gate of the first sub-pixel; The second scan line includes a fourth connection line, a fifth connection line and a sixth connection line, the fourth connection line and the sixth connection line are extended in the row direction, and the fourth connection line is parallel to the first connection line, the sixth connection line is parallel to the third connection line, one end of the fifth connection line is connected to the fourth connection line, and the other end of the fifth connection line is connected to the sixth connection line, the fifth connection line is extended in the column direction and is parallel to the second connection line, the orthographic projection of the fifth connection line on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the second electrode connection portion on the base substrate, and the end of the sixth connection line away from the fifth connection line is connected to the gate of the second sub-pixel.

8. A display device, characterized in that: include: Flexible circuit boards; A chip-on-film connected to the flexible circuit board; The display panel according to any one of claims 1 to 7, wherein the display panel is electrically connected to the flexible circuit board via a chip-on-film.

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