Apparatus and method for monitored refresh management operations

Abstract

The invention relates to devices and methods for monitored refresh management operations. The controller performs an access operation on a word line located in a portion of a memory array in the memory device. The controller counts accesses part by part (e.g., bank by bank, sub-bank by sub-bank, etc.). The memory counts accesses word line by word line. The memory sets a refresh management (RFM) flag for a portion based on the count associated with the word lines in the portion. The controller checks the RFM flag of a portion based on the access count of the portion. The controller issues an RFM command if the RFM flag is set after checking the RFM flag.

Description

Technical Field

[0001] The present disclosure relates to apparatus and methods for monitored refresh management operations. Background Art

[0002] Information may be stored on memory cells of a memory device. Memory cells may be organized at the intersection of word lines (rows) and bit lines (columns). Information in a memory cell may decay over time. For example, information may be stored as a charge on a capacitor, which may decay over time. A memory device may perform a refresh operation to restore information and prevent information loss.

[0003] Certain access patterns may cause an increased rate of information decay in nearby memory cells (e.g., memory cells along nearby word lines). The memory device may use various schemes to identify these access patterns so that additional targeted refresh operations may be performed. The controller may signal the memory to perform refresh operations, some of which may be sequential operations for refreshing memory cells that decay at an expected rate, and some of which may be targeted refresh operations. However, refresh operations may take time that would otherwise be used for other operations and may use power. It may be desirable to ensure that the controller does not excessively issue refresh commands. Summary of the invention

[0004] In one aspect, the present disclosure provides an apparatus comprising: a memory array including: a first portion including a first plurality of word lines; a second portion including a second plurality of word lines; a mode register including a first refresh management (RFM) flag associated with the first portion and a second RFM flag associated with the second portion; a first refresh control circuit configured to set the first RFM flag based on a first plurality of count values, each count value being associated with one of the first plurality of word lines; and a second refresh control circuit configured to set the second RFM flag based on a second plurality of count values, each count value being associated with one of the second plurality of word lines, wherein the first refresh control circuit is configured to set the first RFM flag if the first aggressor queue includes at least one address, and wherein the second refresh control circuit is configured to set the second RFM flag if the second aggressor queue includes at least one address.

[0005] On the other hand, the present disclosure further provides a system comprising: a memory comprising: a memory array comprising a plurality of parts, each of the plurality of parts comprising a corresponding plurality of word lines, each word line being associated with a corresponding one of a plurality of count values; a mode register comprising a plurality of refresh management flags, each refresh management flag being associated with one of the plurality of parts; and a plurality of refresh control circuits configured to set or unset the plurality of RFM flags based on the plurality of count values ​​associated with the one of the plurality of parts associated with the RFM flag; and a controller configured to count the number of access operations of each of the plurality of parts, check the associated one of the plurality of RFM flags based on the count value, and provide an RFM command to the memory if the checked associated one of the plurality of RFM flags is set.

[0006] On the other hand, the present disclosure further provides a method, which includes: performing an access operation on a selected word line in a portion of a memory array of a memory with a controller; changing a first count value in the memory in response to performing the access operation on the selected word line, wherein the first count value is associated with the selected word line; if the first count value crosses a first threshold, setting a refresh management (RFM) flag in the memory; changing a second count value in the controller in response to performing the access operation on the portion, wherein the second count value is associated with the portion; if the second count value has crossed a second threshold, checking the state of the RFM flag; and if the RFM flag is set, issuing an RFM command to the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a memory system according to some embodiments of the present disclosure.

[0008] Figure 2 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure.

[0009] Figure 3 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure.

[0010] Figure 4 is a block diagram of a controller according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The following description of certain embodiments is merely exemplary in nature and is by no means intended to limit the scope of the present disclosure or its application or use. In the following detailed description of the embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof, and the accompanying drawings are shown by illustrative specific embodiments in which the described system and method can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the purpose of clarity, certain features will not be discussed in detail when they are obvious to those skilled in the art, so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0013] Information in a memory array may be accessed through one or more access operations, such as read or write operations. During an example access operation, a word line may be activated based on a row address, and then information of selected memory cells along the active word line may be read or written based on which bit lines are accessed, which may be based on a column address. The memory array may be refreshed row by row (e.g., as part of an auto-refresh and / or self-refresh mode), where the memory cells along each row are periodically refreshed. Such refresh operations may be referred to as sequential refresh operations or normal refresh operations, as the memory may use some sequential logic (e.g., a counter) to generate refresh addresses. The speed at which a row is refreshed (e.g., the maximum time that any given row will experience between refreshes) may be determined based on an expected rate of information decay, and may be adjusted based on various conditions of the memory (e.g., temperature).

[0014] Various access patterns to a row (aggressor row) can result in an increased rate of information decay in nearby memory cells (e.g., along a victim row). For example, "row hammering" can involve repeated accesses to an aggressor row, which can increase the decay rate of neighboring rows (and / or rows further away). Therefore, it can be important to track the number of accesses to each row to determine if it is an aggressor, so that the victim row can be identified and refreshed as part of a targeted refresh operation. For example, each word line can have an associated count value that is used to determine how many times the word line has been accessed.

[0015] The memory device may monitor accesses to a word line to determine if it is an aggressor (e.g., whether the number of accesses crosses a threshold). Identified aggressors may be stored in an aggressor queue, and their victims refreshed as part of a targeted refresh operation. The memory may perform a targeted refresh operation in response to a refresh management (RFM) command issued by a controller. However, if there are no identified aggressor rows, this may be both time-consuming and power-consuming. To better manage time and power consumption, a monitored refresh management (MRFM) operation may be required.

[0016] The present disclosure relates to apparatus, systems and methods for MRFM operations. A memory device may be organized into multiple sections (e.g., memory banks, memory bank groups, sub-memory banks, etc.), each section including multiple word lines, each word line being associated with a count value. Each time a word line is accessed, its count value changes and is compared to an aggressor threshold. If at least one of the count values ​​in a section crosses the aggressor threshold, an RFM flag is set for the section. For example, the RFM flag may be set in a mode register of the memory. A controller uses its own logic to determine when to issue an RFM command to the section. For example, the controller may count the access operations performed on each section and determine that an RFM should be sent when the count value crosses the RFM threshold. When the controller decides to perform an RFM operation on a section, it checks the flag associated with the section. For example, the controller may check the flag by reading the mode register of the memory. If the flag is set, an RFM command is issued to the section. If the flag is not set, the RFM command is not sent. This may allow the controller to send an RFM command only when the memory indicates that the RFM command is useful. This in turn may allow for other advantages, such as simplifying the logic used by the controller to determine whether to check to see if an RFM command should be sent.

[0017] Figure 1 1 is a block diagram of a memory system according to some embodiments of the present disclosure. The memory 100 includes a memory device 150, and a controller 102 that operates the memory device. In some embodiments, the controller 102 and the memory may be integrated components, such as on a single chip. In some embodiments, the controller 102 and the memory 150 may be separate components, for example, the controller 102 may be a processor coupled to the memory 150 through a motherboard or other intermediate components.

[0018] The controller 102 includes an access logic circuit 104 that performs access operations, such as read and write operations, to store data on or retrieve data from the memory 150. The controller 102 also includes a refresh logic circuit 110 that sends a refresh command REF to the memory 150 to cause it to perform one or more refresh operations. The refresh logic circuit 110 includes an RFM logic circuit 112 that determines when and whether the controller should send an RFM command to the memory 150. The memory 150 includes a memory array 160 that is used to store information, such as data written to and read by the controller 102. A row decoder (XDEC) 152 of the memory 150 accesses a word line (WL) of the memory array 160 in response to a row address XADD and an activated ACT signal. The memory 150 includes a refresh control circuit 154 that generates refresh addresses and provides signals to cause the row decoder 152 to refresh one or more word lines as part of a refresh operation. The refresh control circuit 154 also manages setting RFM flags 158 in a mode register 156 of the memory 150. Each RFM flag 158 is associated with a corresponding portion 162 of the memory array 160.

[0019] The RFM logic circuit 112 of the controller 102 counts the access operations performed by the access logic 104 on each portion 162. For example, each portion 162(0) to 162(N-1) may have an associated count value RFM_Count0 to RFM_CountN-1. Based on the count, the refresh logic circuit 110 performs a mode register read (MRR) operation on the mode register 156 of the memory 150 to determine whether the flag associated with the portion is set. If the flag is set, the controller 102 issues an RFM command to the memory 150. If the flag is not set, the controller 102 skips issuing the RFM command. The refresh control circuit 152 sets each flag based on a word line count value, each word line count value being associated with a word line in a corresponding portion. For example, if one or more word lines in the first portion 162(0) have a count that exceeds an attack threshold, a first RFM flag RFM_Flag0 may be set. When the access count RFM_Count0 of the first portion crosses a threshold, the controller 102 may use an MRR operation to check the status of RFM_Flag0 and, if RFM_Flag0 is set, issue an RFM command to the first portion 162 ( 0 ).

[0020] Controller 102 includes access logic circuitry 104 that performs access operations on memory device 150. Examples of access operations include: read operations, in which data is read from a specified location in memory array 160; and write operations, in which data is written from controller 102 to a specified location in memory array 160. Access logic 104 may send various commands and signals as part of an access operation. For example, controller 102 may provide row addresses, column addresses, and bank addresses as well as read or write commands and row activation commands. Addresses and commands may be provided in a specific sequence with timing based on the specifications of memory 150. For simplicity, Figure 1 Only the row address XADD and the row activation ACT and precharge Pre commands are shown in FIG. The row decoder 152 of the memory 150 activates (opens) the word line (row) specified by XADD in the memory array 160 in response to the ACT command, and deactivates (closes) the row in response to Pre.

[0021] Memory array 160 is divided into portions 162. In different embodiments, portions 162 may represent different levels of organization of memory array 160. For example, in some embodiments, portions 162 may represent banks of memory array 160. Banks may be specified by bank addresses. In some embodiments, portions 160 may represent sub-banks of memory array 160. In other words, each bank may include multiple portions 162. In some embodiments, portions 162 may represent groups of banks, and each portion 162 may include multiple banks. Figure 1 In the example of , memory array 160 has been divided into N portions 162(0) through 162(N-1).

[0022] Each portion 162 of the memory array 160 includes a plurality of word lines. In some embodiments, each portion 162 may include the same number of word lines. In other embodiments, the number of word lines in each portion may be different. Figure 1 In the example of FIG. 1 , each portion 162 includes M word lines WL0 to WLM-1.

[0023] As part of the access operation, the controller 102 may provide address information specifying a portion and a word line within the portion. For example, if the portion represents a memory bank, the bank address may specify the portion, while the row address XADD may specify the word line. If the portion 162 represents a sub-bank, the portion may be specified by a bank address and a row address, while the row address identifies the word line. For example, a portion of a row address may indicate a sub-bank, while another portion indicates a word line within the sub-bank.

[0024] The controller 102 includes an RFM logic circuit 112 that stores access counts 114, each access count 114 being associated with one of the portions. In this example, there are N access counts, RFM_Count0 to RFM_CountN-1. When the access logic 104 accesses a word line, the RFM logic 112 updates the count value associated with the portion 162 that includes the word line. For example, if a word line is accessed in portion 0 162(0), the RFM logic circuit 112 will update the count value RFM_Count0. In some embodiments, the RFM logic 112 may increment the count value in response to an access in the associated portion. In some embodiments, a more complex update scheme may be used. For example, the count value may be a rolling accumulation activation (RAA) count that changes (e.g., increases) a certain amount in a first direction in response to an access operation, and changes (e.g., decreases) a different amount in a second direction in response to a refresh operation on the associated portion.

[0025] When a word line is accessed, the refresh control circuit 154 of the memory 150 changes the count value associated with the word line. For example, the memory 150 may include per-row activity tracking, where each word line includes a counter memory cell that stores a count value associated with the number of times the word line has been accessed. For example, when the row decoder 152 receives the row address XADD and the activation signal ACT, it may activate the word line and may read the count value out to the refresh control circuit 154. The refresh control circuit 154 updates the count value, and the updated count value is written back to the counter memory cell. For example, the refresh control circuit 154 may increment the count value.

[0026] The updated word line count value is compared to a threshold value, such as a hammer threshold or an attack threshold. If the updated word line count value exceeds the threshold, the row address XADD is added to the aggressor queue of the refresh control circuit 154, and the word line count value is reset. In addition, the refresh control circuit 154 may set the RFM flag associated with the portion containing the word line. For example, if the word line is in the first portion Portion0 162(0), the first RFM flag RFM_Flag0 may be set in the mode register 156. In this manner, each flag may be set if at least one word line in the portion has an associated word line count value that exceeds the attack threshold.

[0027] The RFM logic 112 determines when to check the state of the flag (e.g., when to check whether to invoke an RFM operation) based on the RFM count value 114. For example, when the RFM count value is updated, it can be compared to the RFM threshold. If the RFM count value has crossed the threshold, the RFM logic 110 can signal the controller 102 that the state of the associated RFM flag 158 in the mode register 156 of the memory should be checked. The controller 102 can check the state of the RFM flag 158 by performing a mode register read (MRR) operation. The one or more registers containing the RFM flag 158 can be readable even when an access operation is in progress. For example, the controller 102 can read the state of the RFM flag associated with the first memory bank while performing an access operation on the second memory bank.

[0028] In an example implementation, the RFM logic circuit 112 may increment the RFM count value each time a word line in the associated portion 162 is accessed. When the RFM count value 114 crosses a threshold, the RFM logic circuit 112 may cause the controller 102 to check the state of the associated RFM flag and then reset the RFM count value. In this manner, the RFM flag for a given portion may be checked every threshold number of accesses to the portion. In other example embodiments, other schemes for determining when to check the RFM flag may be used.

[0029] The refresh logic 110 sends a refresh command REF to the memory 150. In response to the refresh command REF, the refresh control circuit may perform one or more refresh operations. The refresh operation may be a normal refresh operation, a target refresh operation, or a combination thereof. In some embodiments, the memory 150 may only perform a normal refresh operation in response to the refresh command REF, and may only perform a target refresh command in response to the RFM command RFM.

[0030] In a normal refresh operation, the refresh control circuit 154 generates a refresh address based on the address sequence, and the row decoder 152 refreshes one or more word lines associated with the refresh address. In a target refresh operation, the refresh control circuit 154 generates a refresh address based on one of the addresses stored in the aggressor queue, and the row decoder 152 refreshes one or more word lines associated with the refresh address. When a refresh address is generated as part of a target refresh address, the address is removed from the queue. In some embodiments, there may be a separate queue for each portion 162 of the array 160. If a queue becomes empty, the RFM flag associated with that portion may be unset.

[0031] When the controller checks the RFM flag of a portion, if the flag is set, the controller 102 issues an RFM command to the portion. In response to the RFM command, the refresh control circuit performs a targeted refresh operation on the specified portion 162. In this way, the controller 102 can determine when to check whether an RFM command should be executed based on the number of accesses to the portion, and can send an RFM command only when the memory 150 indicates that one or more word lines within the portion are ready for a targeted refresh operation. In other words, the controller 102 can count accesses on a portion-by-portion basis, while the memory 150 can count accesses to individual word lines within each portion.

[0032] Figure 2 2 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 200 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. The device 200 may be controlled by a controller (e.g. Figure 1 The controller 102 of the present invention is operated. The controller may be any device (or collection of devices) that stores information on a memory. For example, the controller may be a processor. In some embodiments, the controller and the memory 200 may be packaged together on a single integrated circuit. In some embodiments, the controller and the memory 200 may be separate. In some embodiments, the controller may operate multiple memory devices 200.

[0033] The semiconductor device 200 includes a memory array 218 (eg, Figure 1 160). The memory array 218 is shown as including a plurality of memory banks. Figure 1 In the embodiment of the present invention, the memory array 218 is shown as including eight memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 218 of other embodiments. Each memory bank includes a plurality of word lines WL (rows), a plurality of bit lines BL (columns), and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. Each memory bank is associated with a value of a memory bank address BADD. In some embodiments, a memory bank may represent Figure 1 Section 162.

[0034] The selection of the word line WL is performed by the row decoder 208, and the selection of the bit line BL is performed by the column decoder 210. Figure 2In the embodiment of the present invention, the row decoder 208 includes a corresponding row decoder for each memory bank, and the column decoder 210 includes a corresponding column decoder for each memory bank. The bit line BL is coupled to a corresponding sense amplifier (SAMP). The read data from the bit line BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 220 through the complementary local data line (LIOT / B), the transfer gate (TG) and the complementary main data line (MIOT / B). Conversely, the write data output from the read / write amplifier 220 is transmitted to the sense amplifier SAMP through the complementary main data line MIOT / B, the transfer gate TG and the complementary local data line LIOT / B, and is written into the memory cell MC coupled to the bit line BL.

[0035] The semiconductor device 200 may employ a plurality of external terminals coupled to the controller. The external terminals include command and address (C / A) terminals coupled to the controller along a command and address bus to receive commands and addresses. Other external terminals include a clock terminal for receiving clock signals CK and / CK along a clock bus, a data terminal DQ for sending and receiving data along a data bus, and a power supply terminal for receiving power supply potentials such as VDD, VSS, VDDQ, and VSSQ.

[0036] The clock terminal is supplied by the controller with external clocks CK and / CK provided to the input circuit 212. The external clocks may be complementary. The input circuit 212 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 210 and the internal clock generator 214. The internal clock generator 214 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 222 to time the operation of the circuit included in the input / output circuit 222, for example, to the data receiver to time the reception of the write data.

[0037] The C / A terminal may be supplied with a memory address by the controller. The memory address supplied to the C / A terminal is transmitted to the address decoder 204 via the command / address input circuit 202. The address decoder 204 receives the address and supplies the decoded row address XADD to the row decoder 208, and supplies the decoded column address YADD to the column decoder 210. The address decoder 204 may also supply a decoded memory bank address BADD, which may indicate the memory bank of the memory array 218 containing the decoded row address XADD and the column address YADD. The C / A terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., a read command for performing a read operation and a write command for performing a write operation), and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and memory bank addresses BADD to indicate the memory cell(s) to be accessed.

[0038] The command may be provided as an internal command signal to the command decoder 206 via the command / address input circuit 202. The command decoder 206 includes circuitry for decoding the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 206 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0039] As part of an example read operation, the device 200 may receive a read command and a memory address indicating where the read command should be executed. In response to the read command, data is read from a memory cell of a bank specified by BADD at the intersection of a row specified by XADD and a column specified by YADD. The read command is received by the command decoder 206, which provides an internal command so that the data read from the memory array 218 is provided to the read / write amplifier 220. The read data is output from the data terminal DQ to the controller via the input / output circuit 222.

[0040] As part of an example write operation, the device 200 may receive a write command along with the data to be written to the array and a memory address indicating where the write operation should be performed. In response to the write command, the data is written to the memory cell at the intersection of the word line specified by XADD and the column specified by YADD to the memory bank specified by BADD. The write command is received by the command decoder 206, which provides an internal command so that the write data is received by the data receiver in the input / output circuit 222. The write clock may also be provided to the external clock terminal for timing the receipt of the write data by the data receiver of the input / output circuit 222. The write data is supplied to the read / write amplifier 120 via the input / output circuit 222, and is supplied by the read / write amplifier 120 to the memory array 218 to be written to the memory cell MC specified by the address.

[0041] The device 200 may also receive a command that causes it to perform a refresh operation. For example, the controller may issue a refresh command REF or a refresh management command RFM. In response to the REF command or RFM, the refresh control circuit 216 (e.g., Figure 1 154) may perform one or more refresh operations. As part of the refresh operation, refresh control circuit 216 issues a refresh address RXADD, and row decoder 208 may refresh one or more word lines based on the refresh address RXADD. The number and type of refresh operations performed may vary based on whether REF or RFM is received. In some embodiments, similar to row decoder 208 and column decoder 210, refresh control circuit 216 may repeat from bank to bank.

[0042] Refresh commands REF and RFM are supplied to refresh address control circuit 216. Refresh address control circuit 216 supplies one or more refresh addresses RXADD to row decoder 208, which refreshes one or more word lines WL identified by refresh row address RXADD. For example, in some embodiments, refresh control circuit 216 may perform a mix of normal (or sequential) refresh operations and target refresh operations in response to refresh command REF, and may perform a target refresh operation in response to RFM command RFM. In some embodiments, refresh control circuit 216 may perform a normal refresh operation in response to REF and a target refresh command in response to RFM.

[0043] The refresh control circuit 216 may perform a sequential refresh operation or a normal refresh operation by issuing one or more sequential refresh addresses as RXADD. The sequential refresh addresses may be generated based on an address sequence. For example, after issuing a sequential refresh address, a counter circuit may increment the address to generate the next address in the sequence (e.g., RXADD(i)=RXADD(i-1)+1). The refresh address control circuit 216 may cycle through the sequential address sequence at a rate determined by REF. In some embodiments, the sequential address sequence may include all addresses in the memory bank 218. In some embodiments, the controller may issue a signal REF at a frequency such that most or all addresses in the memory bank 218 are refreshed within a particular cycle (e.g., such that there is a maximum specified time between two consecutive sequential refreshes of a given word line), and the frequency may be based on an expected rate of information decay in the memory cell MC. In some embodiments, the rate at which the controller issues REF may be based in part on a refresh interval and a refresh interval multiplier read from the mode register 230. The refresh interval multiplier may be based on a condition of the memory 200, such as a temperature sensor ( Figure 2 The temperature read is not shown.

[0044] The refresh control circuit 216 may perform a target refresh operation (e.g., in response to an RFM). The refresh control circuit 216 identifies an address as a target of a target refresh operation. These addresses may generally be referred to as aggressors, although different embodiments may use different criteria to identify these addresses. The refresh control circuit 216 may include a register that stores identified aggressors. As part of the target refresh operation, one or more refresh addresses are generated based on the selected aggressors. For example, in some embodiments, the refresh address may represent a word line that is physically adjacent to a word line associated with an identified aggressor address (e.g., RXADD=XADD+ / -1). Other relationships may be used in other example embodiments. For example, a farther word line may be refreshed (e.g., RXADD=XADD+ / -2, + / -3, etc.).

[0045] The memory device 200 may use one or more systems to determine which address(es) are aggressors. For example, the device 200 may use per-row activity tracking, where each word line has an associated access count value. Figure 1In an example embodiment of , some of the memory cells of the array 118 may be set aside for use in tracking aggressor rows. The memory cells 126 set aside for this purpose may generally be referred to as counter memory cells 126. The counter memory cells may store count values ​​XCount, each count value XCount being associated with one of the word lines. For example, each count value XCount may be stored in a counter memory cell 126 along the word line associated with the count value. The count value XCount may be stored as a binary number, with each bit stored in a memory cell along the word line. To simplify the description, in Figure 2 Only a single example counter memory cell and bit line are shown in FIG. 2 , however, in other example embodiments, more counter memory cells 226 per word line may be used. The number of counter memory cells along each word line may be based on the number of bits of the count value XCount. In some embodiments, additional counter memory cells (e.g., greater in length than the number XCount) may be used, for example, to store error correction information for the count value XCount.

[0046] The counter memory cells 226 may be so called due to their purpose (storing count values), and in some embodiments they may be structurally similar or identical to other memory cells of the array. In some embodiments, the counter memory cells 226 may be grouped together (e.g., at the end of a word line). In other example embodiments, other distributions of the counter memory cells 226 along the word line may be used. In some embodiments, the counter memory cells 226 may not be directly accessible by an external device such as a controller (e.g., to prevent the count value from being overwritten). In other words, the bit lines associated with the counter memory cells 226 may not be accessed by normal column addresses.

[0047] The count value XCount may be used to determine whether the associated word line is an aggressor. For example, each time a word line is accessed, the count value XCount may be read out to the refresh control circuit, which may update the count, compare the updated count to a threshold, and write the updated count back to the counter memory unit 226. For example, the count may be updated by incrementing. If the updated count crosses the threshold, the row address XADD (and the count XCount) associated with the word line may be stored as an aggressor, and the count value may be updated again by resetting the count value to an initial value (e.g., 0). In some embodiments, the threshold may represent a maximum value for the count, and the count may cross the threshold by "rolling back" to the initial value (e.g., from 11111111 to 00000000).

[0048] The memory device 200 includes a mode register 230 (eg, Figure 1156), which includes a plurality of registers. The registers may store information about the memory 200, settings that control the operation of the memory 200, or a combination thereof. For example, the mode register 230 may include a plurality of RFM flags. The RFM flags may each be associated with a portion of the memory array 218. For example, in some embodiments, there may be an RFM flag for each bank of the memory 218. The refresh control circuit 216 may set and unset the RFM flag. For example, the refresh control circuit 216 may include an aggressor queue for each RFM flag (e.g., for each portion of the memory array). When the aggressor queue for a portion is non-empty (e.g., the count XCount of at least one word line in the portion has crossed the aggressor threshold and has not been refreshed), the refresh control circuit 216 sets the RFM flag in the mode register 230 associated with the portion. When the aggressor queue for a portion becomes empty (e.g., due to a target refresh operation), the refresh control circuit 216 unsets the RFM flag for the portion.

[0049] The RFM flag may be stored in a register of the mode register 230 that is readable while the memory device 200 is performing an access operation. For example, the memory device 200 may receive a mode register read (MRR) command that specifies one of the RFM flag registers. The memory 200 may provide the value of the specified register while still performing an access operation on the memory array 218. For example, an RFM flag associated with a first memory bank may be read while an access operation is performed on a second memory bank.

[0050] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 224. The internal voltage generator circuit 224 generates various internal potentials VPP, VARY, VPERI and the like based on the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 222. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 222 so that power supply noise generated by the input / output circuit 222 does not propagate to other circuit blocks.

[0051] Figure 3is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. Figure 3 It can be shown that a memory device 300 (eg, Figure 2 200). For example, the memory array 318 may implement Figure 2 The memory array 218, the row decoder 308 may implement Figure 2 The row decoder 208, the refresh control circuit 316 may implement Figure 2 Refresh control circuit 216, etc.

[0052] Specific internal components and signals of the refresh address control circuit 316 are shown to illustrate the operation of the refresh address control circuit 316. For example, the refresh control circuit 316 includes an aggressor address register or aggressor address queue 344 that stores identified aggressor addresses, a refresh address generator 350 that generates a refresh address RXADD, and an aggressor detector circuit 317 that determines whether the address XADD is the aggressor address HitXADD. The refresh control circuit 216 also includes a refresh state control circuit 360 that controls what type and how many refresh operations are performed in response to various commands such as REF and RFM.

[0053] The dashed lines around the refresh address control circuit 316, row decoder 308, and memory array 318 are shown to indicate that in certain embodiments, each component within the dashed lines may correspond to a specific bank of memory, and these components may be repeated for each of the banks of memory. In some embodiments, the components shown within the dashed lines may be associated with each of the banks of memory. Thus, there may be multiple refresh address control circuits 316, each with its own aggressor address in its own aggressor queue 344. For the sake of brevity, only the components of a single bank will be described. In some embodiments, one or more of the components within the dashed boxes may be individually (e.g., Figure 1 Instead of (or in addition to) repeating from bank to bank, the portion 162 of the memory bank may be repeated. For example, if the portion is a sub-memory bank, there may be an aggressor queue 344 for each sub-memory bank.

[0054] DRAM interface 340 may provide one or more signals to address refresh control circuit 316 and row decoder 308, which in turn (along with column decoders, not shown) may perform access operations on memory array 318. DRAM interface 340 represents various components of the memory that send, receive, and / or decode signals to / from a controller as part of an access operation. For example, DRAM interface 340 may represent command / address input circuitry (e.g., Figure 2 202), address decoder (for example, Figure 2 204) and a command decoder (e.g., Figure 2 206). During an example access operation, the DRAM interface 340 provides a row address XADD and an activation signal ACT. The DRAM interface 340 also provides, for example, a slave controller (eg, Figure 1 102) receives the refresh command REF and the refresh management command RFM.

[0055] The refresh state control circuit 360 performs one or more refresh operations in response to the commands REF and RFM. The refresh state control circuit 360 determines how many and what types of refresh operations to perform in response to one or the other of the commands. The refresh state control circuit generates an internal refresh signal IREF and a target refresh signal RHR. In some embodiments, a valid signal IREF indicates that a refresh operation should be performed, and whether the signal RHR is also valid determines the type of refresh operation. For example, if IREF is valid alone, a normal refresh operation can be performed. If both IREF and RHR are valid, a target refresh operation can be performed. Other modes of signal activation can be used in other example embodiments.

[0056] The refresh state control circuit 360 may execute multiple refresh "pumps" in response to each activation of the refresh signal REF. A refresh operation may be performed on each pump. For example, each time REF is received, the refresh state control circuit may provide several activations of IREF. In some embodiments, some pumps executed in response to REF may be normal refresh operations (e.g., IREF alone is valid), and some may be target refresh operations (e.g., IREF and RHR are valid). In some embodiments, only normal refresh operations may be performed in response to REF. The refresh state control circuit 360 may also execute multiple refresh pumps in response to RFM, however, all pumps provided in response to RFM may be target refresh operations. The number of pumps executed in response to REF and RFM may be the same or different.

[0057] As part of a normal refresh operation, the refresh address generator circuit 350 provides one or more refresh addresses RXADD generated by the sequential refresh address circuit 352. The sequential refresh address generator circuit may use logic for generating each new refresh address as part of a sequence. Each new sequential refresh address may be based on a previous sequential refresh address. In other words, sequential logic may be used to update the previous refresh address provided by the sequential address generator circuit 352 to generate the next refresh address to be provided by the sequential address generator circuit 352. For example, the sequential refresh address generator circuit 352 may include a counter circuit that updates the value of the previous sequential refresh address to generate a new sequential refresh address (e.g., RXADD(i)=RXADD(i-1)+1). In other example embodiments, other logic may be used to generate a sequence of sequential refresh addresses.

[0058] As part of the target refresh operation, the target refresh address generator circuit 354 of the refresh address generator 350 provides one or more target refresh addresses as the refresh address RXADD. The target refresh address generator circuit 354 of the refresh address generator 350 generates the target refresh address based on the identified aggressor address HitXADD stored in the aggressor queue 344. For example, the target refresh address generator 354 may generate two target refresh addresses based on the aggressor address HitXADD, the two target refresh addresses representing the word lines in the array 318 adjacent to HitXADD (e.g., RXADD=HitXADD+ / -1). In other example embodiments, other numbers of addresses per aggressor and other methods of generating refresh addresses based on aggressors may be used. Once all refresh addresses for a given aggressor HitXADD are generated, the address HitXADD may be removed from the aggressor queue 344.

[0059] In response to the refresh address RXADD (whether sequential or targeted) and the signals IREF and / or RHR, the row decoder 308 refreshes the memory cells along the word line indicated by the refresh address. In some embodiments, the normal refresh address may indicate a different number of word lines than the target refresh address. For example, the normal refresh address may be associated with more word lines than the target refresh address. In some embodiments, the sequential refresh address may be associated with multiple word lines, while the target refresh address is associated with a single word line.

[0060] Refresh control circuit 316 includes aggressor detector circuit 317 that determines whether the current address XADD should be stored as an aggressor address in aggressor queue 344. Various schemes may be used to determine whether an address is an aggressor. Figure 3 In the example embodiment shown, a counter memory cell 326 in the memory array 318 is used to track the access count associated with the word line. The aggressor detector circuit 317 includes a counter circuit 348 that updates the count value XCount of the accessed word line and a comparator circuit 346 that determines whether the address XADD is an aggressor based on the updated count value.

[0061] When a row of the memory array 318 is accessed, the values ​​of the counter memory cells 326 along the row are read to the counter circuit 348. The counter memory cells 326 may store bits of a binary number representing a count value. For example, if the number is a 16-bit number, 16 or more counter memory cells may store bits of the number. The counter 348 may determine the value of the access count for the row based on the value read from the counter memory cells 326. The counter 348 may be a count control circuit that may manage the value of the count stored in the counter memory cells 326 (e.g., by reading the original data in the counter memory cells 326 as a value, writing a new value to the counter memory cells 326, etc.). The counter circuit 348 may change the count value (e.g., by incrementing the count value) and provide the changed count value to the threshold comparator 346, which may determine whether the changed count value crosses a threshold (e.g., whether the value is greater than a threshold or greater than or equal to a threshold). If the value does not cross the threshold (e.g., if the value is less than the threshold or less than or equal to the threshold), the counter circuit 348 may write the changed count back to the counter memory unit 326. If the value does cross the threshold, the current address XADD may be determined to be the aggressor address HitXADD, and the threshold comparator circuit 346 provides the aggressor detected signal Agg to the aggressor queue 344. In response to the signal Agg, the aggressor address register 344 stores the row address XADD. Also in response to the signal Agg, the counter circuit 348 may change the count value XCount. In some embodiments, the count value may be reset (e.g., to an initial value) or changed in the opposite direction to the direction in which it changes in response to an access (e.g., if the count increases for an access, the count may be decreased in response to the signal Agg).

[0062] In some embodiments, the change of the count value may be inherent, and the comparator circuit 346 may be omitted. For example, the threshold may be set to the maximum value of the count value XCount, and when XCount reaches the threshold and increments again, the count may roll back to the initial value (e.g., 0). When the counter circuit 348 rolls the value to the initial value, the counter circuit 348 provides the aggressor detected signal Agg.

[0063] In some embodiments, aggressor detector circuit 317 may be located in a region of the memory device that is closer to array 318 than the rest of refresh control circuit 316. For example, aggressor detector 317 may be in a bank logic region associated with array 318, while the rest of the components may be in a more central region.

[0064] In some embodiments, when the aggressor queue 344 includes at least one address, the refresh control circuit 316 may set an associated RFM flag in the mode register 362. For example, when an address is added to the aggressor queue 344, a signal may be sent to set the associated RFM flag. When the aggressor queue 344 becomes empty, the associated RFM flag may be unset. For example, if a targeted refresh operation is performed and the last aggressor address in the queue 344 is removed, a signal may be sent to unset the associated RFM flag. In some embodiments, each of the RFM flags may be a single bit, and the flag may be set when the bit is in a first state (e.g., logic high), and may be unset when the bit is in a second state (e.g., logic low).

[0065] Figure 4 is a block diagram of a controller according to some embodiments of the present disclosure. In some embodiments, the controller 400 may implement Figure 1 Controller 102. Controller 400 operates the memory, e.g. Figure 1 Memory 150, Figure 2 Memory 200 and / or Figure 3 The controller 400 operates the memory by sending and receiving various signals (such as commands, addresses and / or data) along various buses. For clarity, Figure 4 Only certain signals are shown, and other signals and their buses have been omitted.

[0066] The controller 400 includes an access logic circuit 402 (eg, Figure 1 104), access logic circuit 402 controls when access commands are sent to the memory. Access logic 402 can perform access operations by providing commands and addresses along the C / A bus to the C / A terminal of the memory. For example, access logic 402 can provide row, column, and bank addresses (XADD, YADD, and BADD, respectively) and commands (e.g., read or write commands R / W) along the C / A bus. Access logic 402 can also provide Figure 4 Other signals not shown, such as row activation and precharge commands ACT / Pre.

[0067] The controller 400 also includes a refresh logic circuit 404 (eg, Figure 1110), the refresh logic circuit 404 determines when and what type of refresh command to send to the memory. For example, the refresh logic circuit 404 can provide a refresh command REF and a refresh management command RFM. The refresh logic circuit 404 includes a refresh timing circuit 406 that provides a refresh signal REF. The refresh signal can be provided with periodic timing. For example, the refresh timing circuit 406 can count the activations (e.g., rising edges and / or falling edges) of the clock signal and provide the refresh signal REF at least once every N activations of the clock signal.

[0068] In some embodiments, the time between refresh commands REF may be based on the properties of the memory. For example, a mode register (e.g., Figure 1 156 Figure 2 230 and / or Figure 3 362) may include a register specifying a default refresh interval and a register specifying a refresh interval multiplier. The refresh timing circuit 406 may multiply the default refresh interval by the refresh interval multiplier to determine the refresh interval, and provide a refresh command REF at least once in each refresh interval. The controller 400 may periodically check the value of the refresh interval multiplier, for example, by periodically performing a mode register read operation.

[0069] The refresh logic circuit 404 also includes an RFM logic circuit 410 (eg, Figure 1 112), the RFM logic circuit 410 determines when to provide a refresh management command RFM. The RFM logic circuit 410 tracks accesses to different portions of the memory and determines when to check the RFM flag associated with the portion based on the corresponding access. If the flag is set, the RFM command is sent to the portion. Figure 4 In the example embodiment of , the access counts, RFM flags, and RFM commands are on a bank-by-bank level, however, in other example embodiments, other subdivisions of the memory array (e.g., sub-banks, groups of banks, all banks) are possible.

[0070] The RFM logic circuit 410 includes a plurality of RFM counters 412 (e.g., Figure 1114), each RFM counter 412 is associated with a portion of the memory array, in this case a bank of the memory array. When the access logic 402 accesses a bank, the associated counter 412 is updated. For example, the RFM logic circuit 410 may receive a bank address BADD to determine which bank to access. In an example embodiment, when a bank is accessed, the associated counter may be incremented. The comparator circuit 414 compares the updated count value with a threshold. If the updated count value has crossed the threshold, the comparator 414 may signal the RFM flag check logic 416 to check the state of the associated flag in the memory. In response to the flag being checked, the RFM logic circuit 410 may reset the count value of the portion.

[0071] In another example embodiment, the counter may be a rolling accumulation activation RAA counter. The counter may change (e.g., increase) the count value in a first direction by a first amount in response to a bank address BADD, and may change (e.g., decrease) the count value in a second direction by a second amount in response to a refresh command REF issued to the bank. Other actions may also change the counter in the first or second direction. When the comparator 414 determines that the count value has crossed the threshold, the count value may change in the second direction (e.g., by a second amount or by a different amount), and then signal the RFM flag check logic 416 to check the state of the associated flag.

[0072] The comparator circuit 414 notifies the RFM flag check logic circuit 416 to check the RFM flag of a specific portion of the memory (e.g., as specified by the comparator 414 based on which count value triggered the check). The RFM flag check logic 416 performs the check by performing an MRR operation on the mode register storing the RFM flag associated with the specified portion. In response to the MRR operation, the controller 400 receives the value of the specified RFM flag RFM_Flag. If RFM_Flag is set (e.g., at a logic high), the refresh logic circuit 404 issues an RFM command to the specified portion. If RFM_Flag is unset (e.g., at a logic low), the refresh logic circuit 404 does not issue an RFM command.

[0073] Figure 5 is a flow chart of a method according to some embodiments of the present disclosure. In some embodiments, method 500 may be performed by one or more of the devices or systems described herein. For example, in some embodiments, method 500 may be performed by Figure 1 A memory system 100, Figure 2 The memory device 200, Figure 3 The memory device 300 and / or Figure 4 The method 500 includes executing, by a controller (e.g., Figure 1102 and / or Figure 4 400) and the steps performed by the memory (e.g., Figure 1 150 Figure 2 200 and / or Figure 3 Blocks 510 to 530 may represent steps performed by a memory device, and blocks 540 to 560 may represent steps performed by a controller.

[0074] Method 500 may begin at block 510, which describes performing an access operation on a selected word line in a portion of a memory array in a memory device. For example, method 500 may include providing a row address and an access command (e.g., a read or write command) from a controller to a memory, and receiving the row address and the access command with the memory. Method 500 may include providing address information identifying the portion from the controller, and receiving the address information with the memory. For example, if the portion is a memory bank, method 500 may include providing a bank address identifying the portion. In another example, if the portion is a sub-bank, method 500 may include providing a bank address identifying the bank and providing a row address, a portion of which identifies a sub-bank within the bank.

[0075] Block 510 is followed by blocks 520 and 540. Blocks 520 and 540 may represent operations independently performed in the memory and the controller (respectively) in response to an access operation. The steps of blocks 520 to 530 may represent operations performed in response to the memory receiving an access command and performing an access operation, while the steps of blocks 540 to 560 may represent operations performed in response to the controller providing an access command to the memory.

[0076] Block 520 depicts changing a first count value (eg, XCount) associated with a word line in memory. In some embodiments, the first count value may be stored along the word line, such as in a counter memory cell (eg, Figure 2 226 and / or Figure 3 326). Method 500 may include reading a first count value from a word line in response to performing an access operation, changing the first count value, and writing the changed count value back to the word line. For example, the method may include incrementing the first count value in response to performing an access operation.

[0077] Block 520 is followed by block 530, which describes setting an RFM flag associated with the portion if the first count value crosses the first threshold. For example, method 500 may include comparing the changed first count value to the first threshold, and if the first count value is greater than or equal to (or greater than) the first threshold, setting the RFM flag. In some embodiments, method 500 may include rolling the first count value to an initial value and using it as the first count value that crosses the first threshold. In some embodiments, method 500 may include adding a row address associated with the word line to an aggressor queue if the first count value crosses the first threshold.

[0078] The method 500 may include setting the RFM flag if any one of the first plurality of count values, each associated with one of the plurality of word lines in the portion, crosses a first threshold. The method 500 may include unsetting the RFM flag if none of the first plurality of count values ​​crosses the first threshold. For example, the method 500 may include setting the RFM flag if at least one address is present in an aggressor queue associated with the first portion, and unsetting the RFM flag if the associated aggressor queue is empty.

[0079] Method 500 includes block 540, which depicts changing a second count value (eg, Figure 1 114 and / or Figure 4 412 of the present invention. The second count value is associated with the portion. For example, method 500 may include incrementing the second count value in response to an access operation. The RFM logic circuit of the controller may receive an address (e.g., a memory bank address) associated with the portion and change the second count value in response to the address.

[0080] Block 540 is followed by block 550, which describes checking the state of the RFM flag in the memory if the second count value has crossed the second threshold. The method 500 may include comparing the second count value to the second threshold, and checking the state of the RFM flag when the second count value is greater than or equal to (or greater than) the second threshold. The method 500 may include resetting the second count value after checking the state. In some embodiments, the method 500 may include rolling the second count value to an initial value, and checking the state in response to the second count value rolling.

[0081] Checking the status may include issuing an MRR command to a mode register of the memory. The MRR command may specify a register that holds an RFM flag associated with the portion. The RFM flag may be one of a plurality of RFM flags, each associated with a different portion. The method 500 may include providing a value of the RFM flag from the memory to the controller. The method 500 may include checking the RFM flag when performing access operations on different portions of the memory.

[0082] Block 550 may be followed by block 560, which describes issuing an RFM command from the controller to the memory if the flag is set. The method 500 may include not issuing the RFM command if the flag is unset. The method 500 may include performing one or more targeted refresh operations with the memory in response to the RFM command. Performing the targeted refresh operation may include generating a refresh address based on the address in the aggressor queue, and refreshing one or more word lines in the portion based on the refresh address. The method may include removing the address from the aggressor queue after performing the targeted refresh operation.

[0083] It should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or separated and / or performed in a separate device or device portion according to the present systems, devices, and methods.

[0084] Finally, the above discussion is intended to be illustrative only of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the present system has been described in particular detail with reference to exemplary embodiments, it should also be understood that numerous modifications and alternative embodiments may be devised by one of ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as subsequently set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: A memory array comprising: a first portion comprising a first plurality of word lines; a second portion comprising a second plurality of word lines; a mode register comprising a first refresh management (RFM) flag associated with the first portion and a second RFM flag associated with the second portion; a first refresh control circuit configured to set the first RFM flag based on a first plurality of count values, each count value being associated with one of the first plurality of word lines; and a second refresh control circuit configured to set the second RFM flag based on a second plurality of count values, each count value being associated with one of the second plurality of word lines, Wherein the first refresh control circuit is configured to set the first RFM flag if the first aggressor queue includes at least one address, and wherein the second refresh control circuit is configured to set the second RFM flag if the second aggressor queue includes at least one address.

2. The apparatus of claim 1, wherein the mode register is configured to provide a state of the first RFM flag when accessing the second portion of the memory array.

3. The apparatus of claim 1, wherein the first portion is a first memory bank and the second portion is a second memory bank.

4. The apparatus of claim 1, wherein the first portion is a first sub-bank and the second portion is a second sub-bank.

5. The apparatus of claim 1 , wherein the first plurality of word lines are configured to store the first plurality of count values, and The second plurality of word lines are configured to store the second plurality of count values.

6. The apparatus of claim 1 , wherein the first refresh control circuit comprises a first aggressor queue configured to store aggressor addresses based on the first plurality of count values, and The second refresh control circuit includes a second aggressor queue configured to store aggressor addresses based on the second plurality of count values.

7. The apparatus of claim 1 , wherein the first refresh control circuit is configured to perform a target refresh operation in response to an RFM command directed to the first portion, and Wherein the second refresh control circuit is configured to perform a target refresh operation in response to an RFM command directed to the second portion.

8. The apparatus of claim 1 , wherein the first refresh control circuit is configured to set the first RFM flag if at least one of the first plurality of count values ​​is above a threshold, and to unset the first RFM flag if none of the first plurality of count values ​​is above the threshold, and wherein the second refresh control circuit is configured to set the second RFM flag if at least one of the second plurality of count values ​​is above the threshold, and to unset the second RFM flag if none of the second plurality of count values ​​is above the threshold.

9. The apparatus of claim 1 , wherein the first refresh control circuit is configured to change a selected one of the first count values ​​in response to the associated one of the first plurality of word lines being accessed, and wherein the second refresh control circuit is configured to change a selected one of the second count values ​​in response to the associated one of the second plurality of word lines being accessed.

10. A system comprising: A memory comprising: a memory array comprising a plurality of portions, each of the plurality of portions comprising a respective plurality of word lines, each word line being associated with a respective one of a plurality of count values; a mode register comprising a plurality of refresh management flags, each refresh management flag being associated with one of the plurality of portions; and a plurality of refresh control circuits configured to set or unset the plurality of RFM flags based on the plurality of count values ​​associated with the one of the plurality of portions associated with the RFM flag; and A controller is configured to count a number of access operations of each of the plurality of portions, check the associated one of the plurality of RFM flags based on the count value, and provide an RFM command to the memory if the checked associated one of the plurality of RFM flags is set.

11. The system of claim 10 , wherein the plurality of refresh control circuits are configured to set the associated one of the plurality of RFM flags if any of the associated plurality of count values ​​is above a threshold, and to unset the associated one of the plurality of RFM flags if any of the associated plurality of count values ​​is not above the threshold.

12. The system of claim 10, wherein the plurality of refresh control circuits are configured to change a value of a selected one of the associated plurality of count values ​​in response to a selected one of the associated plurality of word lines being accessed.

13. The system of claim 10, wherein the controller is configured to check the associated one of the plurality of RFM flags in response to the number of the access operations crossing a threshold.

14. The system of claim 10, wherein the controller is configured to check the associated one of the plurality of RFM flags by performing a mode register read operation on the memory.

15. The system of claim 14, wherein the controller is configured to perform access operations on different portions of the memory while performing the mode register read operation.

16. A method comprising: performing, with a controller, an access operation on a selected word line in a portion of a memory array of a memory; changing a first count value in the memory in response to performing the access operation on the selected word line, wherein the first count value is associated with the selected word line; If the first count value crosses a first threshold, setting a refresh management (RFM) flag in the memory; changing a second count value in the controller in response to performing the access operation on the portion, wherein the second count value is associated with the portion; If the second count value has crossed a second threshold, checking the state of the RFM flag; and If the RFM flag is set, then an RFM command is issued to the memory.

17. The method according to claim 16, further comprising: providing address information from the controller to the memory, wherein the address information specifies the portion of the memory array; and The second count value is changed in response to the address information.

18. The method of claim 16, further comprising incrementing the first count value in response to performing the access operation on the word line; and The second count value is incremented in response to performing the access operation on the portion.

19. The method of claim 16, further comprising storing a row address in an aggressor queue in response to the first count value crossing the first threshold.

20. The method of claim 16, wherein checking the state of the RFM flag comprises performing a mode register read (MRR) operation on a mode register of the memory.

21. The method of claim 20, further comprising performing an access operation on another portion of the memory array while performing the MRR operation.

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