Control device for controlling storage device and method thereof

Abstract

The invention provides a control apparatus and a control method thereof. The control device is used for controlling operation of the storage device. The storage device comprises a plurality of storage blocks, each storage block comprises a plurality of storage units, and each storage unit stores bit data. The control device comprises a processor used for classifying the storage units into a plurality of groups according to erase counts of the storage units, and the groups respectively correspond to a plurality of recovery times; the memory interface control circuit is coupled to the processor and the storage device, and the processor controls the storage device to execute a bit recovery operation through the memory interface control circuit. Wherein the processor selects one of the groups according to the recovery times, and performs a bit recovery operation on the bit data of each memory cell in the selected group.

Description

Technical Field

[0001] The present disclosure relates to a control device and a control method of a storage device, and more particularly to a bit recovery mechanism of a storage device. Background Art

[0002] In semiconductor technology, the memory cell of a memory device includes various forms. One form is phase change memory (PCM). PCM can operate in a crystalline state and an amorphous state. In the amorphous state, the resistance value of the PCM will drift over time, and the drift of the resistance value will affect the recognition of the operating state of the PCM.

[0003] The drift of the resistance value of the phase change memory can be corrected by a refresh operation (ie, a restore operation). However, a large number of restore operations will also worsen the drift of the resistance value, which may shorten the life of the phase change memory.

[0004] In view of the above issues, an improved recovery operation mechanism is needed, which can dynamically perform recovery operations for phase change memories with different drift degrees, thereby reducing the number of recovery operations.

[0005] Public Content

[0006] According to one aspect of the present disclosure, a control device is provided for controlling the operation of a storage device. The storage device includes a plurality of storage blocks, each of which includes a plurality of storage cells, each of which stores bit data, and the control device includes: a processor, for classifying the storage cells into a plurality of groups according to the erase counts of the storage cells, the groups corresponding to a plurality of recovery times respectively; a memory interface control circuit, coupled to the processor and the storage device, the processor controlling the storage device to perform a bit recovery operation via the memory interface control circuit. The processor selects one of the groups according to the recovery times, and performs the bit recovery operation on the bit data of each of the storage cells in the selected group.

[0007] According to another aspect of the present disclosure, a control method for a storage device is provided, and the control method is used to control the storage device. The storage device includes a plurality of storage blocks, each of which includes a plurality of storage cells, each of which stores bit data, and the control method includes the following steps. The storage cells are classified into a plurality of groups according to the erase counts of each of the storage cells by a processor, wherein the groups correspond to a plurality of recovery times respectively. The storage device is controlled by the processor via a memory interface control circuit to perform a bit recovery operation, including: selecting one of the groups according to the recovery times by the processor, and performing the bit recovery operation on the bit data of each of the storage cells in the selected group.

[0008] Other aspects and advantages of the present disclosure will become apparent from a review of the following drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 4 is a functional block diagram of a control device according to an embodiment of the present disclosure.

[0010] Figure 2 Schematic diagram of the drift of the resistance value of a memory cell.

[0011] Figure 3 is a schematic diagram of the operating voltage of a memory cell.

[0012] Figure 4 FIG. 1 is a diagram showing a relationship between a normalized resistance value of a memory cell and time according to an embodiment of the present invention.

[0013] Figure 5 The figure is a flow chart of a control method of a memory device according to an embodiment of the present disclosure.

[0014] Figure 6 FIG. 4 is a diagram showing another embodiment of the relationship between the normalized resistance value of a memory cell and time.

[0015] Description of Reference Numerals

[0016] 1000: Control device

[0017] 2000: Storage Devices

[0018] 100: Host interface control circuit

[0019] 200: Buffer management circuit

[0020] 300: Processor

[0021] 400: Memory interface control circuit

[0022] 500: Buffer memory

[0023] blk1, blk2: storage blocks

[0024] C11, C1N, CM1, CMN: Storage Unit

[0025] WL1, WLN: word line

[0026] BL1, BLM: bit line

[0027] μ: drift coefficient

[0028] VtR: Amorphous

[0029] VtS: Crystalline

[0030] R(t): resistance value

[0031] Rn(t), Rn1(t), Rn2(t), Rn3(t), Rn4(t): Normalized resistance values

[0032] O_mar: operating margin

[0033] R_win: Read window

[0034] t1, t2, t1′, t2′, t3′, t4′: time

[0035] RT1, RT2, RT3, RT4: Recovery time

[0036] S100~S114: Steps DETAILED DESCRIPTION

[0037] The technical terms in this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, technicians in this technical field may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0038] See also Figure 1 , which is a functional block diagram of a control device 1000 according to an embodiment of the present disclosure. The control device 1000 includes a host interface control circuit 100, a buffer management circuit 200, a processor 300, a memory interface control circuit 400, and a buffer memory 500. The control device 1000 is coupled to the storage device 2000, and the control device 1000 is used to control the operation of the storage device 2000.

[0039] In one example, the processor 300 may be a separate computing processor in the control device 1000, such as a central processing unit (CPU), a microprocessor (micro-processor), a microcontroller (MCU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA), etc. On the other hand, the host interface control circuit 100, the buffer management circuit 200, and the memory interface control circuit 400 are each a separate computing circuit in the control device 1000.

[0040] In another example, the control device 1000 may be a separate computing processor, such as a separate central processing unit, microprocessor, microcontroller, digital signal processor, or programmable logic gate array. Correspondingly, the host interface control circuit 100, the buffer management circuit 200, the processor 300, and the memory interface control circuit 400 are respectively a computing unit in the control device 1000.

[0041] The processor 300 of the control device 1000 is coupled to the memory device 2000 via the memory interface control circuit 400. The memory device 2000 includes a plurality of memory blocks, for example, two memory blocks blk1 and blk2. Each of the memory blocks blk1 and blk2 includes a plurality of memory cells C11-CMN, a plurality of word lines WL1-WLN, and a plurality of bit lines BL1-BLM. The memory cells C11-CMN are connected to the word lines WL1-WLN and the bit lines BL1-BLM respectively. Each of the memory cells C11-CMN is, for example, a phase change memory (PCM). As a phase change memory, the resistance value of each of the memory cells C11-CMN in an amorphous state will drift over time.

[0042] Next, see Figure 2 , which is a schematic diagram of the drift of the resistance value R(t) of the memory cells C11 to CMN. The resistance value R(t) of the memory cells C11 to CMN is expressed as formula (1):

[0043] R(t)=R0×(t / t0) μ (1)

[0044] In formula (1), t is time, t0 is the initial time, μ is the drift coefficient, and R0 is the resistance value at the initial time t0. Figure 2 In the figure, VtS represents the crystal state and VtR represents the amorphous state. When the memory cells C11-CMN are in the crystal state, the resistance value R0 at the initial time t0 is equal to 5.4×(10) 3 Ω, the drift coefficient μ is equal to 0.0008. Figure 2 As shown, the resistance value R(t) of the crystalline state does not drift much over time.

[0045] On the other hand, when the memory cells C11-CMN are in the amorphous state, the resistance value R0 at the initial time t0 is equal to 2×(10) 6 Ω, the drift coefficient μ is equal to 0.11. Since the drift coefficient μ of the amorphous state is much larger than the drift coefficient μ of the crystalline state, Figure 2 As shown, the drift of the resistance value R(t) of the amorphous state with time is greater than that of the crystalline state. The drift of the resistance value R(t) of the amorphous state has a negative impact on the recognition of the operation state of the memory cells C11-CMN.

[0046] Next, see Figure 3 , which is a schematic diagram of the operating voltage of the memory cells C11-CMN. In the crystalline state, the upper limit voltage of the operating voltage of the memory cells C11-CMN is 6V, the lower limit voltage is 5.25V, and the voltage corresponding to the peak is 5.625V. In the amorphous state, the upper limit voltage of the operating voltage of the memory cells C11-CMN is 8.25V, the lower limit voltage is 7.5V, and the voltage corresponding to the peak is 7.875V. Therefore, the width of the operation window of the memory cells C11-CMN is 2.25V (i.e., the voltage difference between the voltage 5.625V corresponding to the peak of the crystalline state and the voltage 7.875V corresponding to the peak of the amorphous state). On the other hand, the read window R_win of the memory cells C11-CMN is between the voltage 6.5V and the voltage 7V, and the width of the read window R_win is 0.5V. In addition, the operation margin O_mar of the memory cells C11-CMN is between the voltage of 4.5V and the voltage of 9V. The upper limit voltage of the operation voltage of the amorphous state must be lower than the upper limit voltage of the operation margin O_mar of 9V.

[0047] When the resistance value R(t) of the memory cells C11-CMN drifts over time, the upper limit voltage / lower limit voltage of the amorphous state and / or crystalline state of the memory cells C11-CMN will also drift, thereby affecting the identification of the operating state of the memory cells C11-CMN. For example, when the resistance value R(t) drifts, the upper limit voltage of the amorphous state of the memory cells C11-CMN increases to 8.75V. In one example, according to the upper limit voltage of 9V of the operating margin O_mar, the tolerance of the drift of the upper limit voltage of the amorphous state is set to 10%. Therefore, when the upper limit voltage of the amorphous state of one or more of the memory cells C11-CMN increases (i.e., drifts upward) to 8.75V, it is necessary to selectively perform a refresh operation (refresh operation), also known as a recovery operation, on one or more of the memory cells C11-CMN that have drifted. When each of the memory cells C11-CMN stores one bit of data, the refresh operation is also known as a bit recovery operation. Hereinafter, the refresh operation of the memory cells C11 ˜CMN is referred to as a bit restore operation.

[0048] From the perspective of operating voltage, when the drift of the upper voltage limit of the amorphous state reaches a predetermined tolerance (e.g., 10%), a bit recovery operation must be selectively performed on the memory cells C11 to CMN. From the perspective of resistance value R(t), when the drift of resistance value R(t) reaches a predetermined tolerance (e.g., 10%), a bit recovery operation must be selectively performed on the memory cells C11 to CMN.

[0049] Next, see Figure 4 , which is a schematic diagram of an embodiment of the relationship between the normalized resistance value Rn(t) of the memory cells C11-CMN and the time t. The resistance value R(t) of the memory cells C11-CMN is normalized to the resistance value R0 at the initial time t0 to obtain the normalized resistance value Rn(t). At the initial time t0, the normalized resistance value Rn(t0) of the memory cells C11-CMN is equal to the value 1. The normalized resistance value Rn(t) in the amorphous state will drift over time, and the drift amount of the normalized resistance value Rn(t) (i.e., the change compared to the normalized resistance value Rn(t0)=1 at the initial time t0) is related to the drift coefficient μ. When the drift coefficient μ is small, it takes a longer time for the normalized resistance value Rn(t) to increase to the value 1.1 (i.e., the drift amount reaches a tolerance of 10%). In contrast, when the drift coefficient μ is larger, the drift of the normalized resistance value Rn(t) can reach a tolerance of 10% in a shorter time.

[0050] For example, when the drift coefficient μ is equal to a smaller value of 0.005, the normalized resistance value Rn2(t2) increases to a value of 1.1 in a longer time t2. The time t2 is approximately equal to 10E4 (10 to the fourth power) seconds. In contrast, when the drift coefficient μ is equal to a larger value of 0.086, the normalized resistance value Rn1(t1) increases to a value of 1.1 in a shorter time t1 (time t1 is less than 10 seconds).

[0051] When the drift of the normalized resistance value Rn(t) of the memory cells C11-CMN reaches a tolerance of 10%, the memory cells C11-CMN must be selectively subjected to a bit recovery operation. In a comparative example, as long as the drift of the normalized resistance value Rn(t) of one of the memory cells C11-CMN reaches a tolerance of 10%, the bit recovery operation is performed on all the memory cells C11-CMN. However, as the number of bit recovery operations (called cycling times) of the memory cells C11-CMN increases, the degree of wear of the memory cells C11-CMN increases, thereby reducing the life time (lifetime) of the memory cells C11-CMN. Moreover, the number of bit recovery operations of the memory cells C11-CMN will also affect the drift coefficient μ. In the above comparative example, when the drift of the resistance value of a memory cell with a larger drift degree (e.g., memory cell C11) reaches a tolerance of 10% and a bit recovery operation is performed, other better memory cells (with a lower wear degree) also need to perform a bit recovery operation. Too many bit recovery operations will increase the wear degree of the better memory cells.

[0052] Compared with the above-mentioned comparative example, the bit recovery mechanism of the present disclosure applies a dynamic refresh cycle to storage cells with different resistance drift degrees. A higher frequency bit recovery operation is performed for storage cells with larger resistance drift, and a lower frequency bit recovery operation is performed for storage cells with smaller resistance drift. Therefore, the number of bit recovery operations for better (less worn) storage cells can be reduced.

[0053] Next, see Figure 5 , which is a flowchart of a control method of a memory device 2000 according to an embodiment of the present disclosure. Figure 5 The control method shown is related to a bit recovery mechanism, which is applied to the memory cells C11-CMN in the memory blocks blk1 and blk2 of the memory device 2000. The process of the bit recovery mechanism is described as follows. First, in step S100, a recovery time mapping table is established by the processor 300 of the control device 1000. The processor 300 can establish the recovery time mapping table according to the relationship between the normalized resistance value Rn(t) of the memory cells C11-CMN and the time t. Please also refer to Figure 6, which is a schematic diagram of another embodiment of the relationship between the normalized resistance value Rn(t) of the memory cells C11-CMN and the time t (similar to Figure 4 Embodiment). The drift coefficient μ of the resistance value R(t) of the memory cells C11-CMN is related to the number of erase operations that have been performed. The number of erase operations that have been performed is called the erase count, and the number of erase counts can also be called the number of cycles. When the erase count of a memory cell is large, it means that the memory cell has performed more erase operations, and therefore, the wear of the memory cell is greater, resulting in a larger drift coefficient μ of the resistance value R(t).

[0054] For example, the erase count EC1 of each memory cell of a portion of the memory cells C11-CMN is between 10E6 (10 to the sixth power) and 10E5. According to the relationship curve between the normalized resistance value Rn1(t) and the time t of the memory cells of this portion, it can be estimated that the drift coefficient μ of the memory cells of this portion is substantially equal to the value 0.08. Please also refer to Table 1, which is an example of the recovery time mapping table established by the processor 300. In the recovery time mapping table, the memory cells with the erase count EC1 between 10E6 and 10E5 are classified as group G1.

[0055] And, according to Figure 6 As shown in the relationship between the normalized resistance value Rn(t) and the time t, the normalized resistance value Rn1(t) of the memory cell of group G1 increases to a value of 1.1 at time t1′, that is, the drift of the normalized resistance value Rn1(t) reaches a tolerance of 10% at time t1′. The time t1′ is about 4 seconds. Therefore, each of the memory cells of group G1 must perform a bit recovery operation before time t1′.

[0056] Please refer to Table 1 again. The time for the memory cells of group G1 to perform the bit recovery operation is defined as the recovery time RT1. The recovery time RT1 of each memory cell of group G1 must be less than Figure 6 The time t1' shown is, for example, the recovery time RT1 is set to 10E0 seconds (ie, 1 second).

[0057] Table 1

[0058] Erase count Recovery time (seconds) Storage unit group 10E5<EC1<10E6 RT1=10E0 G1 10E4<EC2<10E5 RT2=10E2 G2 10E3<EC3<10E4 RT3=10E4 G3 10E2<EC4<10E3 RT4=10E7 G4

[0059] On the other hand, the erase count EC2 of each memory cell of another part of the memory cells C11~CMN is between 10E5 and 10E4, indicating that the erase operation performed on the memory cells in this part is less. The wear degree of these memory cells is less, so their resistance value R(t) has a smaller drift coefficient μ. According to the relationship curve between the normalized resistance value Rn2(t) and time t of the memory cells in this part, it can be estimated that its drift coefficient μ is substantially equal to the value 0.019. In the recovery time mapping table, these memory cells with erase count EC2 between 10E5 and 10E4 are classified as group G2. And, according to Figure 6 , the normalized resistance value Rn2(t) of the memory cell of group G2 increases to a value of 1.1 at time t2′ (its drift reaches a tolerance of 10% at time t2′), and time t2′ is approximately 2×10E2 seconds. Correspondingly, in the recovery time mapping table, the recovery time RT2 of each memory cell of group G2 is set to 10E2 seconds, and the recovery time RT2 is less than time t2′.

[0060] Furthermore, the erase count EC3 of each memory cell of another part of the memory cells C11-CMN is between 10E4 and 10E3, indicating that the erase operation performed on the memory cells of this part is fewer times, and thus the degree of wear is smaller, and the resistance value R(t) has a smaller drift coefficient μ. These memory cells with the erase count EC3 between 10E4 and 10E3 are classified as group G3. According to the relationship curve between the normalized resistance value Rn3(t) and the time t of the memory cells of group G3, it can be estimated that the drift coefficient μ is substantially equal to the value 0.009, and it is estimated that the normalized resistance value Rn3(t) reaches a tolerance of 10% at time t3′ (time t3′ is approximately 2×10E4 seconds). In the recovery time mapping table, the recovery time RT3 of each memory cell of group G3 is set to 10E4 seconds, which is less than the time t3′.

[0061] Similarly, the erase count EC4 of each memory cell of another part of the memory cells C11-CMN is between 10E3 and 10E2, indicating that the wear degree thereof is smaller and thus has a smaller drift coefficient μ. These memory cells with the erase count EC4 between 10E3 and 10E2 are classified as group G4. It can be estimated that the drift coefficient μ of the memory cells of group G4 is substantially equal to the value 0.001, and its normalized resistance value Rn4(t) reaches a tolerance of 10% at time t4′ (time t4′ is approximately 2×10E7 seconds). In the recovery time mapping table, the recovery time RT4 of each memory cell of group G4 is set to 10E7 seconds, which is less than time t4′.

[0062] Next, in step S102, the processor 300 of the control device 1000 establishes an erase count table according to the physical address of the storage unit in the storage device 2000 and the number of times the storage unit has performed an erase operation. Table 2 is an example of an erase count table, in which the erase count of the storage unit whose physical address is "1" is 5.2×10E5, the erase count of the storage unit whose physical address is "5" is 4.7×10E3, the erase count of the storage unit whose physical address is "9" is 2.2×10E2, and so on.

[0063] Table 2

[0064]

[0065]

[0066] Next, in step S104, the processor 300 of the control device 1000 establishes a translation mapping table according to the mapping relationship between the physical address and the logical address of the storage unit in the storage device 2000. Table 3 is an example of a translation mapping table, in which the physical address "1" of the storage unit is mapped to the logical address "0", the physical address "5" of the storage unit is mapped to the logical address "1", the physical address "9" of the storage unit is mapped to the logical address "2", and so on.

[0067] Table 3

[0068] Logical address Physical Address 0 1 1 5 2 9 3 28 … … 30 17 31 22

[0069] Next, in step S106, the processor 300 of the control device 1000 establishes a bit recovery table according to the recovery time mapping table, the erase count table and the translation mapping table. Table 4 is an example of a bit recovery table, wherein the erase count of the storage unit whose physical address is "1" is 5.2×10E5, which is between 10E6 and 10E5. According to the recovery time mapping table of Table 1, the storage unit whose erase count is between 10E6 and 10E5 is defined as group G1, so the storage unit whose physical address is "1" is classified as group G1.

[0070] On the other hand, the erase count of the memory cell with the physical address "5" is 4.7×10E3, which is between 10E3 and 10E4. According to the recovery time mapping table of Table 1, the memory cells with the erase count between 10E3 and 10E4 are defined as group G3, so the memory cell with the physical address "5" is classified into group G3.

[0071] Similarly, the erase count of the memory cell with physical address "9" is 2.2×10E2, which is between 10E2 and 10E3. According to the recovery time mapping table of Table 1, the memory cells with erase counts between 10E2 and 10E3 are defined as group G4, so the memory cell with physical address "9" is classified into group G4.

[0072] By analogy, the erase count of the memory cell with the physical address "28" is 3.9×10E5, which is classified as group G1. The erase count of the memory cell with the physical address "17" is 2.8×10E2, which is classified as group G4. The erase count of the memory cell with the physical address "22" is 1.7×10E4, which is classified as group G2.

[0073] Table 4

[0074] Physical Address Erase count Storage unit group 1 5.2×10E5 G1 5 4.7×10E3 G3 9 2.2×10E2 G4 28 3.9×10E5 G1 … … 17 2.8×10E2 G4 22 1.7×10E4 G2

[0075] According to the bit recovery table in Table 4, it can be known that the storage cells at different physical addresses in the storage device 2000 are classified into group G1, group G2, group G3 or group G4. The storage cells in different groups have different degrees of wear. In the bit recovery mechanism of this embodiment, the processor 300 selectively performs bit recovery operations on the storage cells in different groups according to the bit recovery table. In other words, the bit recovery operations are performed individually in response to the different degrees of wear of the storage cells. The bit recovery mechanism of this embodiment includes 4 recovery operation cycles, and these recovery operation cycles correspond to the recovery times RT1 to RT4 of the storage cells in groups G1 to G4. In one recovery operation cycle, the bit recovery operation is performed only on one group. For example, in the recovery operation cycle of the recovery time RT1 (i.e., 10E0 seconds), the bit recovery operation is performed on all the storage cells in group G1, and in the recovery operation cycle of the recovery time RT2 (i.e., 10E2 seconds), the bit recovery operation is performed only on group G1, and so on.

[0076] The processor 300 selects one of the groups G1 to G4 according to the recovery time RT1 to RT4, and performs a bit recovery operation on the bit data of each storage unit in the selected group. In step S108, it is determined whether one of the recovery times RT1 to RT4 has been reached. If the determination result is no, then return to step S106. If the determination result is yes, then execute steps S110 and S112, the processor 300 selects the group that has reached the recovery time, and performs a bit recovery operation on each storage unit in the selected group. For example, when the determination result of step S108 indicates that the recovery time RT1 has been reached, the processor 300 selects the group G1 corresponding to the recovery time RT1, and performs a bit recovery operation on each storage unit in the selected group G1. The bit recovery operation includes a read operation and a write operation. In this embodiment, the processor 300 of the control device 1000 controls the storage device 2000 via the memory interface control circuit 400 to perform a read operation and a write operation on the storage units of the individual groups.

[0077] In step S110, a read operation is performed on the memory cells of the group that has reached the recovery time. For example, if the determination result of step S108 indicates that the recovery time RT1 has been reached, the processor 300 controls the memory device 2000 to perform a read operation on all the memory cells of the group G1 via the memory interface control circuit 400, so as to read the bit data stored in each memory cell of the group G1 to the buffer memory 500.

[0078] Next, in step S112, the processor 300 updates the bit recovery table. For example, if the erase counts of some storage units in the storage device 2000 have changed, the processor 300 adjusts the classification of these groups and classifies these storage units into appropriate groups according to the latest erase counts.

[0079] Next, in step S114, a write operation is performed on the memory cells of the group that has reached the recovery time, so as to write the bit data read to the buffer memory 500 in step S110 back to the memory cells of this group. Taking the group G1 that has reached the recovery time RT1 as an example, the processor 300 controls the memory device 2000 via the memory interface control circuit 400 to write the bit data (previously read to the buffer memory 500) back to the memory cells of the group G1.

[0080] The read operation and write operation in the bit recovery operation of the present embodiment are controlled by the processor 300 of the control device 1000. The processor 300 controls the storage device 2000 to perform the read operation and the write operation through the memory interface control circuit 400, and accesses the bit data of the storage unit of the specific group in the storage device 2000 to the buffer memory 500. On the other hand, the conventional read operation and write operation are performed by the processor 300 in cooperation with the host interface control circuit 100 and the buffer management circuit 200.

[0081] Next, refer to Table 5, which is an example of a corresponding table of recovery time and address of the present disclosure. The bit recovery mechanism of the present disclosure is executed dynamically, and the bit recovery operation is dynamically performed according to the recovery time RT1~RT4 of the storage cells with different physical addresses. For example, the bit recovery operation is performed when the storage cell of the physical address "1" reaches the recovery time RT1 (i.e., 10E0 seconds). The bit recovery operation is performed when the storage cell of the physical address "5" reaches the recovery time RT3 (i.e., 10E4 seconds). The bit recovery operation is performed when the storage cell of the physical address "9" reaches the recovery time RT4 (i.e., 10E7 seconds).

[0082] Table 5

[0083] Physical Address Erase count Recovery time (seconds) 1 5.2×10E5 RT1=10E0 5 4.7×10E3 RT3=10E4 9 2.2×10E2 RT4=10E7 28 3.9×10E5 RT1=10E0 … … 17 2.8×10E2 RT4=10E7 22 1.7×10E4 RT2=10E2

[0084] On the other hand, see Table 6, which is a corresponding table of recovery time and address of a comparative example. In this comparative example, as long as the drift amount of one of the storage cells of the storage device 2000 reaches a predetermined tolerance, a bit recovery operation is performed on all the storage cells in the same storage block. In other words, the bit recovery mechanism of this comparative example cannot be adjusted dynamically. For example, the erase count of the storage cell with physical address "1" has a large value of 5.2×10E5, indicating that the wear degree of the storage cell with physical address "1" is the largest, and these storage cells reach the tolerance of the drift amount at the recovery time RT1 (i.e., 10E0 seconds). The bit recovery operation must be performed on all the storage cells in the same storage block at the earlier recovery time RT1. Therefore, the storage cells with different physical addresses in the same storage block perform the bit recovery operation at the same time, and the execution time is related to the recovery time RT1. Even if the erase counts of memory cells at some addresses are small, these memory cells still need to perform bit recovery operations at the earlier recovery time RT1, which causes these memory cells with small erase counts to perform bit recovery operations early, resulting in increased wear levels.

[0085] Table 6

[0086]

[0087]

[0088] Compared to the fixed bit recovery mechanism of the above comparative example, the dynamic bit recovery mechanism of the present disclosure is dynamically executed for groups G1-G4 with different recovery times RT1-RT4. The time for executing the bit recovery operation of the storage cells of different groups is different. Therefore, the storage cells with smaller erase counts execute the bit recovery operation at a later recovery time (e.g., recovery time RT4=10E7 seconds), which can reduce the degree of wear.

[0089] In the above-mentioned multiple embodiments, the bit recovery mechanism of the present disclosure is to classify the storage cells into 4 groups G1-G4. In other embodiments, when the drift coefficient μ is large, the drift amount can reach the predetermined tolerance in a shorter time, and the recovery time of the storage cells with different erase counts (corresponding to different drift coefficients μ) has a large difference. Therefore, the storage cells can be further divided into more groups, for example, further divided into 16 groups G1-G16, so as to perform the bit recovery operation more accurately and flexibly for the storage cells with different erase counts (indicating different degrees of wear).

[0090] Although the present disclosure has been disclosed in detail with preferred embodiments and examples as above, it is to be understood that these examples are intended to be illustrative rather than restrictive. It is contemplated that a person skilled in the art may conceive of various modifications and combinations, which fall within the spirit of the present disclosure and the scope of the appended claims.

Claims

1. A control device for controlling the operation of a storage device, wherein the storage device comprises a plurality of storage blocks, each of the storage blocks comprises a plurality of storage cells, each of the storage cells stores one bit of data, the control device comprising: a processor, configured to classify the storage cells into a plurality of groups according to an erase count of each of the storage cells, the groups corresponding to a plurality of recovery times respectively; as well as a memory interface control circuit coupled to the processor and the memory device, wherein the processor controls the memory device to perform a one-bit recovery operation via the memory interface control circuit; The processor selects one of the groups according to the recovery times, and performs the bit recovery operation on the bit data of each storage unit in the selected group.

2. The control device according to claim 1, further comprising: a buffer memory coupled to the processor, The bit recovery operation includes a read operation and a write operation. The processor performs the read operation to read the bit data of each storage unit in the selected group into the buffer memory. The processor executes the write operation to write the bit of data read from the buffer memory back to the corresponding storage unit.

3. The control device according to claim 1, wherein each of the memory cells is a phase change memory operating in a crystalline state and an amorphous state, each of the memory cells has a normalized resistance value, and the recovery time of each of the groups is the time for a drift of the normalized resistance value to reach a predetermined tolerance.

4. The control device according to claim 3, wherein the processor establishes a recovery time mapping table according to the normalized resistance value of each of the memory cells, and the recovery time mapping table includes a corresponding relationship between the recovery time of each of the groups and the erase count of each of the memory cells in the group. 5 . The control device according to claim 4 , wherein the processor establishes an erase count table according to a physical address of each storage unit in the storage device and the erase count. 6 . The control device according to claim 5 , wherein the processor establishes a translation mapping table according to a mapping relationship between a logical address of each storage unit in the storage device and the physical address. 7 . The control device according to claim 6 , wherein the processor establishes a bit recovery table according to the recovery time mapping table, the erase count table and the translation mapping table, and selectively performs the bit recovery operation on the groups according to the bit recovery table.

8. The control device according to claim 7, wherein: After performing the bit restoration operation, the processor updates the bit restoration table to adjust the classification of the groups.

9. A control method for a storage device, wherein the storage device comprises a plurality of storage blocks, each of the storage blocks comprises a plurality of storage cells, each of the storage cells stores one bit of data, the control method comprising: Classifying the memory cells into a plurality of groups according to an erase count of each of the memory cells by a processor, wherein the groups correspond to a plurality of recovery times respectively; as well as The processor controls the storage device via a memory interface control circuit to perform a one-bit recovery operation, including: The processor selects one of the groups according to the recovery times, and performs the bit recovery operation on the bit data of each storage unit in the selected group.

10. The control method according to claim 9, wherein: The steps to perform this bit restore operation include: A read operation is performed by the processor to read the bit data of each of the storage cells in the selected group into a buffer memory, and A write operation is performed by the processor to write the bit of data read from the buffer memory back to the corresponding storage unit.

Images