NOR type flash memory array

Abstract

The invention discloses an NOR type flash memory array which is composed of a plurality of 2T storage units. Wherein the 2T storage unit comprises two parts, namely a storage tube and a selection tube, and programming and erasing operations are realized according to the change of an external signal, so that data storage is realized. The drain end of the storage tube is connected with a bit line, negative voltage is applied during programming operation, the selection tube applies negative voltage to enter a turn-off state, and the storage tube and the selection tube are free of source-drain direction current during programming. According to the programming operation, the programming current in the source-drain direction of the storage unit is eliminated, the programming power consumption is reduced, more storage units can be programmed at a time on the premise of low power consumption, and the programming speed is increased. When the method is applied to an embedded memory, the programming speed can be increased while the programming power consumption is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of non-volatile memory, and in particular to a NOR type flash memory array. Background Art

[0002] With the continuous improvement of integrated circuit design level and process technology, the complexity of circuits has also increased. Nowadays, the number of gates of designed chips ranges from several million to tens of millions. At the same time, higher and higher requirements are put forward for high speed and low power consumption of complex circuits, especially in the application of processors, memory, personal computers and computer systems. According to statistics, in 2010, memory accounted for 22% of the total integrated circuit market. In addition, with the continuous introduction of advanced processes in recent years, the proportion of memory in the entire market share has increased.

[0003] For many high-speed systems, the speed of their internal memory is very high, especially in the design of CPU, ESC, and DSP. The internal embedded memory affects the speed of the entire chip and has a very large impact on the power consumption and speed of the entire system. Therefore, how to design high-speed, reliable, and stable memory has become a problem that memory designers need to consider. Among embedded non-volatile memories, NOR-type FLASH embedded memory has the advantage of fast random read speed, but slow programming speed, and generally can only program dozens of bits at a time.

[0004] Storage unit such as Figure 1 As shown, it consists of two devices, namely the selection tube and the storage tube. The storage tube contains a floating gate, and data storage is achieved by controlling the number of electrons in the floating gate structure of the storage tube. With the continuous development of semiconductor technology, the constantly updated electronic products have put forward higher requirements on the performance of memory, including higher density, higher read and write speed and lower power consumption.

[0005] The typical flash memory array is erased by block erasure, and the erasure mechanism is based on FN tunneling, which can erase the entire sector at one time. Programming uses bit or byte programming, and the programming mechanism is hot electron programming. During programming, the source and drain of the storage unit are turned on, which consumes a large current and has high programming power consumption. At the same time, due to the high programming power consumption, the unit data that can be programmed at the same time is limited. Summary of the invention

[0006] The object of the present invention is to provide a NOR flash memory array to solve the problems in the background technology.

[0007] In order to solve the above technical problems, the present invention provides a NOR flash memory array, which is composed of a plurality of 2T storage cells; wherein:

[0008] The 2T storage unit includes two devices, a storage tube and a selection tube.

[0009] The drain end of the storage tube is connected to the bit line BL, the source end is connected to the drain end of the selection tube, the gate end is connected to the word line WL, and the substrate is connected to the well substrate BULK;

[0010] The drain end of the selection tube is connected to the source end of the storage tube, the source end is connected to the source line SL, the gate end is connected to the control line SG, and the substrate is connected to the well substrate BULK;

[0011] The state of the storage tube will change during programming and erasing operations, while the selection tube will not change with the programming and erasing operations.

[0012] In one embodiment, the word lines WL and control lines SG in the NOR flash memory array are connected in rows, each row of 2T memory cells is connected to a word line WL and a control line SG, and 2T memory cells in different rows are connected to different word lines WL and control lines SG; the bit lines BL in the NOR flash memory array are connected in columns, each column of 2T memory cells is connected to a BL, and different columns are connected to different bit lines BL; the source lines SL of all 2T memory cells in the NOR flash memory array are connected together, and the well substrates BULK of all 2T memory cells are connected together.

[0013] In one embodiment, the step of programming any number of 2T memory cells in one row includes:

[0014] The row where the 2T storage cells that need to be programmed are located has a positive voltage applied to the gate of the storage tube and a negative voltage applied to the gate of the selection tube; the row where the 2T storage cells that do not need to be programmed are located has a power supply voltage or a ground voltage applied to the gate of the storage tube and a negative voltage applied to the gate of the selection tube;

[0015] The bit lines of the column where the 2T memory cell to be programmed is located have a negative voltage applied, and the bit lines of other columns have a power supply voltage or a ground voltage applied;

[0016] A negative voltage is applied to the well substrate of the NOR flash memory array, and a ground voltage is applied to the source line or the source line is left floating.

[0017] In one embodiment, the step of erasing any row of storage cells includes:

[0018] The row where the 2T storage cells to be erased are located has a negative voltage applied to the gate of the storage tube, and a power supply voltage or a ground voltage applied to the gate of the selection tube; the row where the 2T storage cells to be erased are located has a power supply voltage or a ground voltage applied to the gate of the storage tube, and a power supply voltage or a ground voltage applied to the gate of the selection tube;

[0019] A positive voltage is applied to the well substrate of the NOR flash memory array, and a positive voltage is applied to the bit line and the source line or the bit line is left floating.

[0020] In one embodiment, the step of reading any 2T storage cells in one row includes:

[0021] The gates of the storage tubes in the row where the 2T storage cells to be read are located are applied with power supply voltage or ground voltage, and the gates of the selection tubes are applied with power supply voltage; the gates of the storage tubes in the row where the 2T storage cells not to be read are located are applied with power supply voltage or ground voltage, and the gates of the selection tubes are applied with ground voltage;

[0022] The bit line of the column where the 2T memory cell to be read is located is connected to the sense amplifier, and the bit lines of other columns are applied with power supply voltage or ground voltage;

[0023] A ground voltage is applied to the well substrate of the NOR flash memory array, and a ground voltage is applied to the source line.

[0024] A NOR flash memory array provided by the present invention can effectively improve the programming speed in embedded memory applications; the flash memory array proposed by the present invention can program thousands of bits at a time, which can greatly improve the programming speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of the traditional FLASH storage unit structure.

[0026] Figure 2 The present invention is a schematic diagram of the structure of a NOR flash memory array.

[0027] Figure 3 It is a schematic diagram of array erasing provided by the present invention.

[0028] Figure 4 It is a schematic diagram of array programming provided by the present invention.

[0029] Figure 5 It is a schematic diagram of array reading provided by the present invention. DETAILED DESCRIPTION

[0030] The following is a further detailed description of a NOR flash memory array proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0031] The present invention provides a 2T structure low power erase / program flash memory array. Both erasing and programming are based on the FN tunneling principle, so programming is based on the longitudinal electric field, the source and drain potentials of the storage unit are equal, and there is no programming current between the source and the drain. The flash memory array with 2T structure low power programming can reduce the programming power consumption of the flash memory, and at the same time can increase the number of units for parallel programming and thus improve the programming speed.

[0032] The 2T memory cell is composed of a memory tube connected in series with a selection tube. The selection tube of the traditional memory cell is connected to BL, and the memory tube is connected to SL. BL needs to be applied with a suitable voltage during programming and reading. The 2T memory cell proposed in the present invention is different in that the drain end of the memory tube is connected to the bit line BL, the source end is connected to the drain end of the selection tube, the gate end is connected to the word line WL, and the substrate is connected to the well substrate BULK; the drain end of the selection tube is connected to the source end of the memory tube, the source end is connected to the source line SL, the gate end is connected to the control line SG, and the substrate is connected to the well substrate BULK.

[0033] Figure 2 The schematic diagram of a 2T memory array with 4 rows and 4 columns, with a total of 16 2T memory cells. The gates of the storage tubes and the selection tubes in each row of the 2T memory cells in the array are connected to independent gate signals WL and SG, and each column of the 2T memory cells is connected to an independent BL signal. The SL of each 2T memory cell in the array is connected together, and the BULK of each 2T memory cell is connected together.

[0034] Figure 3 For array erase operation, the gates (WL1, WL2) of the storage tubes in the row where the 2T storage cells to be erased are connected to negative voltage (NV_ERS); the gates (WL3, WL4) of the storage tubes in the row where the 2T storage cells that do not need to be erased are applied with power supply voltage or ground voltage. The substrate BULK is connected to positive voltage (PV_ERS). The gate SG of the selection tube is connected to 0V, BL is connected to the erase positive voltage (PV_ERS), and SL is connected to the erase positive voltage (PV_ERS). The gate WL and the substrate BULK must be connected as required, and the remaining SG, BL, and SL can be connected to other potentials or left floating. During erasing, all 2T storage cells in the array are selected, and the voltage difference from the storage tube substrate to the gate is PV_ERS-NV_ERS. After erasing, all cells are in the erased state.

[0035] Figure 4 For array programming operation, during programming, the row WL where the storage tube to be programmed is located is connected to a positive voltage (PV_PGM), and the WLs of the remaining rows are connected to 0V. The BL of the column where the storage tube to be programmed is located is connected to a negative voltage (NV_PGM), and the BLs of the remaining columns are connected to 0V. The storage tube substrate BULK is connected to a negative voltage (NV_PGM), the selection tube gate SG is connected to a negative voltage (NV_PGM), and SL is connected to 0V. In this embodiment, the 2T storage cell in the first row and first column (i.e., the cell corresponding to WL1 and BL1) is in a programming selected state, and the voltage difference from the gate of its storage tube to the substrate is PV_PGM-NV_PGM, and the remaining cells are in an unselected state. After programming, only the cells corresponding to WL1 and BL1 are changed from an erased state to a programmed state, and the states of the remaining cells remain unchanged.

[0036] Figure 5For array read operation, the SG of the row where the storage cell to be read is located is connected to a positive voltage (VDD), and the SG of the remaining rows is connected to 0V. All WLs in the array are connected to 0V. The BL of the column where the storage cell to be read is located is connected to a positive voltage (VRD), and the BL of the remaining columns is connected to 0V. The substrate BULK is connected to 0V, and the SL is connected to 0V. In this embodiment, the 2T storage cell in the first row and the first column (i.e., the cell corresponding to WL1 and BL1) is in a read selected state, and the remaining cells are in an unselected state. After reading, the current on BL1 corresponding to WL1 and BL1 determines whether the cell is in an erased state or a programmed state.

[0037] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A NOR flash memory array, characterized in that: It is composed of several 2T storage units; among them, The 2T storage unit includes two devices, a storage tube and a selection tube. The drain end of the storage tube is connected to the bit line BL, the source end is connected to the drain end of the selection tube, the gate end is connected to the word line WL, and the substrate is connected to the well substrate BULK; The drain end of the selection tube is connected to the source end of the storage tube, the source end is connected to the source line SL, the gate end is connected to the control line SG, and the substrate is connected to the well substrate BULK; The state of the storage tube will change during programming and erasing operations, while the selection tube will not change with the programming and erasing operations.

2. The NOR flash memory array according to claim 1, wherein: The word lines WL and control lines SG in the NOR flash memory array are connected in rows, each row of 2T memory cells is connected to a word line WL and a control line SG, and 2T memory cells in different rows are connected to different word lines WL and control lines SG; the bit lines BL in the NOR flash memory array are connected in columns, each column of 2T memory cells is connected to a BL, and different columns are connected to different bit lines BL; the source lines SL of all 2T memory cells in the NOR flash memory array are connected together, and the well substrates BULK of all 2T memory cells are connected together.

3. The NOR flash memory array according to claim 2, wherein: The steps of programming any 2T memory cells on one row include: The row where the 2T storage cells that need to be programmed are located has a positive voltage applied to the gate of the storage tube and a negative voltage applied to the gate of the selection tube; the row where the 2T storage cells that do not need to be programmed are located has a power supply voltage or a ground voltage applied to the gate of the storage tube and a negative voltage applied to the gate of the selection tube; The bit lines of the column where the 2T memory cell to be programmed is located have a negative voltage applied, and the bit lines of other columns have a power supply voltage or a ground voltage applied; A negative voltage is applied to the well substrate of the NOR flash memory array, and a ground voltage is applied to the source line or the source line is left floating.

4. The NOR flash memory array according to claim 2, wherein: The steps to erase any row of memory cells include: The row where the 2T storage cells to be erased are located has a negative voltage applied to the gate of the storage tube, and a power supply voltage or a ground voltage applied to the gate of the selection tube; the row where the 2T storage cells to be erased are located has a power supply voltage or a ground voltage applied to the gate of the storage tube, and a power supply voltage or a ground voltage applied to the gate of the selection tube; A positive voltage is applied to the well substrate of the NOR flash memory array, and a positive voltage is applied to the bit line and the source line or the bit line is left floating.

5. The NOR flash memory array as claimed in claim 2, wherein: The steps of reading any 2T storage cells on one row include: The gates of the storage tubes in the row where the 2T storage cells to be read are located are applied with power supply voltage or ground voltage, and the gates of the selection tubes are applied with power supply voltage; the gates of the storage tubes in the row where the 2T storage cells not to be read are located are applied with power supply voltage or ground voltage, and the gates of the selection tubes are applied with ground voltage; The bit line of the column where the 2T memory cell to be read is located is connected to the sense amplifier, and the bit lines of other columns are applied with power supply voltage or ground voltage; A ground voltage is applied to the well substrate of the NOR flash memory array, and a ground voltage is applied to the source line.

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