Memory output interface functional path testing method, electronic device, and medium

Abstract

The present invention relates to the field of chip testing technology, and in particular to a memory output interface functional path testing method, electronic device, and medium. The method comprises: step S1, obtaining a target output interface functional path in a functional output circuit connected to a memory output interface, and generating a target output interface functional path list; step S2, an automatic test vector generation tool selecting at least one target output interface functional path from the target output interface functional path list, and automatically generating a test vector; step S3, inputting the generated test vector into a memory through an MBIST input circuit; and step S4, creating a conversion at the output interface through the selected target output interface functional path, capturing target output data, and comparing the target output data with a preset value. If they are consistent, the test passes; otherwise, the test fails. The present invention improves the memory output interface test performance and increases the chip operating frequency.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a memory output interface functional path testing method, electronic equipment, and medium. Background Art

[0002] During chip testing, memory faults are typically tested using MBIST (Memory Built-In Self-Test) circuits integrated within the chip for testing semiconductor memories. Traditional chip testing involves inserting bypass circuits around the memory to test the peripheral circuitry and scanning the memory interface. However, MBIST circuits can only test internal memory faults and are unable to test the functional paths of the memory's output interfaces. The introduction of bypass circuits fails to truly reflect the functional paths of the output interfaces in their functional mode, and the inclusion of logic devices such as multiplexers in the bypass circuits increases the number of logic levels, further degrading timing (chip test circuit structure). Furthermore, the scan paths exclude the memory, resulting in a very low clock frequency that cannot reach the memory's actual operating frequency, which often determines the chip's maximum operating frequency. Therefore, testing the memory's output interface functional paths and increasing the chip's operating frequency have become pressing technical challenges. Summary of the Invention

[0003] The present invention aims to provide a memory output interface functional path testing method, electronic equipment and medium, which improve the memory output interface testing performance and increase the chip operating frequency.

[0004] According to a first aspect of the present invention, a method for testing a memory output interface functional path is provided, comprising:

[0005] Step S1: obtaining a target output interface functional path in a functional output circuit connected to a memory output interface, and generating a target output interface functional path list;

[0006] Step S2: The automatic test vector generation tool selects at least one target output interface function path from the target output interface function path list, and automatically generates a test vector based on the selected target output interface function path;

[0007] Step S3, the generated test vector is input into the memory by the MBIST input circuit connected to the memory input interface;

[0008] Step S4: Create a conversion at the output interface through the selected target output interface functional path, capture target output data, and compare the target output data with the preset value. If they are consistent, the test passes; otherwise, the test fails.

[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0011] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the present invention provides a memory output interface functional path testing method, electronic device, and medium that achieve considerable technological advancement and practicality, and has wide industrial application value, with at least the following beneficial effects:

[0012] The present invention can reduce the workload required for testing output interface functional paths by setting a target output interface functional path list, and uses an MBIST input circuit as an input circuit of an accessor and a functional output circuit as a target data capture circuit, thereby reducing the number of test vectors generated, and the tests of all target output interface functional paths pass through the memory, thereby achieving full-speed testing and improving chip frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 This is a flow chart of a method for testing the functional path of a memory output interface provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a method for testing a memory output interface function path, such as Figure 1 Shown, including:

[0017] Step S1: Acquire a target output interface functional path in a functional output circuit connected to a memory output interface, and generate a target output interface functional path list.

[0018] Among them, the functional output circuit is a combinational logic circuit. The target output interface functional path is the output interface functional path that needs to be tested. It should be noted that there are usually multiple paths in the functional output circuit. If based on each output interface functional path, a large number of test vectors need to be generated, but in fact not every output interface functional path needs to be tested. By obtaining the target output interface functional path list, the generation of test vectors can be greatly reduced, and the efficiency of memory output interface functional path testing can be improved. In an embodiment of the present invention, the memory can specifically be a random access memory (Random Access Memory, referred to as RAM) or a read-only memory (Read-Only Memory, ROM). The input interface of the RAM includes a data input interface and an address input interface, and the input interface of the ROM only includes an address input interface.

[0019] Step S2: The automatic test vector generation tool selects at least one target output interface function path from the target output interface function path list, and automatically generates a test vector based on the selected target output interface function path.

[0020] It should be noted that the automatic test vector generation tool can select one or more target output interface functional paths for each test. In order to improve test efficiency, one test can cover as many target output interface functional paths as possible.

[0021] Step S3: input the generated test vector into the memory through the MBIST input circuit connected to the memory input interface.

[0022] Among them, the MBIST input circuit is a circuit integrated inside the chip for testing semiconductor memory.

[0023] Step S4: Create a conversion at the output interface through the selected target output interface functional path, capture target output data, and compare the target output data with the preset value. If they are consistent, the test passes; otherwise, the test fails.

[0024] It should be noted that since the test target is the output interface functional path, a transition needs to be created on the memory output interface. During the memory output interface functional path test, the ATPG tool is instructed to control the memory input interface through the MBIST input circuit. However, the data read from the memory is captured through the functional output circuit, which helps reduce the overall pattern generation required to observe faults. In addition, all test paths pass through the memory, allowing the test paths to run at the required operating frequency of the memory, achieving full-speed testing and thus increasing the chip operating frequency.

[0025] The embodiment of the present invention selects the MBIST input circuit as the current input circuit and the functional output circuit as the current output circuit. That is, when performing a memory output interface functional path test, the input of the memory is controlled by the MBIST input circuit, and data in the memory is obtained by the functional output circuit. The output interface functional path in the functional output circuit is tested, and the test path all passes through the memory, so that the test path runs at the required operating frequency of the memory, achieving full-speed testing, thereby improving the chip operating frequency.

[0026] As an embodiment, the step S4 includes:

[0027] Step S5: Determine whether all target output interface function paths in the target output interface function path list have been tested. If so, end the process; otherwise, return to step S2.

[0028] As an embodiment, step S1 includes:

[0029] Step S11: Obtain the delay of each output interface functional path in the functional output circuit based on a static timing analysis tool.

[0030] Step S12: Arrange the delays of all output interface functional paths in descending order.

[0031] Step S13: Determine the first N preset output interface functional paths as target output interface functional paths.

[0032] Specifically, the top Y% of output interface functional paths can be determined as the top N preset output interface functional paths, where Y can be set to 10 or 20, for example. A latency threshold can also be set, and output interface functional paths exceeding the latency threshold can be determined as the top N preset output interface functional paths. It should be noted that the target output interface functional paths are the output interface functional paths that need to be tested. By screening the target output interface functional paths, output interface functional paths that do not need to be tested can be filtered out in advance, reducing the number of subsequent test vectors generated and improving the efficiency of output interface functional path testing.

[0033] Step S14: input all target output interface function paths into an automatic test vector generation tool to generate a target output interface function path list.

[0034] As an embodiment, step S3 includes:

[0035] Step S31: Based on the MBIST input circuit, a first address is input through the address input interface of the memory, a first value is input through the data input interface of the memory, and the first value is written into the first address of the memory.

[0036] It should be noted that the first address in the memory is initialized through step S31.

[0037] Step S32, based on the MBIST input circuit, input the second address through the address input interface of the memory, input the second numerical value through the data input interface of the memory, write the second numerical value in the second address of the memory, wherein the first address and the second address are different addresses, and the first numerical value and the second numerical value are different numerical values.

[0038] It should be noted that, in step S32, the second address of the memory is initialized. The first value is set to 1, the second value is set to 0, or the first value is set to 0, the second value is set to 1.

[0039] As an embodiment, step S4 includes:

[0040] Step S41: Read data from a first address through the output interface based on the selected target output interface functional path, and initialize the output interface.

[0041] Step S42: Read data from the second address through the output interface based on the selected target output interface functional path, create a conversion at the output interface, and use the data read from the second address as target output data.

[0042] Step S43: Compare the target output data with a preset value, where the preset value is a second value. If they are consistent, the test passes; otherwise, the test fails.

[0043] It should be noted that if the selected target output interface functional path has a fault, then the test fails if data read from the second address through the output interface based on the selected target output interface functional path is not equal to the second value. If the selected target output interface functional path does not have a fault, then the test passes if data read from the second address through the output interface based on the selected target output interface functional path is equal to the second value.

[0044] As an embodiment, the memory further includes a memory enabling interface, and the method further includes:

[0045] Step S10: In the loading phase (Scan Shift) of the test vector of the scan test, the scan enable signal is at the level of the loading mode, and the memory enable interface is always set to an invalid level so that the memory does not work.

[0046] It should be noted that during the test vector loading phase of the scan test, the memory enable interface is always set to an invalid level so that the memory does not work, so that the memory does not work during the test vector loading phase of the scan test, thereby ensuring the stability of the data stored in the memory.

[0047] Step S20, in the response data capture stage (Scan Capture) of scan test, the scan enable signal is the level of capture mode, and the memory enable interface is controlled by MBIST input circuit to be the effective level of memory normal operation in the memory operation period, and when the memory enable interface is the effective level of memory normal operation, memory can be read and write.

[0048] It should be noted that steps S1 to S4 are executed during the response data capture phase of the scan test.

[0049] As an embodiment, a first enable control circuit can be set in the chip test circuit to control the memory enable interface. The first enable control circuit can be implemented by a simple combination of logic devices to reduce circuit cost. The following two specific implementation methods are used to illustrate this.

[0050] Implementation Method 1:

[0051] The level of described loading mode is a high level, and the level of described capture mode is a low level. The first enable control circuit comprises a first NOT gate and a first AND gate. The MBIST input circuit is connected to the first input pin of the first NOT gate. The scan enable signal is connected to the input pin of the first NOT gate. The output pin of the first NOT gate is connected to the second input pin of the first AND gate. The first AND gate single output pin is connected to the memory enable interface.

[0052] When the scan enable signal is high, it is flipped to a low level through the first NOT gate and serves as an input of the first AND gate, so that when the scan enable signal is high, the output of the first AND gate must be low, thereby setting the memory enable interface to always be low.

[0053] When the scan enable signal is at a low level, it is flipped to a high level through the first NOT gate and serves as an input of the first AND gate. At this time, the output of the first AND gate is completely controlled by another input, that is, controlled by the MBIST input circuit, and can be controlled according to specific operation requirements.

[0054] Implementation Method 2:

[0055] The level of described loading mode is a high level, and the level of described capture mode is a low level, described first enable control circuit comprises the second NOT gate and the first OR gate, the MBIST input circuit is connected to each other with the first input pin of the first OR gate, the scan enable signal is connected to each other with the second input pin of the first OR gate, the output pin of the first OR gate is connected to each other with the input pin of the second NOT gate, and the output pin of the second NOT gate is connected to each other with the memory enable interface.

[0056] When the scan enable signal is at a high level, the output of the first OR gate is definitely at a high level, and after being flipped through the second NOT gate, it is definitely at a low level, thereby setting the memory enable interface to always be at a low level.

[0057] When the scan enable signal is at a low level, the output of the first OR gate is completely controlled by another input, that is, controlled by the MBIST input circuit, and can be controlled according to specific operation requirements.

[0058] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0059] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0060] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0061] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for testing a memory output interface functional path, comprising: Step S1: obtaining a target output interface functional path in a functional output circuit connected to a memory output interface, and generating a target output interface functional path list; Step S2: The automatic test vector generation tool selects at least one target output interface function path from the target output interface function path list, and automatically generates a test vector based on the selected target output interface function path; Step S3, the generated test vector is input into the memory by the MBIST input circuit connected to the memory input interface; Step S4: Create a conversion at the output interface through the selected target output interface functional path, capture target output data, and compare the target output data with the preset value. If they are consistent, the test passes; otherwise, the test fails.

2. The method according to claim 1, characterized in that The step S4 then includes: Step S5: Determine whether all target output interface function paths in the target output interface function path list have been tested. If so, end the process; otherwise, return to step S2.

3. The method according to claim 1, characterized in that The step S1 comprises: Step S11: Obtaining the delay of each output interface functional path in the functional output circuit based on a static timing analysis tool; Step S12: Arrange the delays of all output interface function paths in descending order; Step S13: Determine the first N preset output interface function paths as target output interface function paths; Step S14: input all target output interface function paths into an automatic test vector generation tool to generate a target output interface function path list.

4. The method according to claim 1, wherein The step S3 comprises: Step S31, based on the MBIST input circuit, inputting a first address through the address input interface of the memory, inputting a first value through the data input interface of the memory, and writing the first value into the first address of the memory; Step S32, based on the MBIST input circuit, input the second address through the address input interface of the memory, input the second numerical value through the data input interface of the memory, write the second numerical value in the second address of the memory, wherein the first address and the second address are different addresses, and the first numerical value and the second numerical value are different numerical values.

5. The method according to claim 4, characterized in that The step S4 comprises: Step S41: Read data from a first address through the output interface based on the selected target output interface functional path, and initialize the output interface; Step S42: Read data from the second address through the output interface based on the selected target output interface functional path, create a conversion at the output interface, and use the data read from the second address as target output data; Step S43: Compare the target output data with a preset value, where the preset value is a second value. If they are consistent, the test passes; otherwise, the test fails.

6. The method according to claim 1, characterized in that The memory is a random access memory or a read-only memory.

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 6.

Images