A test scheme for evaluating data retention performance of NOR-type flash memory

Abstract

The application provides a test scheme for checking data retention performance of NOR type Flash memory, focuses on the influence of erase-write cycles on the data retention performance, unifies the erase-write cycle number of the Flash memory test, stipulates clear temperature selection criteria, provides a reference for the Flash memory related test, and comprises the following steps: step one: determining the basic test algorithm of the NOR type Flash memory as the Checkerboard algorithm from the algorithm design complexity and the fault coverage; step two: improving the Checkerboard algorithm process and determining the data retention fault determination step; step three: carrying out a pre-experiment to determine the data retention performance test temperature, erase-write number and sample number of the NOR type Flash memory; step four: determining the erase-write number of the data retention test at normal temperature and the sample number under each erase-write number; step five: determining the test pattern, failure criterion, test duration and test cycle; step six: carrying out the data retention test combined with the erase-write cycle based on the non-replacement timing truncation test; and step seven: test data processing, fitting the average failure time under different erase-write numbers with the erase-write number to obtain the corresponding relationship between the average failure time and the erase-write number.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit quality and reliability testing, in particular to a test scheme for evaluating the data retention performance of NOR type flash memory, and belongs to the field of memory use reliability evaluation. BACKGROUND

[0002] Memory is almost ubiquitous in electronic devices. However, the floating gate structure design also brings unavoidable problems in memory reliability. The most prominent one is that before writing new data, the memory must perform an erase operation to restore each storage cell to an unprogrammed state before writing new data, which seriously affects the write speed, and in addition, repeated erasing and writing will also cause the data retention performance of the memory to decline.

[0003] For memory, reliability refers to the accuracy and integrity of the data it stores, mainly including endurance and data retention. In the use of memory, the most important working scenarios that cause reliability problems are erase-write cycles and data retention, in addition to write interference and read interference.

[0004] Because the memory must perform an erase operation before writing new data, it cannot directly write new data based on the original data. In the memory erase-write process, whether using the hot electron injection principle or the tunneling principle, electrons need to pass through the oxide layer barrier, which will cause damage to the oxide layer. With the increase of erase-write cycle times, the damage to the oxide layer material accumulates, eventually causing the number of charges entering the storage cell to fluctuate greatly when storing data, making the threshold voltage value distribution become scattered, and thus increasing the possibility of errors during data retention and reading.

[0005] During the data retention process of the memory, the reliability problem that is prone to occur is that as the data retention time increases, the charges in the storage cell gradually leak and diffuse, eventually causing errors when reading data. The more data stored in the memory, the longer the data is stored, the more likely this problem occurs. In this process, as the charges in the storage cell leak, the threshold voltage will show a trend of gradually decreasing.

[0006] The main effect of read interference and write interference on the data retained in the memory is that when the read and write voltages are applied, a weak electric field will also appear in the oxide layer, causing a small amount of channel electrons to enter the storage medium, eventually causing data errors. In addition, the storage layer of the floating gate structure may also have coupling crosstalk, causing miswriting to occur.

[0007] Due to the above reliability problems, the reliability indicators of the memory are mainly the endurance and the data retention. The endurance refers to the ability of the memory to have a certain storage window after a plurality of erase-write cycles, that is, the threshold voltage distribution after writing data cannot be too dispersed, and the memory is usually required to have 100,000 times of erasable-write times at room temperature. The data retention refers to the ability of the memory to keep the data reading result unchanged after a period of time under certain environmental conditions, and the memory is usually required to keep the data for 10 years without reading error at room temperature, and some high-reliability devices are required to keep the data for a certain period of time at 55 DEG C.

[0008] According to different internal architectures, the memory can be divided into NAND, NOR, AND and Ni-NOR, etc. The NOR structure proposed by Intel in 1988 and the NAND structure proposed by Toshiba in 1989 are the two most important memories in the market. According to the different characteristics of the two memories, their application scenarios are also different. The NOR type Flash memory should be selected in the occasion of requiring small capacity, fast reading speed and code access, and the NAND type Flash memory should be selected in the occasion of requiring large capacity, low storage cost and fast erasing and writing. Therefore, the NOR type Flash memory has a more stringent requirement on reliability than the NAND type Flash memory, and the NAND type Flash memory is superior to the NOR type Flash memory in capacity and cost.

[0009] At present, the memory related test standards used at home and abroad all require high temperature for acceleration in the data retention test, but there is no specific temperature selection criterion. In addition, whether to perform the erase-write cycle and the number of times of the erase-write cycle are not uniform, so it is necessary to propose a memory test scheme with a specific temperature selection criterion, a unified regulation of whether to perform the erase-write cycle and the number of times of the erase-write cycle.

[0010] The present application mainly aims at the NOR type Flash memory, focuses on the influence of the erase-write cycle on the data retention performance, unifies the number of times of the erase-write cycle of the memory test, and provides a reference for the memory related test. SUMMARY

[0011] 1. Object: In view of the deficiencies of the prior art, the present application provides a test scheme for evaluating the data retention performance of the memory.

[0012] 2. Technical scheme:

[0013] The application mainly aims at NOR type Flash memory, focuses on the influence of erase-write cycle on data retention performance, unifies the erase-write cycle number of memory test, and provides a reference for memory related test by specifying the temperature selection criteria.

[0014] The application provides a test scheme for evaluating the data retention performance of NOR type Flash memory, which comprises the following steps:

[0015] Step 1: From the algorithm design complexity and fault coverage, the basic test algorithm of the NOR type memory is determined as algorithm.

[0016] Step 2: The algorithm flow is improved to determine the data retention fault determination step; in the erase-write process, all write data "0" is selected, and the erase-write number can be selected as different numbers as needed. The data writing and verification need to be performed after the end of the erase-write cycle.

[0017] The test pattern is written, and the first reading of data is to verify whether the data is normally written. If data error occurs in this step, it may be one of the fixed fault, flip-flop fault, write interference fault and coupling fault, but not the data retention fault.

[0018] The second reading of data after the data retention test is to verify whether the normally written data appears a fault. If data error occurs in this step, the detected fault can be considered as the data retention fault.

[0019] Step 3: The pre-test is carried out to determine that the data retention performance test temperature of the NOR type Flash memory is 85°, 125° and 150°, and the erase-write number is 10 and 500 times respectively; each group of samples is 3, and the total number of samples is 18; during the pre-test, the stored data of each device is read and compared with the initially written data every 100 hours. If the data retention fault occurs in the first device at a certain test temperature and the remaining functions are normal, the temperature is selected as the data retention test temperature.

[0020] Step 4: The erase-write number of the data retention test at room temperature is determined as 10, 1000, 10000, 30000 and 50000 times respectively, and the number of samples under each erase-write number is 4, and the total number of samples is 20.

[0021] Step 5: The test pattern, failure criterion, test duration and test cycle are determined; the all "0" pattern should be used for writing during the erase-write cycle, and the data retention fault should be written. The test duration is set to 1000 hours, and the test is selected every 20 hours.

[0022] Step six: based on the non-replacement timing truncation test, the data retention test combined with the erase-write cycle is carried out; according to the improved algorithm process, the memory after the erase-write cycle is written with the test pattern, and the written data is saved for subsequent data read verification. After writing the test pattern, before the data retention test, a data read verification is required to confirm whether the memory is in a normal working state, if some individual failures of some units occur, the failure address should be recorded and excluded in the subsequent data retention failure record, if the entire memory cannot write data, the data retention test of the device is no longer carried out. After completing the erase-write cycle, all devices are placed in a 150 DEG C oven for data retention test.

[0023] For the devices that can pass the data retention test in the previous step, they are placed in a 150 DEG C environment for 1000 hours, and every 20 minutes, the data in them is read for verification, and the unit address of the data retention failure is recorded, and the address that has been recorded is not recorded repeatedly.

[0024] Step seven: test data processing, the average failure time under different erase-write times is calculated and data fitting is carried out with the erase-write times, to obtain the corresponding relationship between the average failure time and the erase-write times.

[0025] 3. Advantages and effects:

[0026] The present application provides a test scheme for evaluating the data retention performance of NOR type flash memory, which has the following advantages:

[0027] (1) The data retention test is accelerated by using high temperature, and the exact temperature selection criteria are specified;

[0028] (2) The erase-write cycle must be carried out before the data retention test, and the number of times of the erase-write cycle is specified, which can investigate the influence of the erase-write cycle on the data retention performance;

[0029] (3) The NOR type flash memory data retention performance test scheme combined with the erase-write cycle disclosed by the present application includes the determination of the failure test algorithm, the test flow, the test temperature, the test pattern and the test data processing method, which can be used for testing the memory and making up for the shortcomings of the existing test methods. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to the specific embodiments of the present application and in combination with the drawings.

[0031] Figure 1 It is a test scheme flow chart for evaluating the data retention performance of NOR type flash memory;

[0032] Figure 2 is an improved algorithm test flow chart;

[0033] Figure 3 is a data retention test flow chart combined with a write-erase cycle. Embodiments:

[0034] The application will be further described below in connection with specific embodiments so that those skilled in the art can better understand the application and implement it. The embodiments are not intended to limit the application.

[0035] The application provides a test scheme for evaluating the data retention performance of a NOR type Flash memory, a flow chart of which is shown in Figure 1 The specific implementation steps are as follows:

[0036] The test scheme for evaluating the data retention performance of a NOR type Flash memory comprises the following steps:

[0037] Step 1: Determine the basic test algorithm of the memory. Analyze the memory failure modes, determine the memory test algorithm selection principle from the aspects of algorithm design complexity and failure coverage rate, and determine the memory data retention failure test algorithm as Algorithm 1.

[0038] Start from the common failures of the memory, analyze the manifestation of each failure. In the process of using the memory, the common failures of the memory array are mainly data retention failure, fixed failure, flip-flop failure, write interference failure and coupling failure. Analyze the commonly used memory test algorithms such as Algorithm 1, Algorithm 2, Algorithm 3 and Algorithm 4.

[0039] Algorithm 1, also known as all 0 / all 1 method, detects by full scanning programming and data verification of the memory.

[0040] Algorithm 2 is also known as the wandering algorithm. In the test process, only one memory cell is written with "1", and the address written with "1" is constantly increasing. The data "1" will wander through every memory cell.

[0041] Algorithm 3, also known as the chessboard algorithm, writes opposite data to all adjacent memory cells in the test process. The specific test process is to first perform full chip data erase, then write opposite data to each cell compared with adjacent cells, and finally perform data read verification. If there is a difference between the data, it indicates that the memory has a functional failure.

[0042] The advantage of the algorithm is that it can detect a variety of cell faults and partial coupling faults with less time cost and design cost, and the disadvantage is that it is powerless for more complex coupling faults. The algorithm can be used to detect data retention faults, fixed faults, transition faults and coupling faults of partial adjacent memory cells.

[0043] The algorithm is an algorithm for reading, writing and erasing operations on all addresses of the memory cells using a finite state machine. By arranging and combining the reading, writing and erasing operations and repeating the loop, almost all coupling faults are covered.

[0044] The advantage of the algorithm is that the coverage rate of coupling faults is high and the time complexity of the algorithm is lower than that of the algorithm, but the disadvantage is that the algorithm has many types and high design complexity, and since the original algorithm is proposed for memory testing, some operations such as writing 1 operation on a cell are not suitable for memory. In addition, since the algorithm has multiple erase and write operations on the memory cells during execution, it will refresh the internal charge of the memory cells, so it is not suitable for detecting data retention faults. The algorithm can be used to detect fixed faults, transition faults and most coupling faults.

[0045] The time complexity of the above four algorithms is shown in Table 2, where n represents the number of loops in the algorithm. It can be seen that under the same memory capacity to be tested, the algorithm and the algorithm require the lowest time cost, the algorithm is in the middle, and the algorithm requires the most time.

[0046] Table 2 Comparison of time complexity of each algorithm

[0047]

[0048] The fault coverage of the above four algorithms is shown in Table 3. It can be seen that the main advantage of the algorithm and the algorithm is concentrated in the test of coupling faults, and the algorithm is applicable to faults other than coupling faults.

[0049] Table 3 Fault coverage of each algorithm

[0050]

[0051] Considering the time complexity and fault coverage, the algorithm is selected as the basic test algorithm and is improved for the performance test of NOR type Flash memory considering the number of erase and write operations.

[0052] Step two: improve the algorithm flow, determine the data retention fault discrimination step. In the process of erase and write, select all write data "0", the number of erase and write, can be selected according to the needs of different number. Data write and verification need to be carried out after the end of the erase and write cycle. Write test pattern, the first reading data is to verify whether the data is normally written, if the data error occurs in this step of verification, it is possible that one of the fixed fault, flip fault, write interference fault and coupling fault, but not the data retention fault.

[0053] The second reading data after the data retention test is to verify whether the normally written data has a fault, if the data error occurs in this step of verification, the detected fault can be considered as the data retention fault.

[0054] The improved test algorithm flow is shown in Figure 2 , wherein the number of erase and write is artificially set, and different number can be selected according to the test needs.

[0055] In the process of erase and write, the selection of all write data "0" is because the state of the memory after erasing is the state of data "1", and only all write 0 can be applied to each single to the stress of erase and write cycle.

[0056] After the end of the erase and write cycle, write test pattern, the first reading data is to verify whether the data is normally written, if the data error occurs in this step of verification, it is possible that one of the fixed fault, flip fault, write interference fault and coupling fault, but not the data retention fault which is the main concern of the research.

[0057] The second reading data after the data retention test is to verify whether the normally written data has a fault, if the data error occurs in this step of verification, the detected fault can be considered as the data retention fault.

[0058] Step three: determine the data retention performance test temperature of the memory through pretest. In order to determine the retention temperature required by the data retention test, and achieve the purpose of saving time cost as much as possible on the premise of not changing the data retention failure mechanism of the memory, pretest is carried out. The test temperatures are 85°, 125° and 150°, and each test temperature is divided into two groups according to different number of erase and write, and the number of erase and write is 10 times and 500 times respectively. The number of samples of each test group is 3, and the total number of test samples is 18.

[0059] The pretest conditions are set as shown in Table 2.

[0060] Table 2 pretest condition setting

[0061]

[0062] During the pre-test, the data stored in each device is read every 100 hours and compared with the data initially written. If the first device fails in data retention at a certain test temperature and the remaining devices function normally, the temperature is selected as the data retention test temperature.

[0063] In this embodiment, the memory 2516 is selected, and specifically, after 500 hours of data retention, only at 150°C does a data retention failure occur, and the remaining functions are normal, so 150°C is selected as the data retention test temperature.

[0064] Step four: Determine the number of erase-write cycles for the data retention test and the number of samples at each erase-write cycle. According to different erase-write cycles at room temperature, the erase-write cycles are divided into 10, 1000, 10000, 30000, and 50000. Four samples are selected for each erase-write cycle. The erase-write cycle is the main factor affecting data retention performance. The more levels selected, the more accurate the final results. Generally, the number of levels is not less than 4.

[0065] The maximum number of erase-write cycles that the current memory can perform is generally 100,000 times, but considering the actual use process, it is generally not performed so many times.

[0066] At the same time, when the erase-write performance of the memory is tested, there are fewer memories that can still work normally after more than 50,000 erase-write cycles, so the maximum number of erase-write cycles is selected as 50,000.

[0067] In this embodiment, the memory 2516 is selected, and specifically, the erase-write cycles are divided into 10, 1000, 10000, 30000, and 50000. Generally, the number of devices for accelerated testing under a single stress should not be less than 3, and in this embodiment, the memory 2516 is selected, and specifically, four samples are selected for each erase-write cycle.

[0068] Step five: Determine the test pattern, failure criterion, test duration, and test cycle. During the erase-write cycle, the full "0" pattern should be used for writing, and the data retention failure should be written in the pattern.

[0069] The test duration is set to 1000 hours, and testing is performed every 20 hours. In order to affect all memory cells with erase-write cycles, the full "0" pattern should be used for writing during the erase-write cycle; during the data retention process, in order to better trigger the data retention failure, the pattern should be written.

[0070] During the test, when the read data is inconsistent with the written data, it is considered to be a failure. The specific failure reason analysis and test data processing should be performed after the entire test is completed and the evaluation process is entered.

[0071] According to the requirements of data retention time length in each standard and the pre-test results, the test time length is set to 1000 hours. Because the time of memory failure cannot be accurately measured, the periodic test method is adopted. Considering that the temperature acceleration stress is large at 150°C, data verification should be performed at a shorter time interval to ensure the accuracy of the measured data. One test is performed every 20 hours.

[0072] Step six: Perform data retention test combined with erase-write cycle. Randomly select 20 devices and randomly divide them into five groups, four in each group. The five groups of devices are subjected to 10, 1000, 10000, 30000, and 50000 erase-write cycles, respectively. The erase-write cycle refers to the process performed according to the improved algorithm flowchart ( Figure 2 ).

[0073] Data writing and verification refers to writing test patterns to the memory after erase-write and saving the written data for subsequent data read verification according to the algorithm flowchart ( Figure 2 ). After writing the test patterns, a data read verification is performed before the data retention test to confirm whether the memory is in a normal working state. If some individual failures occur in certain cells, the failure addresses should be recorded and excluded from the subsequent data retention failure records. If the entire memory cannot write data, the device will no longer be subjected to data retention test.

[0074] Data retention test refers to placing the devices that have passed the previous verification and can be subjected to data retention test in a 150°C environment for 1000 hours. Every 20 hours, the data is read and verified, and the addresses of the cells that have experienced data retention failure are recorded. The addresses that have been recorded will not be recorded again.

[0075] After completing the erase-write cycle, all devices are placed in an oven for data retention test. In this embodiment, the selected memory 2516 is subjected to a data retention test at a temperature of 150°C. The performance retention test conditions are shown in Table 3.

[0076] Table 3 Summary of Performance Retention Test Conditions

[0077]

[0078] During the data retention test, data verification is performed on all devices every 20 hours, and the addresses that have experienced data changes are recorded. During data recording, the same address in the same memory that has experienced data errors will not be recorded repeatedly. If a certain address in the memory fails three data verifications and the error does not disappear during subsequent data verification, it is considered that the memory has experienced data retention failure.

[0079] The memory 2516 selected in this embodiment, specifically, the data retention test flow combined with the write-erase cycle is as shown in Figure 3

[0080] Step seven: test data processing. The test is selected as a non-replacement timing truncated test. The average failure time under different write-erase cycles is calculated and fitted with the write-erase cycles to obtain the relationship between them.

[0081] The test data of each group is processed respectively. Since the storage unit that has a data retention failure no longer performs data writing, it can be regarded as a non-replacement timing truncated test. The average failure time under different write-erase cycles is calculated. Then, the average failure time is fitted with the write-erase cycles to obtain the relationship between them.​

Claims

1. A test method for evaluating the data retention performance of NOR flash memory, comprising the following steps: Step S1: Based on both algorithm design complexity and fault coverage, the basic testing algorithm for NOR Flash memory is determined to be the Checkerboard algorithm; Step S2: Improve the Checkerboard algorithm process and determine the steps for identifying data retention failures; Step S3: Conduct preliminary tests to determine the data retention performance of NOR Flash memory. The test temperatures are 85°C, 125°C, and 150°C, and the number of erase / write cycles are 10 and 500, respectively. There are 3 samples in each group, for a total of 18 samples. Step S4: Determine the number of erase / write cycles for the data retention test at room temperature as 10, 1000, 10000, 30000 and 50000 cycles, with 4 samples for each erase / write cycle, for a total of 20 samples; Step S5: Determine the test pattern, failure criteria, test duration, and test cycle; Step S6: Based on the no-replacement timed truncation test, conduct a data retention test combined with erase-write cycles; Step S7: Experimental data processing. The average failure time calculated under different erase / write cycles is fitted with the number of erase / write cycles to obtain the correspondence between the average failure time and the number of erase / write cycles. In step S2, during the erase / write process, select to write all data "0". The number of erase / write cycles can be selected as needed. Checkerboard data writing and verification should be performed after the erase / write cycle ends. Write the test pattern to the Checkerboard. The first data read is to verify whether the data is written normally. If a data error occurs in this verification step, it is one of the following: fixation failure, flip failure, write interference failure, and coupling failure, rather than a data retention failure. The second data read after the data retention test is to verify whether the normally written data has failed. If a data error occurs in this verification step, the detected fault is considered a data retention failure. During the preliminary test, the data stored in each device is read and compared with the data initially written every 100 hours. If a device fails to retain data for the first time at a certain test temperature while other functions are normal, then that temperature is selected as the data retention test temperature. In step S5, the write operation should be performed using a pattern of all "0"s during the write cycle. To trigger a data retention fault, the write operation should be performed using a checkerboard pattern. The test duration is set to 1000 hours, and a test is performed every 20 hours.

2. The test method for evaluating the data retention performance of NOR Flash memory according to claim 1, characterized in that: In step S6, according to the improved Checkerboard algorithm flow, the Checkerboard test pattern is written to the Flash memory after erasing and writing, and the written data is saved for subsequent data reading verification. After writing the test pattern, before the data retention test, a data reading verification is required to confirm whether the Flash memory is in normal working condition. If a single cell fails, the fault address should be recorded and removed from the subsequent data retention fault record. If the entire memory cannot be written to, the data retention test will not be performed on the memory. After completing the erase and write cycle, all devices are placed in a 150°C oven for the data retention test. For devices that have completed the previous verification and are undergoing data retention testing, place them at 150°C for 1000 hours. Remove them every 20 hours, read the data, and verify the data retention. Record the cell address where the data retention failure occurred, and do not repeat the recorded address.

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