Double-core stacked substrate packaging method and structure

Abstract

The invention relates to the technical field of chip packaging, and discloses a double-core stacked substrate packaging method, which comprises the following steps of: S100, arranging a plurality of preset positions on the top surface of a packaging substrate, and arranging a plurality of conductive connecting columns and outer circuits electrically connected with the conductive connecting columns on the peripheral sides of the preset positions; s200, mounting a first chip at the preset position on the top surface of the packaging substrate, wherein the first chip is electrically connected with the outer-layer circuit; s300, arranging heat-conducting glue on the top surface of the first chip; s400, a second chip is mounted on the top face of the heat-conducting glue, the bottom face of the second chip abuts against the conductive connecting columns, and the second chip is in signal conduction with the first chip through the conductive connecting columns and the outer layer circuit; and S500, filling the mounting areas of the first chip and the second chip with a plastic package member to complete packaging. The heat-conducting glue in the designed structure can absorb redundant heat and balance heat generated by the two chips, and the chips are prevented from being damaged due to heat accumulation.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a dual-core stacked substrate packaging method and structure. Background Art

[0002] With the development of the times, our lives are inseparable from semiconductors, whether it is electronic watches, mobile phones, computers or cars. Even the research and development of precision instruments cannot be separated from the development of semiconductors. At present, electronic products tend to be miniaturized and lightweight, and the performance requirements of products are gradually increasing. At this stage, the production capacity of high-end chips is limited, and the cost of high-end chips also reduces the profits of end customers. In this context, the application of chip flip-chip stacking technology is born, but the traditional chip stacking technology not only requires high-precision secondary flip-chip bonding, but also the huge amount of heat accumulation during the operation of the two chips after packaging will reduce the signal transmission speed, and may also cause electromigration, shortening the service life of the chip devices in the package.

[0003] Therefore, reducing the heat accumulation caused by chip stacking has become an urgent problem to be solved. Summary of the invention

[0004] The main purpose of the present invention is to provide a dual-core stacked substrate packaging method, including steps S100: a plurality of preset positions are provided on the top surface of the packaging substrate, and a plurality of conductive connecting columns and outer layer circuits electrically connected to the conductive connecting columns are provided around the preset positions; S200: a first chip is mounted on the preset positions on the top surface of the packaging substrate, and the first chip is electrically connected to the outer layer circuit; S300: a thermal conductive adhesive is provided on the top surface of the first chip; S400: a second chip is mounted on the top surface of the thermal conductive adhesive, and the bottom surface of the second chip abuts against the conductive connecting columns, and the second chip is connected to the first chip signal through the conductive connecting columns and the outer layer circuit; S500: a plastic package is filled in the mounting area of ​​the first chip and the second chip to complete the packaging.

[0005] Preferably, in step S100, the packaging substrate includes several layers of carrier boards, a plurality of signal via holes are arranged on the carrier boards, copper plating is performed in the signal via holes, and the carrier boards are stacked so that the signal via holes of two adjacent carrier boards are correspondingly connected.

[0006] Preferably, in step S100, the preset position and the outer layer circuit are set on the surface of the carrier board located at the top layer, the outer layer circuit is used for signal conduction between the conductive connecting column and the first chip in the preset position, and the conductive connecting column is connected to the signal conduction hole.

[0007] Preferably, step S110 is further included between step S100 and step S200: after the first chip pads are ball-planted, a plurality of the first chips are arranged on the same strip carrier, and each of the first chips is pasted to a corresponding preset position through the strip carrier driven by a patch device.

[0008] Preferably, step S120 is also included between step S100 and step S200: a plurality of first partitions are divided on the packaging substrate, at least one of the preset positions is located in the first partition, at least one first target is provided in the first partition, and the first target is used for positioning when the bonding equipment bonds the first chip to the preset position.

[0009] Preferably, step S310 is also included between step S300 and step S400: laying multiple layers of dry film on the outer circuit according to the height of the conductive connecting column, cutting and exposing the dry film to form a printed pattern of the conductive connecting column, and developing the unexposed part of the printed pattern and then performing multi-layer electroplating to obtain the conductive connecting column.

[0010] Preferably, step S320 is further included between step S300 and step S400: leveling the tops of all the conductive connection posts and applying a dry film, and removing the dry film with an organic film stripping liquid after curing, so that the top end faces of all the conductive connection posts remain on the same plane.

[0011] Preferably, step S330 is further included between step S300 and step S400: after printing a tin layer on the top of the conductive connection column, the second chip is attached to the thermal conductive adhesive, and the tin layer is attached to the bottom surface of the second chip.

[0012] Preferably, in step S400, the packaging substrate is divided into a plurality of second partitions, at least one of the first chips is located in the second partition, at least one second target is provided in the second partition, and the second target is used for positioning when the mounting equipment mounts the second chip to the top surface of the first chip, and the number of the second partitions is greater than the number of the first partitions.

[0013] The present invention also provides a dual-core stacked substrate packaging structure, comprising: a packaging substrate, comprising at least one layer of carrier board, the carrier board being provided with a plurality of preset positions for installing chips; at least two conductive connecting pillars being arranged around the preset positions; a first chip being arranged in the preset positions, the first chip being electrically connected to the conductive connecting pillars, and the top surface of the first chip being provided with thermal conductive adhesive; a second chip being attached to the thermal conductive adhesive, the bottom surface of the second chip being aligned and abutted against the conductive connecting pillars, and the second chip being electrically connected to the first chip through the conductive connecting pillars.

[0014] In the technical solution provided by the present invention, the second chip is stacked with the first chip through the conductive connecting column, which greatly reduces the planar area of ​​the packaged chip components. At the same time, the double cores are filled with thermal conductive glue, which can absorb excess heat and balance the heat generated by the two chips, preventing the first chip in the lower layer from being damaged due to overheating, and the heat can also be released through the second chip, which greatly improves the reliability and avoids the heat accumulation effect affecting the operation of the packaged chip; the first chip and the second chip are connected and conducted by signals and interconnected in functions through the conductive connecting column and the circuit on the packaging substrate, and at the same time, the thermal conductive glue is prevented from expanding and cooling due to heat, causing the gap between the first chip and the second chip to become larger, affecting the fit between the thermal conductive glue and the chip, thereby reducing the thermal conductivity effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and the figures in the drawings do not constitute proportional limitations unless otherwise stated.

[0016] Figure 1 A schematic diagram of a process of an embodiment of a dual-core stacking substrate packaging method of the present invention;

[0017] Figure 2 A schematic diagram of the structure of the processing process of an embodiment of a dual-core stacked substrate packaging structure of the present invention;

[0018] Figure 3 A schematic diagram of the structure of the processing process of an embodiment of a dual-core stacked substrate packaging structure of the present invention;

[0019] Figure 4 A schematic diagram of the structure of the processing process of an embodiment of a dual-core stacked substrate packaging structure of the present invention;

[0020] Figure 5 A schematic diagram of the structure of the processing process of an embodiment of a dual-core stacked substrate packaging structure of the present invention;

[0021] Figure 6 It is a structural schematic diagram of an embodiment of a dual-core stacked substrate packaging structure of the present invention;

[0022] Figure 7 It is a schematic diagram of the top view of the structure of an embodiment of a dual-core stacked substrate packaging structure of the present invention during processing.

[0023] In the figure: 1. packaging substrate; 11. carrier board; 111. signal via; 112. preset position; 113. first partition; 1131. first target; 114. second partition; 1141. second target; 2. conductive connecting column; 3. first chip; 31. solder ball; 4. second chip; 5. thermal conductive adhesive; 6. printing mold; 7. plastic package; 8. strip carrier. DETAILED DESCRIPTION

[0024] In order to facilitate the understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on another element, or there can be one or more centered elements therebetween. When an element is described as "connected" to another element, it can be directly connected to another element, or there can be one or more centered elements therebetween. The terms "vertical", "horizontal", "left", "right", "inside", "outside" and similar expressions used in this specification are only for illustrative purposes. In the description of the present invention, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features; the meaning of "multiple" is two or more. The term "include" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof may be present or added.

[0025] In addition, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two components. All technical and scientific terms used in this specification have the same meaning as those generally understood by technicians in the technical field of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0026] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] The main purpose of the present invention is to provide a dual-core stacked substrate packaging method, including steps S100: a plurality of preset positions 112 are provided on the top surface of the packaging substrate 1, and a plurality of conductive connecting columns 2 and outer-layer circuits electrically connected to the conductive connecting columns 2 are provided around the preset positions 112; S200: a first chip 3 is mounted on the preset positions 112 on the top surface of the packaging substrate 1, and the first chip 3 is electrically connected to the outer-layer circuit; S300: a thermal conductive adhesive 5 is provided on the top surface of the first chip 3; S400: a second chip 4 is mounted on the top surface of the thermal conductive adhesive 5, and the bottom surface of the second chip 4 abuts against the conductive connecting column 2, and the second chip 4 is connected to the first chip 3 through the conductive connecting column 2 and the outer-layer circuit; S500: a plastic package 7 is filled in the first chip 3 and the second chip 4 installation area to complete the packaging.

[0028] Please refer to Figures 1 to 7 In the technical solution provided by the present invention, the second chip 4 is stacked with the first chip 3 through the conductive connecting column 2, which greatly reduces the plane area of ​​the packaged chip components. At the same time, the thermal conductive glue 5 is filled between the two cores to balance the heat generated by the two chips and prevent the first chip 3 in the lower layer from being damaged due to overheating, which greatly improves the reliability and avoids the heat accumulation effect affecting the operation of the packaged chip; the first chip 3 and the second chip 4 are connected and connected by signals and functionally interconnected through the conductive connecting column 2 and the circuit on the packaging substrate 1, and at the same time, the thermal conductive glue 5 is prevented from expanding and cooling due to heat, causing the gap between the first chip 3 and the second chip 4 to become larger, affecting the fit between the thermal conductive glue 5 and the chip, thereby reducing the thermal conductivity.

[0029] Please refer to Figure 2In step S100, the package substrate 1 includes several layers of carrier boards 11, a plurality of signal via holes 111 are arranged on the carrier boards 11, copper plating is performed in the signal via holes 111, and the carrier boards 11 are stacked so that the signal via holes 111 of two adjacent carrier boards 11 are connected correspondingly. A preset position 112 and an outer layer circuit are arranged on the surface of the carrier board 11 located at the top layer, and the outer layer circuit is used for signal conduction between the conductive connection column 2 and the first chip 3 in the preset position 112, and the conductive connection column 2 is connected to the signal via hole 111. The packaging substrate 1 in this embodiment is a radio frequency substrate, which includes four layers of carrier boards 11 for winding inductors. The manufacturing process of the carrier board 11 is as follows: baking the raw printed circuit board, drilling positioning holes, using laser to drill signal via holes 111 and performing copper plating inside, printing and developing the internal circuits of the carrier board 11, and the above steps complete the basic production process of a carrier board 11; after completing the production of a bottom carrier board 11, it is stacked on top and multi-layered and pressed, and the upper carrier board 11 is drilled with an X-laser target to drill positioning holes for braiding (removing the edge copper coating) and outer layer graphics, and then the above-mentioned production process of the signal via holes 111 is repeated again to obtain the signal via holes 111, and the signal via holes 111 of adjacent layers are connected correspondingly. Repeat the above manufacturing process of the carrier board 11 until the top layer of the carrier board 11 is completed. The purpose of setting the multi-layer carrier board 11 is: the packaging structure is applied to the radio frequency chip, the multi-layer stacking structure is for winding the inductor circuit, and the design of the multi-layer stacking structure allows the inductance value to be significantly improved by increasing the number of layers of the inductor coil and the number of turns of each layer of the coil within a limited packaging space.

[0030] Please refer to Figure 2 and Figure 7, in step S100 to step S200, between step S100 and step S200, there are also steps S110 and S120: after the first chip 3 pad is balled, multiple first chips 3 are set on the same tape carrier 8 (tape), the balling is to allow the solder ball 31 to be soldered with the bottom pin of the chip in advance, the first chip 3 is loaded into the tape to prepare for the PNL level (panel level) substrate patching by the patch equipment, and the patch equipment drives all the first chips 3 to be fixed to the preset position 112 one by one through the tape disk (tape carrier 8). Multiple first partitions 113 are divided on the package substrate 1, at least one preset position 112 is located in the first partition 113, and at least one first target 1131 is set in the first partition 113, and the first target 1131 is used for alignment when the patch equipment attaches the first chip 3 to the preset position 112. During the process of mounting the first chip 3, the first target 1131 is taken to divide the packaging substrate 1 into multiple first partitions 113 for mounting operations. There is at least one preset position 112 in each first partition 113. The mounting equipment in each first partition 113 aligns and mounts the chips separately through the first target 1131. Due to the expansion and contraction of the surface of the packaging substrate 1, the alignment and mounting of the divided intervals can improve the overall alignment accuracy. The more the number of divided first partitions 113, the higher the alignment accuracy.

[0031] Please refer to Figure 3 , in step S100 to step S200, the first chip 3 is flip-chipped and glued in a Class 100 clean room using a high-precision glue dispenser, which can effectively reduce the introduction of dust and other pollutants. Before mounting, glue dispensing and soldering need to be performed at the preset position 112. The requirement for the mounting equipment is that the offset can be controlled within 20um. After the glue dispensing is completed, the mounting of the first chip 3 needs to be completed within 6 hours to prevent the problem of cracking of the solder ball 31 of the first chip 3 during the second flip-chip mounting. After the mounting of the first chip 3 is completed, solid crystal reflow needs to be performed, and vacuum reflow needs to be used, which can effectively reduce the formation of bubbles and gaps during the heating process and improve the bonding strength between the chip and the circuit board. The equipment temperature needs to be greater than 100 degrees Celsius, and the flux can be volatilized in this process, and finally the flip-chip mounting of the first chip 3 is completed.

[0032] Please refer to Figures 3 to 5, in step S300 to step S320, after the production of the package substrate 1 is completed, multiple layers of dry film are laid on the outer layer circuit by vacuum lamination according to the designed height of the conductive connection column 2, and the dry film is cut and exposed to form a printed pattern of the conductive connection column 2. Before electroplating, a copper layer can be plated on the dry film or a copper layer can be set by sputtering copper, and then the unexposed part of the printed pattern is developed and then a secondary layer is electroplated to obtain the conductive connection column 2; before attaching the second chip 4, all the conductive connection columns 2 need to be leveled to the same end face, and dry film is attached to the top of all the conductive connection columns 2. After curing, the dry film is removed using an organic film stripping liquid to keep the top end faces of all the conductive connection columns 2 on the same plane. After the production of the conductive connection column 2 is completed, a tin layer is overprinted on the top of the conductive connection column 2 through a special mold, so that the conductive connection column 2 retains the solder paste process and is completely attached to the conductive connection column 2 through vacuum reflow hot melting to prevent the solder paste from affecting other positions of the package substrate 1. During the process of laying the thermal conductive adhesive 5 on the upper surface of the first chip 3, a printing mold 6 is used and placed above the packaging substrate 1. An avoidance window is opened therein. Except for the upper end surface of the first chip 3, the rest of the parts that do not need to be glued are covered. The whole board can be overprinted at one time, and there is no need for a dispensing machine to perform single-point production operations, which greatly improves the alignment accuracy and production efficiency.

[0033] Please refer to Figure 5 In step S400, the second flip-chip application of the second chip 4 and the first flip-chip application of the first chip 3 are performed in substantially the same method and environment. The packaging substrate 1 is divided into a plurality of second partitions 114, at least one first chip 3 is located in the second partition 114, and at least one second target 1141 is provided in the second partition 114. The second target 1141 is used for alignment during the process of the chip mounting equipment attaching the second chip 4 to the top surface of the first chip 3. The number of second partitions 114 is greater than the number of first partitions 113. The functions of the second partition 114 and the second target 1141 are the same as those of the first target 1131 and the first partition 113 during the mounting process of the first chip 3. It should be noted that the number of second partitions 114 is greater than that of the first partitions 113. As mentioned above, the more partitions there are, the smaller the area of ​​the partitions is and the higher the alignment accuracy is. After the first chip 3 is flip-chip mounted, the second chip 4 is flip-chip mounted and a total of two area divisions are performed. If the number of the latter division intervals is less than the previous one, the deviation of the chip installation positions will increase. Only with more partitions will the alignment deviation between the two chips be smaller.

[0034] Please refer to Figure 6In step S500, after the first chip 3 and the second chip 4 are flipped, the plastic package 7 is filled. The plastic package 7 can be a thermosetting resin material to form a package body that protects the chip and the connection wires to protect the internal chip and the connection from the external environment, and at the same time provide the necessary mechanical support to achieve the overall PNL-level packaging. Subsequently, the sub-blocks are cut (removing the excess copper layer), and at the same time, the edges of the finished product are ensured to be neat, and the small blocks are cut into single pieces through a cutting device to obtain the final product.

[0035] Please refer to Figure 6 The present invention also provides a dual-core stacked substrate packaging structure, including: a packaging substrate 1, including at least one layer of carrier board 11, the carrier board 11 is provided with a plurality of preset positions 112 for installing chips; at least two conductive connecting pillars 2, arranged around the preset position 112; a first chip 3, arranged in the preset position 112, the first chip 3 is electrically connected to the conductive connecting pillar 2, and the top surface of the first chip 3 is provided with a thermal conductive adhesive 5; a second chip 4, attached to the thermal conductive adhesive 5, the bottom surface of the second chip 4 is aligned and abutted with the conductive connecting pillar 2, and the second chip 4 is electrically connected to the first chip 3 through the conductive connecting pillar 2. This packaging structure is mainly used for packaging radio frequency chips, the packaging substrate 1 is used to wrap the inductor circuit, the thermal conductive adhesive 5 therein can balance the heat generated by the two radio frequency chips, and prevent the first chip 3 from being damaged due to the heat generated by its own work and the heat accumulated by the work of the inductor line, the signal conduction between the two radio frequency chips is completed through the conductive connecting pillar 2, and the plastic packaging material is filled on the top of the packaging substrate 1 to wrap the first chip and the second chip to protect them from external mechanical impact.

[0036] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Although the present invention has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-core stacked substrate packaging method, characterized in that: Includes steps: S100: a plurality of preset positions (112) are provided on the top surface of the packaging substrate (1), and a plurality of conductive connection pillars (2) and outer layer circuits electrically connected to the conductive connection pillars (2) are provided around the preset positions (112); S200: mounting a first chip (3) at the preset position (112) on the top surface of the packaging substrate (1), wherein the first chip (3) is electrically connected to the outer layer circuit; S300: Disposing a thermal conductive adhesive (5) on the top surface of the first chip (3); S400: mounting the second chip (4) on the top surface of the thermally conductive adhesive (5), with the bottom surface of the second chip (4) abutting against the conductive connecting column (2), and the second chip (4) being connected to the first chip (3) through the conductive connecting column (2) and the outer layer circuit; S500: Filling a plastic packaging member (7) in the mounting area of ​​the first chip (3) and the second chip (4) to complete packaging.

2. The dual-core stacked substrate packaging method according to claim 1, characterized in that: In step S100, the packaging substrate (1) includes a plurality of carrier boards (11), a plurality of signal via holes (111) are provided on the carrier boards (11), copper plating is performed in the signal via holes (111), and the carrier boards (11) are stacked so that the signal via holes (111) of two adjacent carrier boards (11) are connected correspondingly.

3. The dual-core stacked substrate packaging method according to claim 2, characterized in that: In step S100, the preset position (112) and the outer layer circuit are arranged on the surface of the carrier (11) located at the top layer, the outer layer circuit is used for signal conduction between the conductive connection column (2) and the first chip (3) in the preset position (112), and the conductive connection column (2) is connected to the signal conduction hole (111).

4. The dual-core stacked substrate packaging method according to claim 3, characterized in that: Also included between step S100 and step S200 is step S110: after the first chip (3) pads are ball-planted, a plurality of the first chips (3) are arranged on the same strip carrier (8), and each of the first chips (3) is pasted to a corresponding preset position (112) via the strip carrier (8) under the drive of a patch device.

5. The dual-core stacked substrate packaging method according to claim 4, characterized in that: Also included between step S100 and step S200 is step S120: a plurality of first partitions (113) are divided on the packaging substrate (1), at least one of the preset positions (112) is located in the first partition (113), at least one first target (1131) is provided in the first partition (113), and the first target (1131) is used for alignment during the process of bonding the first chip (3) to the preset position (112) by a bonding device.

6. The dual-core stacked substrate packaging method according to claim 5, characterized in that: Between step S300 and step S400, there is also a step S310: laying multiple layers of dry film on the outer layer circuit according to the height of the conductive connecting column (2), cutting and exposing the dry film to form a printed pattern of the conductive connecting column (2), and developing the unexposed part of the printed pattern and then performing multi-layer electroplating to obtain the conductive connecting column (2).

7. The dual-core stacked substrate packaging method according to claim 6, characterized in that: Between step S300 and step S400, step S320 is also included: leveling the tops of all the conductive connection posts (2) and applying a dry film, and removing the dry film using an organic film stripping liquid after curing, so that the top end faces of all the conductive connection posts (2) remain on the same plane.

8. The dual-core stacked substrate packaging method according to claim 7, characterized in that: Also included between step S300 and step S400 is step S330: after printing a tin layer on the top of the conductive connection column (2), the second chip (4) is attached to the thermal conductive adhesive (5), and the tin layer is attached to the bottom surface of the second chip (4).

9. The dual-core stacked substrate packaging method according to claim 8, characterized in that: In step S400, the packaging substrate (1) is divided into a plurality of second partitions (114), at least one of the first chips (3) is located in the second partition (114), at least one second target (1141) is provided in the second partition (114), the second target (1141) is used for alignment when a chip mounting device mounts the second chip (4) to the top surface of the first chip (3), and the number of the second partitions (114) is greater than the number of the first partitions (113).

10. A dual-core stacked substrate packaging structure, characterized in that: include: A packaging substrate (1) comprises at least one carrier board (11), wherein the carrier board (11) is provided with a plurality of preset positions (112) for mounting chips; At least two conductive connection pillars (2) are arranged around the preset position (112); A first chip (3) is arranged in the preset position (112), the first chip (3) is electrically connected to the conductive connection column (2), and a thermal conductive adhesive (5) is provided on the top surface of the first chip (3); The second chip (4) is attached to the thermally conductive adhesive (5), the bottom surface of the second chip (4) is aligned and abutted against the conductive connecting column (2), and the second chip (4) is electrically connected to the first chip (3) via the conductive connecting column (2).

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