Semiconductor package and method of forming same

Abstract

A method of forming a semiconductor package, the method including: surrounding a die with a molding material; and forming a redistribution structure (RDS) over the molding material, and the RDS being electrically coupled to the die, the forming the RDS including: depositing a first dielectric layer over the molding material; patterning the first dielectric layer to form a first opening in the first dielectric layer; performing a first scum removal process to clean the first opening; forming a first redistribution layer (RDL) on the first dielectric layer after performing the first scum removal process; depositing a second dielectric layer over the molding material; patterning the second dielectric layer to form a second opening in the second dielectric layer; performing a second scum removal process to clean the second opening, where the first scum removal process and the second scum removal process are performed under different process conditions; and forming a second RDL on the second dielectric layer after performing the second scum removal process. The embodiment of the invention also provides a semiconductor package.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor packages and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is due to the iterative reduction of the minimum component size, which allows more components to be integrated into a given area. With the growth of the demand for shrinking electronic devices, there has emerged a need for smaller and more creative semiconductor die packaging technology. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration density and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] Some embodiments of the present disclosure provide a method for forming a semiconductor package, the method comprising: surrounding a tube core with a molding material; and forming a redistribution structure above the molding material, and the redistribution structure is electrically coupled to the tube core, the formation of the redistribution structure comprising: depositing a first dielectric layer above the molding material; patterning the first dielectric layer to form a first plurality of openings in the first dielectric layer; performing a first descum process to clean the first plurality of openings; after performing the first descum process, forming a first redistribution layer on the first dielectric layer; depositing a second dielectric layer above the molding material; patterning the second dielectric layer to form a second plurality of openings in the second dielectric layer; performing a second descum process to clean the second plurality of openings, wherein the first descum process and the second descum process are performed under different process conditions; and after performing the second descum process, forming a second redistribution layer on the second dielectric layer.

[0004] Some other embodiments of the present disclosure provide a method for forming a semiconductor package, the method comprising: forming a molding material around a tube core; forming a first dielectric layer over the molding material using a polymer material; patterning the first dielectric layer to form a first plurality of openings in the first dielectric layer; after patterning the first dielectric layer, performing a first descum process, wherein the first descum process is a first plasma process performed at a first pressure and a first duration; after performing the first descum process, forming a conductive material in the first plurality of openings and over an upper surface of the first dielectric layer to form a first redistribution layer; forming a second dielectric layer over the first dielectric layer using a polymer material; patterning the second dielectric layer to form a second plurality of openings in the second dielectric layer; after patterning the second dielectric layer, performing a second descum process, wherein the second descum process is a second plasma process performed at a second pressure and a second duration, wherein the second pressure is different from the first pressure and the second duration is different from the first duration; and after performing the second descum process, forming a conductive material in the second plurality of openings and over an upper surface of the second dielectric layer to form a second redistribution layer.

[0005] Another embodiment of the present disclosure provides a semiconductor package, which includes: a die; a molding material located around the die; and a redistribution structure located at a first side of the molding material and electrically coupled to the die, the redistribution structure including: a first dielectric layer in contact with the first side of the molding material and extending along the first side of the molding material, wherein a first surface of the first dielectric layer away from the molding material has a first surface roughness; a first redistribution layer along the first surface of the first dielectric layer; a second dielectric layer along the first surface of the first dielectric layer and the first redistribution layer, wherein a second surface of the second dielectric layer away from the molding material has a second surface roughness higher than the first surface roughness; and a second redistribution layer along the second surface of the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 9 , Fig. 10A , Fig. 10B , Fig.11 , Fig. 12A , Fig. 12B , Fig.13 , Fig.14A , Fig. 14B and Figures 15 to 24 Cross-sectional views of a semiconductor package at various manufacturing steps according to an embodiment are shown.

[0008] Fig.25A and Fig.25B Together, flowcharts of methods of forming a semiconductor package according to an embodiment are shown. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples of different components for implementing the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. Throughout the discussion herein, unless otherwise stated, the same or similar reference numerals in different figures refer to the same or similar components formed by the same or similar processes using the same or similar materials.

[0010] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0011] The embodiments discussed herein may be discussed in a specific context, such as the formation of a redistribution structure of an integrated fan-out (InFO) package. The redistribution structure of the InFO package includes a plurality of polymer layers and a redistribution layer (e.g., a metal pattern including wires and vias) formed above the polymer layer. Depending on the topography of the underlying metallization pattern, each polymer layer in the redistribution structure may be treated by a different descumming process. For example, a point of reference (POR) descumming process may be performed at about 70 Pascals for a duration of about 60 seconds, and an enhanced low-pressure descumming process may be performed at a lower pressure for a longer duration, such as at about 35 Pascals for a duration between 60 seconds and 300 seconds. Criteria for determining which descumming process to use for each polymer layer are disclosed. The enhanced low-pressure descumming process may produce a higher surface roughness and lower reflectivity in the treated polymer layer, which mitigates bridging problems (e.g., electrical shorts) of the metallization pattern formed on the treated polymer layer. In addition, the enhanced low pressure descum process can achieve better sidewall profiles and smaller footing, which in turn allows for better overlay control and fewer stress-related issues (e.g., delamination and cracking). The disclosed standard allows for flexible selection between the POR descum process and the enhanced low pressure descum process to achieve a balance between better device performance and higher production yields.

[0012] It should be noted that the embodiments discussed herein do not necessarily illustrate every component or part that may be present in the structure.In addition, the method embodiments discussed herein may be discussed as being performed in a particular order; however, other method embodiments may be performed in any logical order.

[0013] Figures 1 to 9 , Fig. 10A , Fig. 10B , Fig.11 , Fig. 12A , Fig. 12B , Fig.13 , Fig.14A , Fig. 14B and Figures 15 to 24 1 shows a cross-sectional view of a semiconductor package 500 according to an embodiment at various manufacturing steps. In an embodiment, the semiconductor package 500 is formed by placing a top package 300 (eg, a memory package, see Fig.24 ) is attached to a bottom package 200 (e.g., an integrated fan-out (InFO) package) to form a PoP package. In the illustrated embodiment, Figures 1 to 9 , Fig. 10A , Fig. 10B , Fig.11 , Fig. 12A , Fig. 12B , Fig.13 , Fig.14A , Fig. 14B and Figures 15 to 23 The processing steps for forming an InFO package 200 as the bottom package are shown. Fig.24 The PoP package 500 is shown formed by attaching the top package 300 to the InFO package 200 .

[0014] Reference now Figure 1 , Figure 1 A carrier substrate 100 and a release layer 102 formed on the carrier substrate 100 are shown. A first packaging region 600 and a second packaging region 602 are shown for forming a first semiconductor package (eg, a first InFO package) and a second semiconductor package (eg, a second InFO package), respectively.

[0015] The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 100 may be a wafer so that a plurality of packages may be formed on the carrier substrate 100 at the same time. The release layer 102 may be formed of a polymer-based material, which may be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 100. In some embodiments, the release layer 102 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 102 may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 102 may be dispensed in a liquid form and cured, and the release layer 102 may be a laminated film laminated to the carrier substrate 100, etc. The top surface of the release layer 102 may be horizontal and may have a high degree of flatness (e.g., flatness).

[0016] exist Figure 2 In the embodiment, a dielectric layer 104 and a metallization pattern 106 (sometimes referred to as a redistribution layer 106 or a redistribution line 106) are formed. Figure 2 As shown, dielectric layer 104 is formed on release layer 102. The bottom surface of dielectric layer 104 may be in contact with the top surface of release layer 102. In some embodiments, dielectric layer 104 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, dielectric layer 104 is formed of a nitride (such as silicon nitride), an oxide (such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.), etc. The dielectric layer 104 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, etc., or a combination thereof.

[0017] Metallization pattern 106 is formed on dielectric layer 104. As an example of forming metallization pattern 106, a seed layer (not shown) is formed above dielectric layer 104. In some embodiments, seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, seed layer includes a titanium layer and a copper layer located above the titanium layer. For example, physical vapor deposition (PVD) etc. can be used to form seed layer. Then a photoresist is formed on the seed layer and the photoresist is patterned. Photoresist can be formed by spin coating etc., and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to metallization pattern 106. The patterning of the photoresist forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. Conductive material can be formed by plating such as electroplating or chemical plating. Conductive material can include metals, such as copper, titanium, tungsten, aluminum etc. Then, remove the photoresist and the portion of the seed layer on which the conductive material is not formed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the conductive material and the seed layer forms the metallization pattern 106. It should be noted that in the discussion herein, unless otherwise stated, "conductive" refers to "conductivity", and conductive material refers to conductive material (e.g., having low resistance and suitable for transmitting current), such as copper, tungsten, aluminum, gold, etc., or a combination thereof. The term "conductive" can be used interchangeably with the term "conductivity" in this article.

[0018] Next, in Figure 3 In the embodiment of the present invention, a dielectric layer 108 is formed on the metallization pattern 106 and the dielectric layer 104. In some embodiments, the dielectric layer 108 is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithography mask, such as PBO, polyimide, BCB, etc. In other embodiments, the dielectric layer 108 is formed of a nitride (such as silicon nitride), an oxide (such as silicon oxide, PSG, BSG, BPSG), etc. The dielectric layer 108 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. The dielectric layer 108 is then patterned to form an opening to expose a portion of the metallization pattern 106. The patterning may be performed by an acceptable process, such as by exposing the dielectric layer 108 to light when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching.

[0019] The dielectric layers 104 and 108 and the metallization pattern 106 may be referred to as a backside redistribution structure 110. As shown, the backside redistribution structure 110 includes two dielectric layers 104 and 108 and a layer of metallization pattern 106. In other embodiments, the backside redistribution structure 110 may include any number of dielectric layers, metallization patterns, and vias. By repeating the process of forming the metallization pattern 106 and the dielectric layer 108, one or more additional metallization patterns and dielectric layers may be formed in the backside redistribution structure 110. A via may be formed by forming a seed layer and a conductive material of the metallization pattern in an opening of the underlying dielectric layer during the formation of the metallization pattern. The vias may thereby interconnect and electrically couple the individual metallization patterns.

[0020] Next, in Figure 3 and Figure 4 In the embodiment, a through hole 112 is formed in the dielectric layer 108 to expose a portion of the metallization pattern 106 below in order to form the through hole 112. In an embodiment, in order to form the through hole 112, an opening is formed in the dielectric layer 108 to expose a portion of the metallization pattern 106 below. As shown in the figure, a seed layer 109 is formed in the opening above the dielectric layer 108 and above the exposed portion of the metallization pattern 106. In some embodiments, the seed layer 109 is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer 109 includes a titanium layer and a copper layer located above the titanium layer. For example, PVD or the like can be used to form the seed layer 109. Next, a photoresist 111 is formed on the seed layer 109 and the photoresist 111 is patterned. The photoresist 111 can be formed by spin coating or the like, and the photoresist 111 can be exposed to light for patterning. The pattern of the photoresist 111 corresponds to the through hole. Patterning forms an opening through the photoresist 111 to expose the seed layer 109. A conductive material is formed in the opening of the photoresist 111 and on the exposed portion of the seed layer 109. The conductive material may be formed by plating such as electroplating or chemical plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like.

[0021] Next, in Figure 4 In the embodiment of the present invention, the photoresist 111 and the portion of the seed layer 109 on which the conductive material is not formed are removed. The photoresist 111 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist 111 is removed, the exposed portion of the seed layer 109 is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the conductive material and the seed layer 109 forms a through hole 112. It should be noted that for simplicity, Figure 4 The portion of the seed layer 109 located below the through hole 112 is not separately shown in the following drawings.

[0022] Next, in Figure 5In the embodiment, an integrated circuit die 114 (also referred to as die 114) is attached to dielectric layer 108 by adhesive 116. Figure 5 As shown, two integrated circuit dies 114 are attached in each of the first packaging area 600 and the second packaging area 602. In other embodiments, more or fewer integrated circuit dies 114 may be attached in each area. For example, in an embodiment, only one integrated circuit die 114 may be attached in each area. The integrated circuit die 114 may be a logic die (e.g., a central processing unit (CPU), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof. Moreover, in some embodiments, the integrated circuit die 114 may have different sizes (e.g., different heights and / or surface areas), while in other embodiments, the integrated circuit die 114 may have the same size (e.g., the same height and / or surface area).

[0023] Prior to being attached to the dielectric layer 108, the integrated circuit die 114 may be processed according to an applicable manufacturing process to form an integrated circuit in the integrated circuit die 114. For example, the integrated circuit die 114 each includes a semiconductor substrate 118, such as doped or undoped silicon or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. Devices such as transistors, diodes, capacitors, resistors, etc. may be formed in and / or on the semiconductor substrate 118, and the devices may be interconnected by an interconnect structure 120 (formed, for example, by metallization patterns in one or more dielectric layers on the semiconductor substrate 118) to form an integrated circuit.

[0024] The integrated circuit die 114 also includes a pad 122, such as an aluminum pad, for making external connections. The pad 122 is located on a side that can be referred to as a corresponding active side of the integrated circuit die 114. A passivation film 124 is located on the integrated circuit die 114 and on a portion of the pad 122. An opening passes through the passivation film 124 to the pad 122. A die connector 126, such as a conductive column (e.g., including a metal such as copper), is located in the opening through the passivation film 124, and the die connector 126 is mechanically coupled and electrically coupled to the corresponding pad 122. For example, the die connector 126 can be formed by plating, etc. The die connector 126 is electrically coupled to the circuit of the integrated circuit die 114.

[0025] The dielectric material 128 is located on the active side of the integrated circuit die 114, such as on the passivation film 124 and the die connector 126. The dielectric material 128 laterally seals the die connector 126, and the dielectric material 128 is laterally co-boundary with the corresponding integrated circuit die 114. The dielectric material 128 can be a polymer (such as PBO, polyimide, BCB, etc.), a nitride (such as silicon nitride, etc.), an oxide (such as silicon oxide, PSG, BSG, BPSG, etc.), etc., or a combination thereof, and the dielectric material 128 can be formed, for example, by spin coating, lamination, CVD, etc.

[0026] Adhesive 116 is located on the back side of integrated circuit die 114 and adheres integrated circuit die 114 to backside redistribution structure 110, such as dielectric layer 108 in the figure. Adhesive 116 can be any suitable adhesive, epoxy, die attach film (DAF), etc. Adhesive 116 can be applied to the back side of integrated circuit die 114, such as to the back side of a corresponding semiconductor wafer, or adhesive 116 can be applied over the surface of carrier substrate 100. Integrated circuit die 114 can be singulated by, for example, sawing or dicing, and adhered to dielectric layer 108 through adhesive 116 using, for example, a pick and place tool.

[0027] Next, in Figure 6 In the embodiment of the present invention, a sealant 130 (also referred to as a molding material 130) is formed on each component. The sealant 130 may be a molding compound, an epoxy resin, etc., and the sealant 130 may be applied by compression molding, transfer molding, etc. After curing, the sealant 130 may undergo a planarization process, such as a grinding process, a chemical mechanical planarization (CMP) process, etc., to expose the through-hole 112 and the tube die connection 126. After the planarization process, the top surfaces of the through-hole 112, the tube die connection 126, and the sealant 130 are coplanar.

[0028] Next, if Figures 7 to 9 , Fig. 10A , Fig. 10B , Fig.11 , Fig. 12A , Fig. 12B , Fig.13 , Fig.14A , Fig. 14B and Figures 15 to 19 As shown in FIG. 1 , a front side redistribution structure 160 is formed. Fig.19 As shown, the front side redistribution structure (RDS) 160 includes dielectric layers 132, 140, 148, and 156 and metallization patterns 138, 146, and 154 (also referred to as redistribution layers (RDL) 138, 146, and 154 or redistribution lines 138, 146, and 154).

[0029] exist Figure 7 In the embodiment of the present invention, a dielectric layer 132 is deposited on the encapsulant 130, the through-holes 112, and the die connectors 126. In some embodiments, the dielectric layer 132 is formed of a photosensitive material that can be patterned using a photolithography mask, such as PBO, polyimide, BCB, etc. The dielectric layer 132 can be formed by spin coating, lamination, CVD, etc., or a combination thereof. In some embodiments, due to the flat upper surface of the molding material 130, the deposited dielectric layer 132 (e.g., polymer layer) has a flat (e.g., horizontal) upper surface. The dielectric layer 132 can be deposited to a thickness that is the sum of the target thickness of the dielectric layer 132 (e.g., a thickness between about 4 μm and about 20 μm) and an additional thickness, which is, as an example, between about 0.5 μm and about 3.0 μm. As discussed below, a subsequent descum process for the dielectric layer 132 will reduce the thickness of the dielectric layer 132 to its target thickness.

[0030] Next, in Figure 8 , patterning dielectric layer 132. Patterning forms openings 133 in dielectric layer 132 to expose portions of vias 112 and die connectors 126. Patterning can be performed by an acceptable process, such as by exposing dielectric layer 132 to light when dielectric layer 132 is a photosensitive material, or by etching using, for example, anisotropic etching. In some embodiments where dielectric layer 132 is a photosensitive material, dielectric layer 132 is developed after exposure, and a post-development curing process is then performed to harden patterned dielectric layer 132.

[0031] Next, a descumming process is performed to clean the opening 133, for example, to remove residues generated by the patterning process from the bottom of the opening 133. In some embodiments, the descumming process is a plasma process performed using a gas source including oxygen or nitrogen. The gas source is ignited into a plasma (e.g., an oxygen plasma or a nitrogen plasma), and the opening 133 is cleaned using the plasma. In an exemplary embodiment, the descumming process for the dielectric layer 132 is performed for a duration of about 60 seconds at a pressure of about 70 Pascals (Pa). The process conditions (e.g., pressure and process duration) of the descumming process are adjusted to remove residues from the bottom of the opening 133. In some embodiments, the descumming process reduces the thickness of the dielectric layer 132 (e.g., uniformly across all positions of the dielectric layer 132) to its target thickness. The descumming process roughens the upper surface of the dielectric layer 132. In some embodiments, after completing the descumming process for the dielectric layer 132, the surface roughness parameter Rq of the upper surface of the dielectric layer 132 is less than about 5nm, such as 4.5nm. The surface roughness parameter Rq is an ISO standard parameter which represents the root mean square (RMS) value of the surface profile height deviation from the mean line.

[0032] The process conditions of the descum process performed on the dielectric layer 132 are different from the process conditions of the low-pressure descum process performed subsequently. To distinguish between the two descum processes and for ease of discussion, the descum process performed on the dielectric layer 132 (e.g., performed at about 70 Pascals for about 60 seconds) is also referred to herein as a point of reference (POR) descum process.

[0033] Next, a scrubber cleaning process is performed to clean the surface of the dielectric layer 132. Ashes or particles generated during the descum process for the dielectric layer 132 are removed by the scrubber cleaning process. In some embodiments, the scrubber cleaning process is performed using water (e.g., deionized water). Nitrogen (N2) may be mixed with water to increase the pressure of the water, thereby improving the cleaning efficiency of the scrubber cleaning process.

[0034] Next, in Fig. 9In the embodiment of the present invention, a metallization pattern 138 (also referred to as RDL138) having a through hole is formed on the dielectric layer 132. As an example of forming the metallization pattern 138, a seed layer (not shown) is formed above the dielectric layer 132 and in the opening 133 passing through the dielectric layer 132. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. For example, PVD or the like can be used to form the seed layer. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 138. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the conductive material and the seed layer forms a metallization pattern 138 and a via. The via is formed in an opening 133 through the dielectric layer 132, and the via is electrically coupled to, for example, a through-hole 112 or a die connector 126.

[0035] Next, in Fig. 10A In the embodiment of the present invention, a dielectric layer 140 is deposited on the metallization pattern 138 and the dielectric layer 132. In some embodiments, the dielectric layer 140 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, etc. The dielectric layer 140 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. In some embodiments, all dielectric layers (e.g., 132, 140, 148, and 156) of the front side RDS 160 are formed of the same material (e.g., a polymer material).

[0036] Fig. 10B Shows Fig. 10A For example, Fig. 10BShows a dielectric layer 132, two wires 138 (the portions of the metallization pattern 138 disposed on the upper surface of the dielectric layer 132), and the deposited dielectric layer 140. In some embodiments, the thickness T1 of the wire 138 is between about 2 μm and about 15 μm, the width L of the wire 138 is between about 1 μm and about 20 μm, the distance S between adjacent wires 138 is between about 1 μm and about 100 μm or greater, and the thickness T2 of the dielectric layer 140 above (e.g., directly above) the wire 138 is between about 2 μm and about 18 μm. The ratio of the distance S to the width L can be greater than one (e.g., S / L>1). The ratio of the thickness T1 to the thickness T2 can be between about 0.2 and about 5 (e.g., 0.2<T1 / T2<5), such as between about 0.4 and about 1.5.

[0037] As Fig. 10B shown, the thickness of the dielectric layer 140 is non-uniform, and the upper surface 140U of the dielectric layer 140 is uneven (e.g., a wavy upper surface). The non-uniform thickness of the dielectric layer 140 may be caused by variations in the height and / or pitch of the underlying metallization pattern 138. The wavy upper surface of the dielectric layer 140 may cause difficulties in subsequent processing steps (such as a lithography process). Thus, it is advantageous to reduce the depression depth R1 of the dielectric layer 140, where the depression depth R1 is the vertical distance between the peaks and valleys of the upper surface 140U of the dielectric layer 140.

[0038] In some embodiments, to reduce the depression depth R1, the dielectric layer 140 is deposited as the sum of a target thickness of the dielectric layer 140 (e.g., a target total thickness such as T1+T3, where T3 is as Fig. 12A shown) and an additional thickness, the additional thickness being between about 0.5 μm and about 3 μm. The additional thickness increases the total thickness of the dielectric layer 140, and the flatness (e.g., smoothness) of the upper surface 140U of the thicker dielectric layer 140 is less affected by variations in the height and / or pitch of the underlying metallization pattern 138. Thus, the depression depth R1 of the dielectric layer 140 with the additional thickness is reduced, e.g., to less than about 1.5 μm. As a comparison, if the dielectric layer 140 is formed to its target thickness without the additional thickness, the depression depth R1 of the dielectric layer 140 may be greater than about 2.3 μm.

[0039] Next, in Fig.11, patterning the dielectric layer 140. The patterning forms openings 141 to expose portions of the metallization pattern 138. The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 140 to light when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching. In embodiments where the dielectric layer 140 is a photosensitive material, the dielectric layer 140 is developed after exposure, and a post-development curing process is then performed to harden the patterned dielectric layer 140.

[0040] Next, in Fig. 12A and Fig. 12B In the process, a descum process 147 is performed to clean the openings 141 in the dielectric layer 140 (eg, to remove residues resulting from the patterning process). Fig. 12A (or Fig.13 or Fig. 14B ) shows the semiconductor package and Fig. 10B The descum process 147 corresponds to the portion shown. In some embodiments, the descum process 147 is a plasma process performed using a gas source including oxygen or nitrogen. The gas source is ignited into a plasma (e.g., an oxygen plasma or a nitrogen plasma), and the opening 141 is cleaned using the plasma. In an embodiment, the descum process 147 for the dielectric layer 140 is performed using the same gas source as the POR descum process for the dielectric layer 132, but the descum process 147 for the dielectric layer 140 is performed at a lower pressure and for a longer duration than the POR descum process. For ease of discussion, the descum process 147 performed to treat the dielectric layer 140 is referred to as an enhanced low-pressure descum process.

[0041] In an embodiment, the enhanced low-pressure descum process 147 is performed at a pressure between about 30% and about 70% of the pressure of the POR descum process, and the duration is between about 1 and about 5 times the duration of the POR descum process, such as between about 2 and about 5 times the duration of the POR descum process. For example, when the POR descum process may be performed at a pressure of about 70 Pascals and the duration is about 60 seconds, the enhanced low-pressure descum process 147 may be performed at a pressure of about 35 Pascals and the duration is between about 60 seconds and about 300 seconds.

[0042] In some embodiments, the process conditions (e.g., pressure and duration) of the enhanced low-pressure descum process 147 are adjusted to remove residues from the bottom of the opening 141 to uniformly reduce the thickness of the dielectric layer 140 (e.g., uniformly across all locations of the dielectric layer 140) to its target thickness and increase the surface roughness of the dielectric layer 140 more than the POR descum process. In some embodiments, the enhanced low-pressure descum process etches (e.g., removes) the dielectric layer 140 at a faster rate than the POR descum process, and thus, the additional deposition thickness of the dielectric layer 140 (e.g., the additional thickness above T1+T3) can be greater than the additional deposition thickness of the dielectric layer 132, which helps to reduce the recess depth R1 of the dielectric layer 140.

[0043] like Fig. 12A As shown, after the enhanced low-pressure descumming process 147 is completed, the upper surface 140U of the dielectric layer 140 is Fig. 10B The position of the upper surface 140U in ( Fig. 12A In an embodiment, the thickness T3 of the (recessed) dielectric layer 140 above (eg, directly above) the conductive line 138 is between about 2 μm and about 15 μm. It is worth noting that Fig. 12A The recess depth R1 of the dielectric layer 140 is Fig. 10B The recess depth R1 of the dielectric layer 140 is the same, and the recess depth R1 is less than about 1.5 μm. In other words, the enhanced low-pressure descum process 147 retains the dielectric layer 140 deposited to a depth smaller than 1.5 μm. Fig. 10B In some embodiments, the degree of planarization (DOP) of the dielectric layer 140 is calculated as Because the recess depth R1 of the dielectric layer 140 achieved using a larger deposition thickness (e.g., the target thickness plus an additional thickness of 0.5 μm to 3 μm) and the enhanced low-pressure descum process 147 is smaller than the recess depth achieved using a smaller deposition thickness and the POR descum process, the DOP of the dielectric layer 140 is higher than the DOP of the dielectric layer 140 if the smaller deposition thickness and the POR descum process are used. For example, the DOP achieved using a larger deposition thickness and the enhanced low-pressure descum process 147 may be greater than about 79%, while the DOP achieved using a smaller deposition thickness and the POR descum process may be less than about 70%.

[0044] Furthermore, the enhanced low pressure descum process 147 significantly roughens the upper surface of the dielectric layer 140 . Fig. 12AA plurality of notches 140D are shown located at the upper surface 140U of the dielectric layer 140. The size of the notches 140D may be exaggerated to show the significantly increased surface roughness of the dielectric layer 140. In some embodiments, after completing the enhanced low-pressure descum process 147, the surface roughness parameter Rq of the upper surface of the dielectric layer 140 is between about 1.5 times and about 10 times, such as between two times and about ten times, the surface roughness parameter Rq of the dielectric layer 132 after the POR descum process. For example, the POR descum process may cause the dielectric layer 132 to produce a surface roughness parameter Rq of less than about 5 nm (such as 4.5 nm). In contrast, the enhanced low-pressure descum process 147 may cause the dielectric layer 140 to produce a surface roughness parameter Rq of between about 7 nm and about 40 nm. As discussed below, the higher surface roughness caused by the enhanced low-pressure descum process 147 causes the subsequently formed seed layer 143 (see Fig.13 ) produces significantly reduced reflectivity, which achieves further advantages as discussed below.

[0045] It should be noted that Fig. 12A A portion of the semiconductor package is shown without the opening 141 in the dielectric layer 140 . Fig. 12B Another portion of the semiconductor package is shown having an opening 141 in the dielectric layer 140. For simplicity, Fig. 12B The upper surface 140U of the dielectric layer 140 is Fig. 12B 140U, it is understood that the upper surface 140U may be uneven and may have indentations due to increased surface roughness.

[0046] like Fig. 12B As shown, the opening 141 exposes the sidewall 140S of the dielectric layer 140 and the underlying conductive line 138. The sidewall 140S is relatively Fig. 12B The conductor 138 is inclined in the horizontal direction and forms an angle α with the upper surface of the conductor 138 . Fig. 12B The opening 141 in the conductive line 138 has a trapezoidal cross-section. In other words, the distance between the opposite sidewalls 140S exposed by the opening 141 decreases as the opening 141 extends toward the conductive line 138. In some embodiments, the enhanced low-pressure descumming process 147 can better remove residue from the opening 141 than the POR descumming process, thereby creating a better sidewall profile, with the sidewalls 140S closer to being perpendicular to the conductive line 138. Fig. 12B In other words, if a POR descum process is performed to clean the opening 141, the angle α created by the POR descum process will be smaller than the angle α created by the enhanced low pressure descum process 147. Better sidewall profiles allow for better overlay control in lithography.

[0047] Fig. 12BThe footing 140F at the bottom of each sidewall 140S of the dielectric layer 140 is further shown in dotted lines. The footing 140F represents a protruding portion of the dielectric layer 140 that protrudes into the opening 141. In a subsequent process, the opening 141 is filled with a conductive material to form a through hole. The footing 140F reduces the contact area between the through hole and the wire 138, thereby increasing the contact resistance. In addition, after the opening 141 is filled with a conductive material to form a through hole, the area around the footing 140F is subjected to higher stress and has a higher risk of failure such as delamination or cracking. In some embodiments, the width W of the footing 140F after the enhanced low-pressure descumming process 147 is less than the width of the footing after the POR descumming process. This shows another advantage of the enhanced low-pressure descumming process 147 (e.g., lower contact resistance, less stress). For example, if a POR descumming process is performed to clean the opening 141, the width W of the footing 140F may be greater than about 0.6 μm. In contrast, if the enhanced low pressure descum process 147 is performed to clean the opening 141, the width W of the footing 140F may be less than about 0.6 μm. It should be noted that since the opening 141 is subsequently filled to form a through hole (eg, see Fig.14A The through hole 146V in the opening 141, therefore the shape and size of the opening 141 correspond to the shape and size of the through hole to be formed later.

[0048] Next, after the enhanced low pressure descum process 147, a scrubber cleaning process is performed to clean the surface of the dielectric layer 140. Ashes or particles generated during the descum process for the dielectric layer 140 are removed by the scrubber cleaning process. The scrubber cleaning process may be the same as or similar to the scrubber cleaning process discussed above, and thus the details will not be repeated.

[0049] Next, in Fig.13 In the embodiment of the present invention, a seed layer 143 is formed (e.g., conformally) on the upper surface 140U of the dielectric layer 140 and in the opening 141 passing through the dielectric layer 140. In some embodiments, the seed layer 143 is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer 143 includes a titanium layer and a copper layer located above the titanium layer. For example, PVD or the like can be used to form the seed layer.

[0050] Since the upper surface 140U has a high surface roughness parameter Rq, the seed layer 143 also has a high surface roughness parameter Rq that is the same or similar to the dielectric layer 140. The high surface roughness of the seed layer 143 causes the seed layer 143 to have a low reflectivity, where the reflectivity can be calculated as the percentage of incident light energy reflected by the seed layer 143. In an embodiment, the reflectivity of the seed layer (e.g., 143) formed on the surface (e.g., 140U) of the dielectric layer (e.g., 140) treated by the enhanced low-pressure descum process is lower than the reflectivity of the seed layer formed on the surface (if the surface is treated by the POR descum process) (e.g., about one-third or less). For example, the reflectivity of the seed layer formed on the dielectric layer 132 is about 45%, while the reflectivity of the seed layer 143 formed on the dielectric layer 140 is about 15% or less.

[0051] Next, a photoresist 144 is formed on the seed layer 143 and patterned. The photoresist 144 may be formed by spin coating or the like, and may be exposed to light for patterning. Fig.13 In the example of , light source 142 is projected through photomask 145 to expose photoresist 144. In some embodiments, after exposure, photoresist 144 is developed, and a post-development curing process is then performed to harden the patterned photoresist 144. The pattern of photoresist 144 corresponds to a subsequently formed metallization pattern 146 (see Fig.14A ). The patterning of the photoresist 144 forms an opening through the photoresist 144 to expose the seed layer 143 .

[0052] like Fig.13 As shown, part of the light source 142 (referred to as the reflected light source 142R) is reflected by the seed layer 143. The reflected light source 142R may expose the photoresist 144 and thereby deform the pattern of the patterned photoresist 144. Fig.13 In the example of FIG. 1 , if the reflected light source 142R (shown as a dashed arrow line) is strong enough, the reflected light source 142R may expose the top layer of the portion 144A of the photoresist 144 and thereby reduce the height of the portion 144A (e.g., after development). In subsequent processing, when a conductive material is formed to fill the opening in the photoresist 144, the conductive material may flow over the top surface of the portion 144A (which has a reduced height relative to other portions of the photoresist 144) and cause bridging problems (e.g., electrical shorts) between metallization patterns formed on opposite sides of the portion 144A of the photoresist 144, thereby causing device failure and yield loss.

[0053] Recall that the seed layer 143 has increased surface roughness and lower reflectivity caused by the enhanced low-pressure descum process 147. Due to the low reflectivity, only a small portion (e.g., 15% or less) of the incident light energy is reflected, which prevents or mitigates the effect of the reflected light source 142R exposing the photoresist 144. The increased surface roughness also causes the reflected light source 142R to propagate in random directions, thereby scattering the reflected light energy and preventing the reflected light energy from being concentrated in a certain area, further reducing the possibility of bridging problems. Thus, the seed layer 143 with low reflectivity and high surface roughness acts as a bottom anti-reflective coating (BARC) for the photoresist 144.

[0054] Next, in Fig.14A In the process, a conductive material is formed in the opening of the photoresist 144 and on the exposed portion of the seed layer 143. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist 144 and the seed layer 143 are removed, and the portion on which the conductive material is not formed. The photoresist 144 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist 144 is removed, the exposed portion of the seed layer 143 is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the conductive material and the seed layer 143 forms a metallization pattern 146, which includes a wire and a through hole 146V located above the upper surface of the dielectric layer 140. The through hole 146V is formed in an opening passing through the dielectric layer 140 and is electrically coupled to a portion of, for example, the metallization pattern 138.

[0055] Fig. 14B Shows Fig.14A The semiconductor package is part of the Fig. 14B In the example of FIG. 1 , a plurality of conductive lines 146 are shown on the dielectric layer 140 (eg, portions of the metallization pattern 146 disposed above the upper surface of the dielectric layer 140 ). Fig. 14B Also shown is a conductive line 138 embedded in dielectric layer 140 and located on dielectric layer 132. It is worth noting that Fig. 14B The portion of the semiconductor package shown in FIG. 1 does not include a via 146V extending through the dielectric layer 140 (see FIG. 14A ). Fig.14A ).

[0056] In some embodiments, because bridging issues are reduced or avoided using an enhanced low voltage descum process 147, the thickness T4 of the conductor 146 can be formed to be greater than the thickness achievable when a POR descum process is used. Because the thickness T4 is larger, the width L2 of the conductor 146 can be formed to be smaller while still maintaining the same resistance (e.g., because the cross-sectional area of ​​the conductor 146 remains unchanged). In addition, the disclosed method also allows the pitch S2 between adjacent conductors 146 to be reduced compared to the pitch achievable when a POR descum process is used. The smaller width L2 and smaller pitch S2 of the conductor 146 allow for a higher level of wiring density without sacrificing electrical performance, or alternatively, allow for a higher level of electrical performance (e.g., lower resistance) at the same level of wiring density. Fig. 14B In the example of FIG. 1 , the width L2, thickness T4, and pitch S2 of the conductive line 146 are respectively smaller than the width L, thickness T1, and pitch S of the conductive line 138. In some embodiments, if a POR descum process is used to process the dielectric layer on which the redistribution layer is formed, then Fig. 14B The width L, thickness T1, and pitch S of the conductive line 138 shown in illustrative figures represent (eg, are the same as or similar to) the width, thickness, and pitch of conductive lines in the redistribution layer of the front-side redistribution structure 160, respectively.

[0057] Next, the same processing steps as forming the dielectric layer 140 and the metallization pattern 146 are repeated, such as Fig. 10A , Fig. 10B , Fig.11 , Fig. 12A , Fig. 12B , Fig.13 , Fig.14A and Fig. 14B As shown, additional layers of dielectric layers and additional layers of metallization patterns are formed to form the front side redistribution structure 160 .

[0058] exist Fig.15 , a dielectric layer 148 is deposited on the metallization pattern 146 and the dielectric layer 140. The dielectric layer 148 may be formed of the same material and using the same formation method as the dielectric layer 140, so the details are not repeated. The dielectric layer 148 may be formed to have a thickness equal to the sum of the target thickness of the dielectric layer 148 and the additional thickness (e.g., the additional thickness is between about 0.5 μm and about 3 μm).

[0059] Next, in Fig.16 In the embodiment, the dielectric layer 148 is patterned using the same or similar patterning process as discussed above for the dielectric layer 140 , so the details are not repeated. The patterning forms openings in the dielectric layer 148 to expose portions of the metallization pattern 146 .

[0060] Next, the enhanced low pressure descum process discussed above is performed to treat the dielectric layer 148. The enhanced low pressure descum process reduces the thickness of the dielectric layer 148 to its target thickness and produces a high surface roughness parameter Rq, for example, between about 7 nm and about 40 nm, of the dielectric layer 148. Next, the cleaning machine cleaning process discussed above is performed to remove particles generated by the enhanced low pressure descum process.

[0061] Next, in Fig.17 In the embodiment of the present invention, a metallization pattern 154 having a through hole is formed on the dielectric layer 148. For example, a seed layer (not shown) is formed above the dielectric layer 148 and in an opening passing through the dielectric layer 148. The seed layer has a low reflectivity (e.g., 15% or less). A photoresist is then formed on the seed layer and patterned. The pattern of the photoresist corresponds to the metallization pattern 154. The patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The remaining portion of the conductive material and the seed layer forms the metallization pattern 154 and the through hole. The through hole is formed in the opening through the dielectric layer 148 to, for example, a portion of the metallization pattern 146. The details are the same or similar to the metallization pattern 146 discussed above, and therefore are not repeated.

[0062] Next, in Fig.18 , a dielectric layer 156 is deposited on the metallization pattern 154 and the dielectric layer 148. In some embodiments, the dielectric layer 156 is formed of the same material (eg, polymer material) as the dielectric layer 140 using the same formation method, and thus the details are not repeated.

[0063] Next, in Fig.19 , patterning the dielectric layer 156. The patterning forms openings to expose portions of the metallization pattern 154. An enhanced low-pressure descumming process is performed to clean the openings, reduce the thickness of the dielectric layer 156 to its target thickness, and increase the surface roughness parameter Rq of the dielectric layer 156 to, for example, a range between about 7 nm and about 40 nm. Next, a scrubber cleaning process is performed to remove particles generated by the enhanced low-pressure descumming process. The details are similar to the scrubber cleaning process discussed above, and therefore will not be repeated.

[0064] Fig.19The front side redistribution structure 160 shown is a non-limiting example. More or fewer dielectric layers and metallization patterns may be formed in the front side redistribution structure 160. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed above may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed above may be repeated. One of ordinary skill in the art will readily understand which steps and processes may be omitted or repeated.

[0065] Next, in Fig. 20 In the embodiment, a pad 162 is formed on the outer side of the front redistribution structure 160. The pad 162 is used to couple to the conductive connection member 166 (see Fig.21 ), and the pad 162 can be referred to as under-bump metallization (UBM) 162. In the illustrated embodiment, the pad 162 is formed to extend through the opening in the dielectric layer 156 to the metallization pattern 154. As an example of forming the pad 162, a seed layer (not shown) is formed above the dielectric layer 156 and in the opening in the dielectric layer 156. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. For example, PVD, etc. can be used to form the seed layer. Then a photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating, etc., and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to the pad 162. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electroplating or chemical plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the conductive material and the seed layer forms a pad 162.

[0066] Next, in Fig.21In the embodiment of the present invention, a conductive connector 166 is formed on the UBM 162. The conductive connector 166 can be a BGA connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel plating-electroless palladium plating-immersion gold technology (ENEPIG), etc. The conductive connector 166 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 166 is formed by initially forming a solder layer by common methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into a desired bump shape. In another embodiment, the conductive connector 116 is a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the top of the metal column connector 166. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and the metal capping layer may be formed by a plating process.

[0067] Next, in Fig. 22 In the process, a carrier substrate release process is performed to separate (or "release") the carrier substrate 100 from the backside redistribution structure (e.g., dielectric layer 104). According to some embodiments, release includes projecting light, such as laser or ultraviolet light, onto release layer 102, so that release layer 102 decomposes under the heat of the light and carrier substrate 100 can be removed. The structure is then flipped over and placed on tape 190.

[0068] like Fig. 22 As further shown, openings are formed through the dielectric layer 104 to expose portions of the metallization pattern 106. For example, the openings may be formed using laser drilling, etching, or the like.

[0069] Next, a singulation process is performed by sawing along the scribe line regions (eg, between the adjacent regions 600 and 602 ). The sawing singulates the first package region 600 from the second package region 602 .

[0070] Fig.23 The resulting singulated package 200 is shown, which may originate from one of the first packaging region 600 or the second packaging region 602. The package 200 may also be referred to as an integrated fan-out (InFO) package 200.

[0071] Fig.24A package structure 500 is shown that includes a package 200 (also referred to as a first package 200 or a bottom package 200) and a second package 300 (also referred to as a top package 300). The second package 300 includes a substrate 302 and one or more stacked dies 308 (e.g., 308A and 308B) coupled to the substrate 302. Although a single stack of dies 308 (e.g., 308A and 308B) is shown, in other embodiments, multiple stacked dies 308 (each having one or more stacked dies) may be arranged side by side to be coupled to the same surface of the substrate 302.

[0072] exist Fig.24 In the embodiment, the substrate 302 can be made of semiconductor materials such as silicon, germanium, diamond, etc. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these, etc. can also be used. In addition, the substrate 302 can be a silicon on insulator (SOI) substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI) or a combination thereof. In an optional embodiment, the substrate 302 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Optional materials for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. An accumulation film such as Ajinomoto accumulation film (ABF) or other laminated materials can be used for the substrate 302.

[0073] The substrate 302 may include active devices and passive devices ( Fig.24 As will be appreciated by those of ordinary skill in the art, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, etc. may be used to meet the structural and functional requirements of the design for the second package 300. The devices may be formed using any suitable method.

[0074] The substrate 302 may also include metallization layers (not shown) and through-holes 306. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), wherein the through-holes interconnect the layers of conductive materials, and the metallization layers may be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). In some embodiments, the substrate 302 is substantially free of active and passive devices.

[0075] The substrate 302 may have bonding pads 303 on a first side of the substrate 302 to couple to the stacked die 308 and bonding pads 304 on a second side of the substrate 302 opposite to the first side of the substrate 302 to couple to the functional connectors 314 .

[0076] In the illustrated embodiment, the stacked die 308 is coupled to the substrate 302 via bond wires 310, but other connectors, such as conductive bumps, may be used. In an embodiment, the stacked die 308 is a stacked memory die. For example, the stacked memory die 308 may include a low power (LP) double data rate (DDR) memory module, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, etc. memory modules.

[0077] In some embodiments, the stacked die 308 and the bonding wires 310 may be encapsulated by a molding material 312. The molding material 312 may be molded on the stacked die 308 and the bonding wires 310, for example, using compression molding. In some embodiments, the molding material 312 is a molding compound, a polymer, an epoxy resin, a silicon oxide filling material, etc., or a combination thereof. A curing step may be performed to cure the molding material 312, wherein the curing may be a thermal curing, a UV curing, etc., or a combination thereof.

[0078] After forming the second package 300, the second package 300 is mechanically and electrically bonded to the first package 200 via the functional connectors 314, the bonding pads 304, and the metallization pattern 106. Although the functional connectors 314 and the conductive connectors 166 are not necessarily the same, the functional connectors 314 may be similar to the conductive connectors 166 described above, and will not be described again here.

[0079] The bond between the second package 300 and the first package 200 may be a solder bond. In an embodiment, the second package 300 is bonded to the first package 200 by a reflow process. During the reflow process, the functional connector 314 contacts the bonding pad 304 and the metallization pattern 106 to physically and electrically couple the second package 300 to the first package 200. After the bonding process, an intermetallic compound (IMC, not shown) may be formed at the interface of the metallization pattern 106 and the functional connector 314, and also at the interface between the functional connector 314 and the bonding pad 304 (not shown).

[0080] Modifications to the disclosed embodiments are possible and are fully intended to be included within the scope of the present disclosure. For example, in the embodiment discussed above for forming the front side redistribution structure 160, the dielectric layer 132 of the front side redistribution structure 160 is processed by a POR descum process, while the other dielectric layers (e.g., 140, 148, 156) of the front side redistribution structure 160 are processed by an enhanced low pressure descum process. This embodiment is suitable when the surface of the molding material 130 facing the front side redistribution structure 160 is a flat surface, in which case the recess depth R1 of the deposited dielectric layer 132 is very small, and the flat surface of the molding material 130 does not cause bridging problems (e.g., because the reflected light source is reflected directly upward).

[0081] As another example, however, if the surface of the molding material 130 facing the front side redistribution structure 160 has a molding pit (e.g., a micro cavity), the dielectric layer 132 and the metallization pattern 138 may be formed using the same processing steps as for the dielectric layer 140 and the metallization pattern 146. For example, after the openings are formed in the dielectric layer 132, the dielectric layer 132 may be processed using an enhanced low pressure descum process. In other words, both the dielectric layers 132 and 140 are deposited to a greater thickness (e.g., a target thickness plus an additional thickness) and are both processed using an enhanced low pressure descum process. For the remaining dielectric layers 148 and 156 in the front side redistribution structure 160, a criterion is used to determine whether to process each of the dielectric layers 148 and 156 using a POR descum process or an enhanced low pressure descum process. Examples of such criteria are based on the topography of the underlying metallization pattern on which the dielectric layer 148 (or 156) is formed and the target thickness of the dielectric layer 148 (or 156). For ease of discussion, reference is made to Fig. 10B , and assume that conductor 138 is the "underlying metallization pattern" of dielectric layer 148 (or 156), and assume that dielectric layer 140 is dielectric layer 148 (or 156). Using Fig. 10B In the symbol, if the ratio between the pitch S and the width L of the underlying conductive line is greater than 1 (e.g., S / L>1), and if the thickness T1 of the underlying conductive line is greater than or equal to the target thickness T2 of the portion of the dielectric layer 148 (or 156) directly above the underlying conductive line (e.g., T1≥T2), then an enhanced low-pressure descumming process is used for the dielectric layer 148 (or 156); otherwise, a POR descumming process is used.

[0082] Those skilled in the art will readily appreciate other variations of the disclosed embodiments. For example, depending on the flatness of the outer surface of the molding material 130 (e.g., whether the outer surface of the molding material 132 has molding pits), the POR descum process or the enhanced low-pressure descum process is used to process the dielectric layer 132. For each of the other dielectric layers (e.g., 140, 148, and 156), the criteria discussed above (e.g., S / L>1 and T1≥T2) are used to determine whether to use the POR descum process or the enhanced low-pressure descum process to process the dielectric layer. It should be noted that when a POR descum process is used to process a dielectric layer (e.g., 132, 140, 148, or 156), the size, shape, and physical properties (e.g., surface roughness, reflectivity, sidewall profile, foot size, wire thickness, and pitch between wires) of the components produced by or affected by the POR descum process have the same or similar values / properties as discussed above in the comparison between the POR descum process and the enhanced low-pressure descum process.

[0083] Embodiments of the devices and methods in the current disclosure have many advantages. The enhanced low-pressure descumming process not only cleans the openings in the dielectric layer, but also increases the surface roughness of the dielectric layer. Because of the increased surface roughness, the seed layer subsequently formed has a lower reflectivity, which reduces or alleviates the bridging problem. As a result, the device failure rate is reduced and the production yield is improved. The enhanced low-pressure descumming process also provides a better sidewall profile for the openings in the dielectric layer and reduces the width of the foot. Better sidewall profiles allow better overlay control, and smaller footing produces fewer stress-related problems (e.g., delamination, cracking). The disclosed criteria can be used to determine whether to use a POR descumming process (e.g., with a shorter process duration) or an enhanced low-pressure descumming process (e.g., with a longer process duration) for each dielectric layer of the redistribution structure. This ensures that the enhanced low-pressure descumming process is used for some dielectric layers only when needed, thereby reducing production time and cost, because the POR descumming process can be used for other dielectric layers to shorten production time.

[0084] Fig.25A and Fig.25B 1 and 2 show a flow chart of a method 1000 for forming a semiconductor package in an embodiment. It should be understood that Fig.25A and Fig.25B The embodiment methods shown in are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, the embodiments may be added, removed, replaced, rearranged, or repeated. Fig.25A and Fig.25B The steps shown in .

[0085] refer to Fig.25A and Fig.25B , at box 1010, a molding material is formed around the tube core. At box 1020, a first dielectric layer is formed over the molding material using a polymer material. At box 1030, the first dielectric layer is patterned to form a first plurality of openings in the first dielectric layer. At box 1040, after patterning the first dielectric layer, a first descum process is performed, wherein the first descum process is a first plasma process performed at a first pressure for a first duration. At box 1050, after performing the first descum process, a conductive material is formed in the first plurality of openings and over an upper surface of the first dielectric layer to form a first redistribution layer (RDL). At box 1060, a second dielectric layer is formed over the first dielectric layer using a polymer material. At box 1070, the second dielectric layer is patterned to form a second plurality of openings in the second dielectric layer. At block 1080, after patterning the second dielectric layer, a second descum process is performed, wherein the second descum process is a second plasma process performed at a second pressure for a second duration, wherein the second pressure is different from the first pressure, and the second duration is different from the first duration. At block 1090, after performing the second descum process, an electrically conductive material is formed in the second plurality of openings and over the upper surface of the second dielectric layer to form a second RDL.

[0086] According to an embodiment, a method of forming a semiconductor package includes: surrounding a die with a molding material; and forming a redistribution structure (RDS) over the molding material, and the redistribution structure is electrically coupled to the die, and forming the redistribution structure (RDS) includes: depositing a first dielectric layer over the molding material; patterning the first dielectric layer to form a first plurality of openings in the first dielectric layer; performing a first descum process to clean the first plurality of openings; after performing the first descum process, forming a first redistribution layer (RDL) on the first dielectric layer; depositing a second dielectric layer over the molding material; patterning the second dielectric layer to form a second plurality of openings in the second dielectric layer; performing a second descum process to clean the second plurality of openings, wherein the first descum process and the second descum process are performed under different process conditions; and after performing the second descum process, forming a second RDL on the second dielectric layer. In an embodiment, the first descum process is performed at a first pressure for a first duration under the first process condition, and the second descum process is performed at a second pressure for a second duration under the second process condition, wherein the first pressure is different from the second pressure, and the first duration is different from the second duration. In an embodiment, the second pressure is lower than the first pressure, and the second duration is longer than the first duration. In an embodiment, the second pressure is between about 30% and about 70% of the first pressure, and wherein the second duration is between about one and about five times the first duration. In an embodiment, the first dielectric layer and the second dielectric layer are formed of the same polymer material. In an embodiment, the first descum process causes the upper surface of the first dielectric layer away from the molding material to produce a first surface roughness parameter Rq, wherein the second descum process causes the upper surface of the second dielectric layer away from the molding material to produce a second surface roughness parameter Rq, wherein the second surface roughness parameter Rq is greater than the first surface roughness parameter Rq. In an embodiment, forming the first RDL includes forming a conductive material in a first plurality of openings and on the first dielectric layer, wherein forming the second RDL includes forming a conductive material in a second plurality of openings and on the second dielectric layer. In an embodiment, the conductive material on the first dielectric layer is formed to have a first thickness, and the conductive material on the second dielectric layer is formed to have a second thickness greater than the first thickness. In an embodiment, forming the RDS further includes: conformally forming a first seed layer in the first plurality of openings and on the first dielectric layer after performing a first descum process and before forming a first RDL, wherein forming the first RDL includes forming a conductive material on the first seed layer; and conformally forming a second seed layer in the second plurality of openings and on the second dielectric layer after performing a second descum process and before forming a second RDL, wherein forming the second RDL includes forming a conductive material on the second seed layer, wherein the first seed layer and the second seed layer are formed of the same material, wherein a second reflectivity of the second seed layer is lower than a first reflectivity of the first seed layer.In an embodiment, the first reflectivity is about 45% and the second reflectivity is about 15%. In an embodiment, the second dielectric layer is deposited before the first dielectric layer so that the second dielectric layer is between the molding material and the first dielectric layer. In an embodiment, the second dielectric layer is deposited after the first dielectric layer so that the first dielectric layer is between the molding material and the second dielectric layer.

[0087] According to an embodiment, a method for forming a semiconductor package includes: forming a molding material around a tube core; forming a first dielectric layer over the molding material using a polymer material; patterning the first dielectric layer to form a first plurality of openings in the first dielectric layer; after patterning the first dielectric layer, performing a first descum process, wherein the first descum process is a first plasma process performed at a first pressure and a first duration; after performing the first descum process, forming a conductive material in the first plurality of openings and over an upper surface of the first dielectric layer to form a first redistribution layer (RDL); forming a second dielectric layer over the first dielectric layer using a polymer material; patterning the second dielectric layer to form a second plurality of openings in the second dielectric layer; after patterning the second dielectric layer, performing a second descum process, wherein the second descum process is a second plasma process performed at a second pressure and a second duration, wherein the second pressure is different from the first pressure and the second duration is different from the first duration; and after performing the second descum process, forming a conductive material in the second plurality of openings and over an upper surface of the second dielectric layer to form a second RDL. In an embodiment, the second pressure is lower than the first pressure, and the second duration is longer than the first duration. In an embodiment, the second pressure is between about 30% and about 70% of the first pressure, and the second duration is between about one and about five times the first duration. In an embodiment, the first descum process causes a first surface roughness to be generated on the upper surface of the first dielectric layer, and the second descum process causes a second surface roughness to be generated on the upper surface of the second dielectric layer, wherein the second surface roughness is higher than the first surface roughness. In an embodiment, the method further includes: forming a first seed layer in the first plurality of openings and above the upper surface of the first dielectric layer after performing the first descum process and before forming a conductive material in the first plurality of openings, wherein the first seed layer has a first reflectivity; and forming a second seed layer in the second plurality of openings and above the upper surface of the second dielectric layer after performing the second descum process and before forming a conductive material in the second plurality of openings, wherein the second seed layer has a second reflectivity different from the first reflectivity.

[0088] According to an embodiment, a semiconductor package includes: a die; a molding material located around the die; and a redistribution structure (RDS) located at a first side of the molding material and electrically coupled to the die, the RDS including: a first dielectric layer in contact with and extending along the first side of the molding material, wherein a first surface of the first dielectric layer away from the molding material has a first surface roughness; a first redistribution layer (RDL) along the first surface of the first dielectric layer; a second dielectric layer along the first surface of the first dielectric layer and the first RDL, wherein a second surface of the second dielectric layer away from the molding material has a second surface roughness higher than the first surface roughness; and a second RDL along the second surface of the second dielectric layer. In an embodiment, the first RDL includes a first conductive line extending along the first surface of the first dielectric layer, wherein the second RDL includes a second conductive line extending along the second surface of the second dielectric layer, wherein a first thickness of the first conductive line is less than a second thickness of the second conductive line. In an embodiment, a via is laterally spaced apart from the die and embedded in the molding material, wherein the via is electrically coupled to the RDS.

[0089] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor package, the method comprising: surrounding the die with a molding material; as well as A redistribution structure is formed over the molding material and electrically coupled to the die, wherein forming the redistribution structure comprises: depositing a first dielectric layer over the molding material; patterning the first dielectric layer to form a first plurality of openings in the first dielectric layer; performing a first descum process to clean the first plurality of openings; After performing the first descum process, forming a first redistribution layer on the first dielectric layer; depositing a second dielectric layer over the molding material; patterning the second dielectric layer to form a second plurality of openings in the second dielectric layer; performing a second descum process to clean the second plurality of openings, wherein the first descum process and the second descum process are performed under different process conditions; and After performing the second descum process, a second redistribution layer is formed on the second dielectric layer.

2. The method according to claim 1, wherein: The first descum process is performed at a first pressure under first process conditions for a first duration, and the second descum process is performed at a second pressure under second process conditions for a second duration, wherein the first pressure is different from the second pressure and the first duration is different from the second duration.

3. The method according to claim 2, wherein: The second pressure is lower than the first pressure, and the second duration is longer than the first duration.

4. The method according to claim 3, wherein: The second pressure is between 30% and 70% of the first pressure, and wherein the second duration is between one and five times the first duration.

5. The method according to claim 4, wherein: The first dielectric layer and the second dielectric layer are formed of a same polymer material.

6. The method according to claim 3, wherein: The first descumming process causes the upper surface of the first dielectric layer away from the molding material to produce a first surface roughness parameter Rq, wherein the second descumming process causes the upper surface of the second dielectric layer away from the molding material to produce a second surface roughness parameter Rq, wherein the second surface roughness parameter Rq is greater than the first surface roughness parameter Rq.

7. The method according to claim 3, wherein: Forming the first redistribution layer includes forming a conductive material in the first plurality of openings and on the first dielectric layer, wherein forming the second redistribution layer includes forming the conductive material in the second plurality of openings and on the second dielectric layer.

8. The method according to claim 7, wherein: The conductive material on the first dielectric layer is formed to have a first thickness, and the conductive material on the second dielectric layer is formed to have a second thickness greater than the first thickness.

9. A method of forming a semiconductor package, the method comprising: forming a molding material around the die; forming a first dielectric layer over the molding material using a polymer material; patterning the first dielectric layer to form a first plurality of openings in the first dielectric layer; After patterning the first dielectric layer, performing a first descum process, wherein the first descum process is a first plasma process performed at a first pressure for a first duration; After performing the first descum process, forming a conductive material in the first plurality of openings and over an upper surface of the first dielectric layer to form a first redistribution layer; forming a second dielectric layer over the first dielectric layer using the polymer material; patterning the second dielectric layer to form a second plurality of openings in the second dielectric layer; After patterning the second dielectric layer, performing a second descum process, wherein the second descum process is a second plasma process performed at a second pressure for a second duration, wherein the second pressure is different from the first pressure, and the second duration is different from the first duration; and After performing the second descum process, the conductive material is formed in the second plurality of openings and over an upper surface of the second dielectric layer to form a second redistribution layer.

10. A semiconductor package, comprising: Die; a molding material disposed around the die; as well as a redistribution structure located at the first side of the molding material and electrically coupled to the die, the redistribution structure comprising: a first dielectric layer in contact with the first side of the molding material and extending along the first side of the molding material, wherein a first surface of the first dielectric layer away from the molding material has a first surface roughness; a first redistribution layer along the first surface of the first dielectric layer; a second dielectric layer along the first surface of the first dielectric layer and the first redistribution layer, wherein a second surface of the second dielectric layer away from the molding material has a second surface roughness higher than the first surface roughness; and A second redistribution layer is disposed along the second surface of the second dielectric layer.

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