Chip packaging structure and preparation method thereof

Abstract

The invention discloses a chip packaging structure and a preparation method thereof, and belongs to the technical field of chip packaging. The chip packaging structure comprises a substrate; the first heat dissipation layer is arranged on the substrate, and a first groove is formed in the first heat dissipation layer; a chip, wherein the chip is arranged in the first groove; the second heat dissipation layer is arranged on one side, close to the substrate, of the first heat dissipation layer; the sintering layer is arranged on the side, away from the substrate, of the second heat dissipation layer, and the material of the sintering layer comprises copper. According to the technical scheme of the invention, the problem of poor heat dissipation performance of a chip packaging structure in the prior art can be solved.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure and a preparation method thereof. Background Art

[0002] As people continue to pursue more complete functions of electronic products, the integration of integrated circuits is getting higher and higher, the number of chip I / Os is increasing, and the integration of system modules is also getting higher and higher. This forces the chip (IC) level packaging and circuit board (PCB) level packaging technology to be more and more closely linked, and thus embedded component packaging (Embedded component packaging) came into being. However, for GaN chips, the operating temperature is better, and better heat dissipation design is needed to exert their excellent performance.

[0003] In the current related technologies, the chip in the chip packaging structure mainly relies on thermal conductive glue, blind holes, insulated metal plates, or embedded copper layers for heat dissipation. However, compared with GaN chips, in the above-mentioned related technologies, the heat dissipation effect of the chip packaging structure cannot meet the operating temperature of the GaN chip, thereby affecting the normal operation of the chip and making it impossible for the chip to exert its higher power density. In addition, in the current related technologies, the heat dissipation path in the chip packaging structure is a vertical heat dissipation path, that is, a heat dissipation path from the top of the chip packaging structure to the bottom of the chip packaging structure.

[0004] However, in the GaN chip packaging structure, a resin layer is provided around the GaN chip to protect the chip. However, due to the low thermal conductivity of the resin layer, the chip packaging structure in the related art cannot achieve three-dimensional efficient heat dissipation of the chip. Summary of the invention

[0005] The present application provides a chip packaging structure, aiming to solve the problem of poor heat dissipation of the chip packaging structure in the related art.

[0006] In a first aspect, the present application provides a chip packaging structure, including:

[0007] substrate;

[0008] A first heat dissipation layer, wherein the first heat dissipation layer is disposed on the substrate and a first groove is disposed on the first heat dissipation layer;

[0009] a second heat dissipation layer, the second heat dissipation layer being arranged on a side of the first heat dissipation layer close to the substrate;

[0010] a sintered layer, the sintered layer being arranged on a side of the second heat dissipation layer away from the substrate;

[0011] Wherein, the material of the sintered layer includes copper.

[0012] In some embodiments, a second groove is provided on a side of the sintering layer away from the second heat dissipation layer, and the first heat dissipation layer is located in the second groove;

[0013] And / or, a third groove is provided on a side of the second heat dissipation layer away from the substrate, and the sintered layer is located in the third groove.

[0014] In some embodiments, the chip packaging structure further includes: a first heat-conducting layer, a conductive portion, and a second heat-conducting layer; the conductive portion is disposed between the substrate and the first heat-conducting layer;

[0015] The first heat-conducting layer is disposed between the conductive portion and the second heat-conducting layer;

[0016] The second heat-conducting layer includes a first heat-conducting portion and a second heat-conducting portion. The first heat-conducting portion is arranged at a side of the chip away from the second heat-conducting layer; and the second heat-conducting portion is arranged between the first heat-conducting portion and the substrate.

[0017] In some embodiments, the chip packaging structure further includes:

[0018] A plurality of pads, wherein the plurality of pads are respectively arranged on a surface of the chip on a side away from the first heat conducting layer; and / or the material of the pads is copper;

[0019] A conductive layer, the conductive layer is arranged on a side of the second heat-conducting layer away from the chip; at least one conductive column is arranged on a side of the conductive layer close to the second heat-conducting layer;

[0020] The conductive column is electrically connected to the pad, and an orthographic projection of the conductive column on the substrate coincides with an orthographic projection of the pad on the substrate.

[0021] In some embodiments, the chip packaging structure further includes:

[0022] A first solder resist layer, wherein the first solder resist layer is arranged on a side of the substrate away from the chip;

[0023] The first solder resist layer is provided with a first through hole, and the orthographic projection of the first through hole on the substrate covers the orthographic projection of the second heat conducting layer on the substrate;

[0024] and / or,

[0025] A second solder resist layer, wherein the second solder resist layer is arranged on a side of the conductive layer away from the chip;

[0026] A second through hole is provided on the second solder resist layer, and an orthographic projection of the second through hole on the substrate covers an orthographic projection of the chip on the substrate.

[0027] In some embodiments, the chip packaging structure further includes:

[0028] A first anti-oxidation layer, wherein the first anti-oxidation layer is disposed on a side of the substrate away from the chip and is located in the first through hole;

[0029] and / or,

[0030] A second anti-oxidation layer is disposed on a side of the conductive layer away from the chip and is located in the second through hole.

[0031] In some embodiments, the length range of the chip is [3um, 10um]; the width range of the chip is [2um, 10um]; the height range of the chip is [200um, 500um].

[0032] In some embodiments, the length range of the third groove is [53um, 60um]; the width range of the third groove is [52um, 60um]; the height range of the third groove is [200um, 500um].

[0033] In some embodiments, the material of the first heat-conducting layer includes: copper; and / or the material of the second heat-conducting layer includes: copper.

[0034] In the embodiment of the present application, the material of the sintered layer can be copper. This arrangement allows the heat generated by the chip during operation to be transferred to the substrate through the first heat dissipation layer with high thermal conductivity, the sintered layer, and the second heat dissipation layer, thereby achieving efficient heat dissipation.

[0035] In addition, in the embodiment of the present application, a first groove is provided on the first heat dissipation layer, and the chip is located in the first groove. This arrangement of arranging the chip in the first groove allows the heat generated by the first heat dissipation layer to the chip to be dissipated in multiple directions from the side walls and bottom walls of the groove, thereby achieving three-dimensional efficient heat dissipation of the chip packaging structure.

[0036] In a second aspect, the present application also provides a method for preparing a chip packaging structure, comprising:

[0037] Using a magnetron sputtering process, a first heat dissipation layer is formed on the bottom and sides of the chip;

[0038] Using copper blocks to make a second heat dissipation layer;

[0039] The sintering material filled between the first heat dissipation layer and the second heat dissipation layer is sintered by a pressureless sintering process to form a sintered layer; wherein the material of the sintered layer includes copper. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0041] Figure 1A A structural schematic diagram of a chip packaging structure provided for related technology 1.

[0042] Figure 1B A structural schematic diagram of a chip packaging structure provided for related technology 2.

[0043] Figure 1C A structural schematic diagram of a chip packaging structure provided for related technology 3.

[0044] Figure 1D A structural schematic diagram of a chip packaging structure provided for related technology 4.

[0045] Figure 1E A partial structural schematic diagram of a chip packaging structure provided for related technology 5.

[0046] Figure 1F A schematic diagram of the chip packaging structure provided for related technology.

[0047] Figure 1G A schematic diagram of the heat dissipation principle of a chip packaging structure provided for related technologies.

[0048] Figure 1 A schematic diagram of the structure of a chip packaging structure provided in this application.

[0049] Figure 2 A partial flow chart of a method for preparing a chip packaging structure provided in the present application.

[0050] Figure 3 A schematic diagram of a process for preparing a chip packaging structure provided in the present application.

[0051] Figure 4A to Figure 4O A schematic diagram of a process of preparing a chip packaging structure provided in the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0053] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0054] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0055] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0056] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0057] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0058] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0059] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0060] At present, with people's continuous pursuit of more perfect functions of electronic products, the integration of integrated circuits is getting higher and higher, the number of chip I / Os is increasing, and the integration of system modules is also getting higher and higher, which makes the connection between chip (IC) level packaging and circuit board (PCB) level packaging technology closer and closer.

[0061] Therefore, embedded component packaging came into being. However, since the temperature of GaN chips is relatively high during operation, better heat dissipation design is needed to exert their excellent performance.

[0062] The current mainstream heat dissipation path only focuses on the top and bottom of the chip for vertical heat dissipation. For embedded three-dimensional packaging, the resin layer around the side of the chip also accumulates a lot of heat.

[0063] For example, Figure 1A A schematic diagram of a chip packaging structure provided by related technology 1, Figure 1B A schematic diagram of a chip packaging structure provided by related technology 2, Figure 1C A schematic diagram of a chip packaging structure provided by related technology 3, Figure 1D A schematic diagram of a chip packaging structure provided by related technology 4, Figure 1E A schematic diagram of a chip packaging structure provided by related technology 5, such as Figure 1A As shown, in related art 1,

[0064] The chip packaging structure includes a substrate, a thermally conductive adhesive 2A, and a chip 1A. The chip 1A is bonded to the substrate through the thermally conductive adhesive 2A. The heat generated by the chip 1A during operation is transferred to the substrate through the thermally conductive adhesive 2A for heat dissipation. Furthermore, the thermal conductivity of the thermally conductive adhesive is in the range of [0.6W / (m·K), 1.5W / (m·K)]. For example, in one example, the thermal conductivity of the thermally conductive adhesive is 0.6W / (m·K), 0.9W / (m·K), 1W / (m·K), 1.2W / (m·K), and 1.5W / (m·K).

[0065] In the related art 2, Figure 1B As shown, the chip packaging structure includes a substrate, a plurality of blind vias Va, and a chip 1B. The chip 1B is connected to the substrate through the blind vias Va. Further, a dielectric material is provided in the blind vias Va, and the thermal conductivity of the dielectric material is 0.6W / (m·K). The heat generated by the chip 1B during operation is transferred to the substrate through the dielectric material in the blind vias Va for heat dissipation.

[0066] In related art 3, Figure 1C As shown, Figure 1CAs shown, the chip packaging structure includes an insulated metal substrate IMS, (Insulated Metal Substrate), a gate driver board GDB, (Gate Driver Board), and a chip 3A. The heat generated by the chip 3A during operation is dissipated through the insulated metal substrate IMS.

[0067] In the related art 4, Figure 1D As shown, the chip packaging structure includes a base plate, a base plate DBC, and a chip GaN Device, wherein the chip GaN Device is arranged on the base plate DBC, and the heat generated by the chip GaN Device during operation is conducted to the base plate through the base plate DBC, and the heat is dissipated through the base plate DBC and the base plate.

[0068] In related art 5, Figure 1E As shown, the chip packaging structure includes a chip (not shown) and a copper block 5B, wherein the chip is welded or bonded to the upper part of the copper block 5B, and the heat generated by the chip during operation is dissipated through the copper block 5B.

[0069] In summary, in the current related technologies, the chip in the chip packaging structure mainly relies on thermal conductive adhesive, blind holes, insulating metal plates, or copper blocks for heat dissipation. However, compared with GaN chips, the heat dissipation effect of the chip packaging structure in the above-mentioned related technologies cannot meet the operating temperature of the GaN chip, thereby affecting the normal operation of the chip and making it unable to exert its higher power density.

[0070] In addition, in the current related technology, the heat dissipation path in the chip packaging structure is a vertical heat dissipation path, that is, a heat dissipation path from the top of the chip packaging structure to the bottom of the chip packaging structure.

[0071] However, in the GaN chip packaging structure, a resin layer is provided around the GaN chip to protect the chip. However, due to the low thermal conductivity of the resin layer, the chip packaging structure in the related art cannot achieve three-dimensional efficient heat dissipation of the chip.

[0072] The following is an analysis of the heat dissipation path and heat dissipation performance of the chip packaging structure in related technologies 1-5 based on the principles:

[0073] Figure 1F A schematic diagram of a chip packaging structure provided for related technologies, Figure 1G A schematic diagram of the heat dissipation principle of the chip packaging structure provided for related technologies, such as Figure 1F and Figure 1G As shown, the chip packaging structure includes: a chip 6A and a PCB board 6B, wherein the chip 6A is arranged on the PCB board 6B.

[0074] refer to Figure 1F and Figure 1G It can be seen that T C is the temperature of the chip package surface; T B is the temperature of the PCB surface when chip 6A is installed; T A is the external environment temperature; T J is the temperature of the transistor junction inside the chip; P is the chip power.

[0075] The thermal resistance formula from chip to package layer is:

[0076]

[0077] The thermal resistance formula from chip to PCB is:

[0078]

[0079] In summary, in the current related technologies, the heat dissipation path in the chip packaging structure is a vertical heat dissipation path, that is, a heat dissipation path from the top of the chip packaging structure to the bottom of the chip packaging structure. The thermal resistance formula is as described above.

[0080] Figure 1 A schematic diagram of a chip packaging structure provided in this application is shown in FIG. Figure 1 As shown, the chip packaging structure includes: a substrate 1, a chip 2, a first heat dissipation layer 3, a second heat dissipation layer 4, and a sintering layer 5. The first heat dissipation layer 3 is arranged on the substrate 1, and a first groove V1 is arranged on the first heat dissipation layer 3, and the chip 2 is arranged in the first groove V1. Further, the chip 2 can be a GaN chip. The second heat dissipation layer 4 is arranged on a side of the first heat dissipation layer 3 close to the substrate 1.

[0081] The sintered layer 5 is disposed on the side of the second heat dissipation layer 4 away from the substrate 1 , and the material of the sintered layer 5 includes copper. In the embodiment of the present application, the thermal conductivity of the sintered layer 5 is as high as 200 W / (m·K), which can efficiently dissipate heat for the chip 2 .

[0082] In the embodiment of the present application, the material of the sintered layer 5 can be copper. This arrangement allows the heat generated by the chip 2 during operation to be conducted to the substrate 1 through the first heat dissipation layer 3 with high thermal conductivity, the sintered layer 5, and the second heat dissipation layer 4, thereby achieving efficient heat dissipation.

[0083] In addition, in the embodiment of the present application, a first groove V1 is provided on the first heat dissipation layer 3, and the chip 2 is located in the first groove V1. This arrangement of arranging the chip 2 in the first groove V1 allows the first heat dissipation layer 3 to dissipate the heat generated by the chip 2 from the side walls and bottom walls of the first groove V1 in multiple directions, thereby achieving three-dimensional efficient heat dissipation of the chip packaging structure. Compared with the chip packaging structure provided in the related art, the chip packaging structure provided in the present application has a better heat dissipation effect.

[0084] Of course, in another embodiment, the materials of the first heat dissipation layer 3, the second heat dissipation layer 4, and the sintering layer 5 can all be copper. For example, the first heat dissipation layer 3 is a first copper layer, the second heat dissipation layer 4 is a second copper layer, and the sintering material used in the sintering layer 5 is copper paste. This arrangement allows the heat generated by the chip 2 during operation to be conducted to the substrate 1 through the first copper layer, the sintering layer 5, and the second copper layer having high thermal conductivity, thereby achieving efficient heat dissipation.

[0085] Preferably, when the chip in the chip packaging structure is a GaN chip, since the source Source, gate Gate, and drain Drain of the GaN chip are all arranged on the surface of the GaN chip, the chip packaging structure provided in the embodiment of the present application is more suitable for efficient three-dimensional heat dissipation of the GaN chip.

[0086] In some embodiments, a second groove V2 is provided on the side of the sintered layer 5 away from the second heat dissipation layer 4, and the first heat dissipation layer 3 is located in the second groove V2; and / or a third groove V3 is provided on the side of the second heat dissipation layer 4 away from the substrate 1, and the sintered layer 5 is located in the third groove V3.

[0087] In the present application, a first groove V1, a second groove V2, and a third groove V3 are respectively arranged on the first heat dissipation layer 3, the sintered layer 5, and the second heat dissipation layer 4, and the chip is arranged in the first groove V1, the sintered layer is arranged in the second groove V2, and the second heat dissipation layer 4 is arranged in the third groove V3. This arrangement can conduct the heat generated by the chip during operation to the outside through the side walls and bottom walls of the first groove V1, the second groove V2, and the third groove V3 in sequence, thereby realizing three-dimensional heat dissipation of the chip.

[0088] In some embodiments, the chip packaging structure further includes: a first heat conducting layer 7 , a conductive portion 20 , and a second heat conducting layer 8 , wherein the conductive portion 20 is disposed between the substrate 1 and the first heat conducting layer 7 ; and the first heat conducting layer 7 is disposed between the conductive portion 20 and the second heat conducting layer 8 .

[0089] The second heat conducting layer 8 includes a first heat conducting portion 80 and a second heat conducting portion 81 connected as one body. The first heat conducting portion 80 is arranged on a side of the chip 2 away from the second heat dissipation layer 4 , and the second heat conducting portion 81 is arranged between the first heat conducting portion 80 and the substrate 1 .

[0090] Furthermore, the materials of the first heat-conducting layer 7 and the second heat-conducting layer 8 may be the same or different. For example, in the embodiment of the present application, the material of the first heat-conducting layer 7 includes: BT resin; the material of the second heat-conducting layer 8 includes: BT resin.

[0091] Furthermore, the second heat conducting layer 8 includes a first heat conducting portion 80 and a second heat conducting portion 81 . The first heat conducting portion 80 is arranged on a side of the chip 2 away from the second heat conducting layer 4 , and the second heat conducting portion 81 is arranged between the first heat conducting layer 7 and the second heat dissipation layer 4 .

[0092] In some embodiments, the chip packaging structure further includes: a plurality of pads 13 and a conductive layer 9. The plurality of pads 13 are respectively arranged on the surface of the chip 2 away from the first heat conducting layer 3; and / or the pads 13 are made of copper.

[0093] The conductive layer 9 is arranged on the side of the second thermal conductive layer 80 away from the chip 2, and at least one conductive column 14 is arranged on the side of the conductive layer 9 close to the second thermal conductive layer 80; the conductive column 14 is electrically connected to the pad, and the orthographic projection of the conductive column 14 on the substrate coincides with the orthographic projection of the pad on the substrate.

[0094] In the embodiment of the present application, the chip 2 performs electrical transmission with the outside world through the electrical connection between the pad 13 and the conductive layer 9 .

[0095] In some embodiments, the chip packaging structure further includes: a first solder resist layer 10 and / or a second solder resist layer 11;

[0096] The first solder resist layer 10 is disposed on a side of the substrate 1 away from the chip 2, and the first solder resist layer 10 is provided with a first through hole V4, and the orthographic projection of the first through hole V4 on the substrate 1 covers the orthographic projection of the second heat conducting layer 4 on the substrate 1;

[0097] The second solder resist layer 10 is disposed on a side of the conductive layer 9 away from the chip 2 .

[0098] A second through hole V5 is provided on the second solder resist layer 11 , and the orthographic projection of the second through hole V5 on the substrate 1 covers the orthographic projection of the chip 2 on the substrate 1 .

[0099] In some embodiments, the chip packaging structure further includes: a first anti-oxidation layer 16, and / or a second anti-oxidation layer 17. The first anti-oxidation layer 16 is disposed on a side of the substrate 1 away from the chip 2 and is located in the first through hole V4.

[0100] Furthermore, the orthographic projection of the first anti-oxidation layer 16 on the substrate 1 coincides with the orthographic projection of the first through hole V4 on the substrate 1 .

[0101] And / or, the second anti-oxidation layer 17 is disposed on a side of the conductive layer 9 close to the chip 2 and is located in the second through hole V5.

[0102] Furthermore, the orthographic projection of the second anti-oxidation layer 17 on the substrate 1 coincides with the orthographic projection of the second through hole V5 on the substrate 1 .

[0103] In some embodiments, the length of the chip 2 ranges from [3 μm, 10 μm]; the width of the chip 2 ranges from [2 μm, 10 μm]; and the height of the chip 2 ranges from [200 μm, 500 μm].

[0104] For example, the length of chip 2 can be 3μm, 5μm, 7μm, 9μm, 10μm; the width of chip 2 can be 2μm, 4μm, 6μm, 8μm, or 10μm; the height of chip 2 can be 200μm, 250μm, 300μm, 350μm, 400μm, or 500μm.

[0105] In some embodiments, the length range of the third groove V3 is [53 μm, 60 μm]; the width range of the third groove V3 is [52 μm, 60 μm]; the height range of the third groove V3 is [200 μm, 500 μm].

[0106] For example, the length L1 of the third groove V3 may be 53μm, 55μm, 58μm, or 60μm; the width L3 of the third groove V3 may be 52μm, 53μm, 55μm, 58μm, or 60μm; the height L2 of the third groove V3 may be 200μm, 300μm, 400μm, 450μm, or 500μm.

[0107] Furthermore, the groove bottom thickness L4 of the third groove is 0.1 mm.

[0108] In some embodiments, the material of the first heat-conducting layer 7 includes copper; and / or, the material of the second heat-conducting layer 8 includes copper; and / or, the material of the first heat-dissipating layer 3 includes copper; and / or, the material of the second heat-dissipating layer 4 includes copper. For example, in one example, the material of the first heat-conducting layer 7 is copper and the material of the second heat-conducting layer 8 is copper.

[0109] Figure 2 A partial flow chart of a method for preparing a chip packaging structure provided in this application, such as Figure 2 As shown, the preparation method comprises:

[0110] S10, forming a first heat dissipation layer provided with a first groove on the bottom and side of the chip by using a magnetron sputtering process;

[0111] S20, using a copper block to make a second heat dissipation layer;

[0112] S30, using a pressureless sintering process to sinter the sintering material filled between the first heat dissipation layer and the second heat dissipation layer to form a sintered layer; wherein the material of the sintered layer includes copper.

[0113] On the basis of the above embodiments, the present application also provides a specific embodiment of a method for preparing a chip packaging structure, wherein: Figure 3 A schematic diagram of a process for preparing a chip packaging structure provided in this application, Figure 4A to Figure 4O A schematic diagram of a process for preparing a chip packaging structure provided in this application, such as Figure 3 as well as Figure 4A to Figure 4O As shown, the method includes:

[0114] S1. Using a magnetron sputtering process, a titanium layer and a copper layer are sputtered on the bottom and side of the chip in sequence to form a first heat dissipation layer. The chip may be a GaN chip.

[0115] Furthermore, a pad is provided on the chip, and the upper surface of the pad is not higher than the upper surface of the passivation layer on the surface of the chip 2. This arrangement can prevent short circuit problems when the chip 2 is side-sputtered.

[0116] For example, in one example, a 0.1 μm Ti layer and a 4 μm copper layer (first heat dissipation layer) are sequentially sputtered on the back side of the substrate of the chip 2 (the substrate is generally a Si substrate) by magnetron sputtering for interconnection in the back-end sintering process, thereby improving interlayer reliability.

[0117] Then, sputtering is performed on the side (left and right sides) of the chip 2 by magnetron sputtering: the chip 2 with the first heat dissipation layer is placed on the magnetron sputtering platform so that it is perpendicular to the sputtering surface, and a 0.1μm Ti layer and a 4μm copper layer (second heat dissipation layer 4) are formed on the side of the chip 2 with the first heat dissipation layer.

[0118] S2. Use a pressureless sintering process to sinter the first heat dissipation layer and the second heat dissipation layer 4; use a dispensing process to fill the sintering material between the chip and the substrate to form a sintering layer, and obtain a sample.

[0119] In the pressureless sintering process, the thickness of the copper film can be directly attached to the second heat dissipation layer 4 to be approximately 75 μm, and the sintering conditions are: baking at 250° C. for 3 hours without oxygen (under nitrogen atmosphere). In this way, the sintered layer can have good flatness.

[0120] Alternatively, the nano copper paste may be placed on the second heat dissipation layer 4 by screen printing or dispensing. At this time, the thickness of the nano copper paste needs to be kept at approximately 100 μm.

[0121] The GaN chip 2 processed as above is attached to the second heat dissipation film, and the pad of the GaN chip 2 is located at the side away from the substrate. This arrangement can make the offset tolerance of the GaN chip 2 ≤ 10 μm.

[0122] It should be noted that in the pressureless sintering process, the gap between the first heat dissipation layer and the second heat dissipation layer 4 is filled with nano copper paste through the dispensing process, and the copper paste is not higher than the surface of the second heat dissipation layer 4 away from the substrate, thereby preventing short circuit.

[0123] S3, pressing the first heat-conducting layer and the copper layer on the PCB substrate to form a pressing layer, and forming an unclosed groove on the pressing layer by using a laser.

[0124] Furthermore, the total thickness of the lamination layer is related to the height of the chip 2 and the thickness of the bottom of the second groove V2.

[0125] For example, in the embodiment of the present application, the total thickness range of the lamination layer is: L2+L4+30 μm, where L2 is the height of the chip 2, and its value range is [200 μm, 500 μm], and L4 (L4=0.1 mm) is the bottom thickness of the third groove V3.

[0126] Furthermore, in the present application, UV laser is used to ablate a predetermined area of ​​the lamination layer to form a non-enclosed groove.

[0127] S4. An adhesive layer 30 is provided on a side of the copper layer away from the first heat conducting layer, and a surface of the sample away from the chip 2 is bonded to a surface of the adhesive layer 30 close to the copper layer.

[0128] Furthermore, the bonding layer 30 may be a PI high temperature tape to support the embedded second heat dissipation layer 4, and the adhesive function of the PI high temperature tape is used to prevent the embedded second heat dissipation layer 4 from being displaced during the bonding process.

[0129] In the embodiment of the present application, the deviation accuracy of sample bonding is ≤10 μm.

[0130] S5. Form a second heat-conducting layer on a side of the chip away from the substrate; wherein the second heat-conducting layer includes a first heat-conducting portion and a second heat-conducting portion, the first heat-conducting portion is arranged on a side of the chip away from the second heat-conducting layer; and the second heat-conducting portion is arranged between the first heat-conducting layer and the second heat-conducting layer.

[0131] The step of forming a second heat-conducting layer on the side of the chip 2 away from the substrate further includes: laminating the second heat-conducting layer and the pressing layer, wherein the thickness of the second heat-conducting layer is 100 μm.

[0132] Of course, the user can make a reasonable selection of the thickness of the second thermal conductive layer based on the width and height of the unclosed groove, so as to prevent reliability risks such as lack of glue around the second thermal conductive layer after lamination.

[0133] S6. Using laser technology, form at least one through hole on a side of the second heat conducting layer away from the chip.

[0134] Utilizing CO 2 The laser ablates the second heat-conducting layer above the pad of the chip 2 to form at least one through hole for subsequent electroplating of the conductive column 14 .

[0135] In CO 2 During the process of laser ablating the second heat-conducting layer above the pad of the chip 2 , the pad on the chip 2 must not be penetrated, otherwise the chip 2 will fail.

[0136] S7. A conductive layer 9 is disposed on a side of the second heat-conducting layer away from the chip, and at least one conductive column is disposed on a side of the conductive layer 9 close to the second heat-conducting layer.

[0137] Through horizontal desmearing, horizontal hole forming, VCP hole filling and other process means, a conductive layer 9 above the second heat conductive layer and a conductive column 14 for connecting the chip pad are formed.

[0138] S8. The conductive column is electrically connected to the pad of the chip through the through hole, and the orthographic projection of the conductive column on the substrate coincides with the orthographic projection of the pad on the substrate.

[0139] S9, forming a first solder resist layer on a side of the substrate away from the chip, and / or forming a second solder resist layer on a side of the conductive layer 9 away from the second heat conducting layer.

[0140] Based on the above steps, a first solder resist layer is formed on the side of the substrate away from the chip 2, and / or a second solder resist layer is formed on the side of the conductive layer 9 away from the second heat conducting layer, thereby forming a chip packaging structure.

[0141] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A first heat dissipation layer, wherein the first heat dissipation layer is disposed on the substrate and a first groove is disposed on the first heat dissipation layer; a chip, wherein the chip is arranged in the first groove; a second heat dissipation layer, the second heat dissipation layer being arranged on a side of the first heat dissipation layer close to the substrate; A sintered layer is disposed on a side of the second heat dissipation layer away from the substrate; wherein the material of the sintered layer includes copper.

2. The chip packaging structure according to claim 1, characterized in that: A second groove is provided on a side of the sintered layer away from the second heat dissipation layer, and the first heat dissipation layer is located in the second groove; And / or, a third groove is provided on a side of the second heat dissipation layer away from the substrate, and the sintered layer is located in the third groove.

3. The chip packaging structure according to claim 1, characterized in that: Also includes: A first heat-conducting layer, a conductive portion, and a second heat-conducting layer; the conductive portion is disposed between the substrate and the first heat-conducting layer; The first heat-conducting layer is disposed between the conductive portion and the second heat-conducting layer; The second heat-conducting layer includes a first heat-conducting portion and a second heat-conducting portion connected as one body, the first heat-conducting portion is arranged at a side of the chip away from the second heat-dissipating layer, and the second heat-conducting portion is arranged between the first heat-conducting portion and the substrate.

4. The chip packaging structure according to claim 3, characterized in that: Also includes: A plurality of pads, wherein the plurality of pads are respectively arranged on a surface of the chip away from the first heat conducting layer; And / or, the material of the pad is copper; A conductive layer, the conductive layer is arranged on a side of the second heat-conducting layer away from the chip; at least one conductive column is arranged on a side of the conductive layer close to the second heat-conducting layer; The conductive column is electrically connected to the pad, and an orthographic projection of the conductive column on the substrate coincides with an orthographic projection of the pad on the substrate.

5. The chip packaging structure according to claim 4, characterized in that: Also includes: A first solder resist layer, wherein the first solder resist layer is arranged on a side of the substrate away from the chip; The first solder resist layer is provided with a first through hole, and the orthographic projection of the first through hole on the substrate covers the orthographic projection of the second heat conducting layer on the substrate; and / or, A second solder resist layer, wherein the second solder resist layer is arranged on a side of the conductive layer away from the chip; A second through hole is provided on the second solder resist layer, and an orthographic projection of the second through hole on the substrate covers an orthographic projection of the chip on the substrate.

6. The chip packaging structure according to claim 5, characterized in that: Also includes: A first anti-oxidation layer, wherein the first anti-oxidation layer is disposed on a side of the substrate away from the chip and is located in the first through hole; and / or, A second anti-oxidation layer is disposed on a side of the conductive layer away from the chip and is located in the second through hole.

7. The chip packaging structure according to claim 1, characterized in that: The length range of the chip is [3um, 10um]; the width range of the chip is [2um, 10um]; the height range of the chip is [200um, 500um].

8. The chip packaging structure according to claim 2, characterized in that: The length range of the third groove is [53um, 60um]; the width range of the third groove is [52um, 60um]; the height range of the third groove is [200um, 500um].

9. The chip packaging structure according to claim 3, characterized in that: The material of the first heat-conducting layer includes: copper; and / or the material of the second heat-conducting layer includes: copper; And / or, the material of the first heat dissipation layer includes copper; and / or, the material of the second heat dissipation layer includes copper.

10. A method for preparing a chip packaging structure, characterized in that: include: Using a magnetron sputtering process, a first heat dissipation layer is formed on the bottom and sides of the chip; Using copper blocks to make a second heat dissipation layer; The sintering material filled between the first heat dissipation layer and the second heat dissipation layer is sintered by a pressureless sintering process to form a sintered layer; wherein the material of the sintered layer includes copper.

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